CN207586101U - A kind of cytoanalyze that can synchronize storage multiplex pulse data - Google Patents
A kind of cytoanalyze that can synchronize storage multiplex pulse data Download PDFInfo
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Abstract
A kind of cytoanalyze that can synchronize storage multiplex pulse data, wherein, including:Light source production module, multiple optical signal receiver modules, multiple signal processing modules, multiple ADC acquisition modules, FPGA module and DDR storage modules；The optical signal receiver module, signal processing module and ADC acquisition module quantity are equal；The optical signal receiver module, signal processing module, ADC acquisition modules, FPGA module and DDR storage modules are sequentially connected electrically.Cytoanalyze provided by the utility model, microcontroller is replaced with FPGA module, using the logical resource that the parallel processing manner and FPGA of FPGA are abundant, multi-path digital pulse data is corresponded to using multiple data synchronisation units, realizes the synchronous storage of multi-path digital pulse data.
Description
Technical field
The utility model is related to a kind of cytoanalyzes, and in particular to be it is a kind of can synchronous storage multiplex pulse data
Cytoanalyze.
Background technology
In blood cell Medical Instruments, generally require the information such as the volume to cell, internal structure and analyze, these information
It is the key index for influencing Hematometer performance.The common cell measurement method of Hematometer -- laser scattering method at present, when laser shines
When being mapped to cell particle, multiple optical signal receivers are placed in 0~90 ° of range different angle of cell, need to believe multiple light
Algorithm is uploaded to after number synchronizing storage, ensures no loss of data, it can be needed for algorithm platform normal assay cell
The feature wanted.
Existing multichannel data storage mode is mainly based upon the serial storage mode of microcontroller architecture, and this mode can
To use a piece of DDR (Double Data Rate, Double Data Rate synchronous DRAM) particles or use simultaneously more
Piece DDR storage modules are stored, but the prior art has some limitations：(1) a piece of DDR based on microcontroller architecture
Storage module storage mode, can only time-dividing storage, it is impossible to synchronous storage multichannel data；(2) multi-disc based on microcontroller architecture
The storage mode of DDR storage modules (corresponding multichannel data), due to the serial processing mode of microcontroller, is actually not achieved synchronization
The purpose of storage, and additionally increase hardware cost；(3) the serial storage mode based on microcontroller architecture, multichannel data are deposited
Storing up sart point in time, there are deviations, and when the message transmission rate of processing is faster, storage sart point in time deviation is bigger, may lead
Cause the loss of data.
Therefore, the prior art could be improved and improve.
Utility model content
The purpose of this utility model is to provide a kind of cytoanalyzes that can synchronize storage multiplex pulse data, it is intended to solve
Certainly serial storage mode of the cytoanalyze based on microcontroller architecture can not realize that multiplex pulse data synchronize in the prior art
The problem of storage.
A kind of cytoanalyze that can synchronize storage multiplex pulse data, wherein, including:It is one light source production module, more
A optical signal receiver module, multiple signal processing modules, multiple ADC (Analog-to-Digital Converter, modulus
Conversion) acquisition module, FPGA (Field-Programmable Gate Array, field programmable gate array) module and
One DDR storage module；The optical signal receiver module, signal processing module and ADC acquisition module quantity are equal；The light
Signal receiver module, signal processing module, ADC acquisition modules, FPGA module and DDR storage modules are sequentially connected electrically；
The light source production module is arranged on the side of the cell of cytoanalyze, for generating constant optical signal；
The optical signal receiver module is arranged on the opposite side of the cell of cytoanalyze, the optical signal receiver mould
Block is equipped with multiple；One optical signal receiver module receives the optical signal across an angle of cell, and by the light of the angle
Signal is converted into analog pulse electric signal all the way, exports to corresponding signal processing module；The different light letter of multiple placement locations
Number receiver module synchronous working, is converted into analog pulse telecommunications by the optical signal of the correspondence different angle across cell respectively
Number, and export to corresponding multiple signal processing modules；
The signal processing module is equipped with multiple；One signal processing module corresponds to an optical signal receiver module, connects
Analog pulse electric signal all the way is received, Bing Duigai roads analog pulse electric signal is amplified and bandpass filtering treatment, exports to correspondence
ADC acquisition modules；Multiple signal processing modules synchronous working, is respectively amplified corresponding analog pulse electric signal and band
Pass filter processing, exports to corresponding multiple ADC acquisition modules；
The ADC acquisition modules are equipped with multiple, and ADC acquisition module corresponds to a signal processing module, will mould all the way
Intend pulse electrical signal and be converted into digit pulse data all the way, export to the FPGA module；Multiple ADC acquisition modules synchronize work
Make, corresponding analog pulse electric signal is converted into digit pulse data respectively, is exported to the FPGA module；
The FPGA module carries out data processing to multi-path digital pulse data, is then written in DDR storage modules；
The DDR storage modules are used to store digit pulse data.
The cytoanalyze, wherein, the FPGA module includes：One SPI (Serial Peripheral
Interface, Serial Peripheral Interface (SPI)) control unit, multiple data synchronisation units, multiple data identification units, multiple data groups
Packet unit, multiple data buffer storage units and a DDR controller unit；The data synchronisation unit, data identification unit, data
Group packet unit and data buffer storage unit quantity are equal；The SPI control units, data synchronisation unit, data identification unit, data
Group packet unit, data buffer storage unit and DDR controller unit are sequentially connected electrically；
The SPI control units are used to receive the beginning acquisition instructions and knot for the digit pulse data that cytoanalyze issues
Beam acquisition instructions, and the instruction is transferred to data synchronisation unit；
The data synchronisation unit be equipped with it is multiple, to start acquisition instructions as enable signal, a data synchronisation unit packet
Include a register, data synchronisation unit will be all the way in digit pulse data buffer storage to corresponding register, Bing Jianggai roads
Digit pulse data and beginning acquisition instructions are exported to corresponding data identification unit；Multiple data synchronisation unit synchronous workings,
Respectively by corresponding digit pulse data buffer storage to corresponding register, and by multi-path digital pulse data and start acquisition and refer to
Output is enabled to corresponding multiple data identification units；
The data identification unit be equipped with it is multiple, to start acquisition instructions as enable signal, a data identification unit pair
A data synchronisation unit is answered, a corresponding data identifier is added, and will add for the corresponding data of digit pulse all the way
The digit pulse data of data identifier are exported to corresponding data group packet unit；Multiple data identification unit synchronous workings,
Respectively corresponding digit pulse data interpolation data identifier, and export to corresponding multiple data group packet units；
The data group packet unit is equipped with multiple, and data group packet unit corresponds to a data identification unit, will add
The digit pulse all the way data of data identifier are packaged into data packet, export to corresponding data buffer storage unit；Multiple data
The corresponding digit pulse data for being added to data identifier are packaged into data packet respectively, exported by group packet unit synchronous working
To corresponding multiple data buffer storage units；
The data buffer storage unit is equipped with multiple；One data buffer storage unit corresponds to a data group packet unit, including one
A buffer receives the data packet of corresponding data group packet unit output, writes the data packet in buffer；Multiple data buffer storage lists
Member synchronous working receives the data packet of corresponding data group packet unit output, and multiple data packets is written corresponding caching respectively
In device；
The DDR controller unit is used to read data from the buffer of the data buffer storage unit, and will read out
Data storage to the corresponding address of DDR storage modules in；
The cytoanalyze, wherein, the data identification unit merges in data group packet unit, digit pulse all the way
The data packet of data corresponds to a data identifier.
It is provided by the utility model can the operation principle of synchronous storage multiplex pulse data cytoanalyze be：
The SPI control units refer to for the acquisition that starts that receiving host (cytoanalyze in the utility model) issues
It enables and terminates acquisition instructions, and pass through this and start acquisition instructions or terminate acquisition instructions control data synchronisation unit progress ADC numbers
According to acquisition start or acquire to terminate.
The data synchronisation unit is to start acquisition instructions as the enable signal of data buffer storage.When caching enable signal has
During effect, multichannel data is cached in corresponding register by synchronization.
The data identification unit is synchronized to multiplex pulse data and adds data identifier, and the data identifier can be distinguished more
Circuit-switched data is the pulse signal of what angle respectively.
The purpose of the data group packet unit be in order to reduce buffer write clock frequency and reduce to DDR store mould
Block writes the requirement of clock frequency.It is that the reading clock frequency of buffer must be big that multichannel data, which can synchronize one of key point of storage,
Clock frequency is write in buffer.The reading clock frequency of the buffer writes clock frequency equal to or less than DDR's.Data
The data packet bit wide of group packet unit requirement output is n times of input data bit wide, n is the integer more than or equal to 1, then buffer
Write 1/n times that clock frequency is ADC acquisition clock frequencies.Therefore, by changing the bit wide of output data packet, thus it is possible to vary caching
Device writes clock frequency, to adapt to the demand of different operating environment.
The data buffer storage unit then sets the bit wide of buffer according to the data packet bit wide of data group packet module output,
Multichannel data synchronizes the key point second is that the bit wide of data buffer is necessarily equal to the bit wide of data packet of storage.Buffer is not
Situation about overflowing can occur.
DDR controller unit mainly control from data buffer storage unit read data while, also the data of reading store
In the corresponding address of DDR storage modules.When data buffer is half-full, DDR controller unit reads data packet from buffer,
And it is written into DDR memory modules.When receiving acquisition END instruction, DDR controller unit will own in buffer
Data read, and be written in DDR memory modules.The cooperation of above-mentioned module can solve existing cytoanalyze and cannot synchronize to deposit
The technical issues of storing up multiplex pulse data.
A kind of cytoanalyze and its controlling party that can be realized multiplex pulse data and synchronize storage provided by the utility model
Method has following advantageous effect：
(1) the utility model only achieves that multiplex pulse data with a FPGA module and a DDR storage module
Synchronous memory requirement, hardware cost decrease.
(2) for the utility model only by the use of a FPGA module as master controller, all data are all in a FPGA mould
It is handled in block, it is easy to control.
(3) using the parallel processing manner of FPGA module, the data of higher rate can be handled.
(4) according to the logical resource of FPGA module and the space resources of DDR storage modules, data processing can neatly be opened up
The quantity of channel realizes more data sync storage demands.
(5) according to application scenarios, the bit wide of data packet can flexibly be selected；Increase the bit wide of data packet, higher speed can be handled
The data of rate；Reduce the bit wide of data packet, the data of storage more multichannel can be synchronized.
Description of the drawings
Fig. 1 is the module frame chart of the cytoanalyze provided by the utility model that can synchronize storage multiplex pulse data.
Fig. 2 is the specific unit block diagram of FPGA module provided by the utility model.
Fig. 3 is the structure diagram of data synchronisation unit provided by the utility model.
Fig. 4 is the structure diagram of data buffer storage unit provided by the utility model.
Specific embodiment
The utility model provides a kind of cytoanalyze that can synchronize storage multiplex pulse data, to make the utility model
Purpose, technical solution and effect it is clearer, clear and definite, the utility model is described in further detail below.It should be appreciated that
Specific embodiment described herein is only used to explain the utility model, is not used to limit the utility model.
In the description of the present invention, it is to be appreciated that the orientation or position of the instructions such as term " side ", " opposite side "
It is based on orientation shown in the drawings or position relationship to put relationship, is for only for ease of description the utility model and simplifies description, and
It is not instruction or implies signified device or element there must be specific orientation, with specific azimuth configuration and operation, therefore
It is not intended that the limitation to the utility model.
In addition, in the utility model, term " multichannel " is meant that more than two-way or two-way；" multiple " are meant that two
It is a or more than two.
Refering to Fig. 1, the cytoanalyze that can be realized multiplex pulse data and synchronize storage generates mould including a light source
14, block 11, multiple optical signal receiver modules 12, multiple signal processing modules 13, multiple ADC acquisition modules FPGA modules
15 and a DDR storage module 16；The optical signal receiver module 12, signal processing module 13 and ADC acquisition modules 14 count
It measures equal；The optical signal receiver module 12, signal processing module 13, ADC acquisition modules 14, FPGA module 15 and DDR storages
16 pieces of mould is deposited to be sequentially connected electrically.
Referring again to Fig. 1, the light source production module 11 is arranged on the side of the cell of cytoanalyze, is sent out to cell
Constant optical signal；Optical signal generates different amplitudes after attenuation cell, in the different angle of the another side of cell backlight
Optical signal.
The optical signal receiver module 12 is arranged on the opposite side of the cell of cytoanalyze, the optical signal receiver
Module 12 is equipped with multiple；Since optical signal is after attenuation cell, multiple and different angles are generated not in the another side of cell backlight
With the optical signal of amplitude, the optical signals of each optical signal receiver module 12 receptions, one angle, and by the light of the angle
Signal is converted into analog pulse electric signal all the way, exports to corresponding signal processing module 13；The different light of multiple placement locations
Signal receiver module 12 works asynchronously, and will be converted into analog pulse electricity across the optical signal of the correspondence different angle of cell respectively
Signal, and export to corresponding multiple signal processing modules 13.
The signal processing module 13 is equipped with multiple, each signal processing module 13 correspondences, one optical signal receiver
Module 12 receives analog pulse electric signal all the way, and Bing Duigai roads analog pulse electric signal is amplified and bandpass filtering treatment, defeated
Go out to corresponding ADC acquisition modules 14；Multiple signal processing modules 13 work asynchronously, respectively to corresponding analog pulse electric signal
It is amplified and bandpass filtering treatment, exports to corresponding multiple ADC acquisition modules 14.
The ADC acquisition modules 14 are equipped with multiple, each ADC acquisition module 14 correspondences, one signal processing module
13, digit pulse data all the way will be converted by analog pulse electric signal all the way, exported to the FPGA module 15；Multiple ADC are adopted
Collection module 14 works asynchronously, and corresponding analog pulse electric signal is converted into digit pulse data respectively, is exported to the FPGA
Module 15.
The FPGA module 15 carries out data processing to multi-path digital pulse data, is then written in DDR storage modules 16.
The DDR storage modules 16 are used to store digit pulse data.
Preferably, the line of 12 placement location of optical signal receiver module and cell is no more than with horizontal angle
45 degree.
Refering to Fig. 2, Fig. 3 and Fig. 4, the FPGA module includes：It is SPI control units 20, multiple data synchronisation units 21, more
A data identification unit 22, multiple data group packet units 23, multiple data buffer storage units 24 and DDR controller unit 25；It is described
Data synchronisation unit 21, data identification unit 22, data group packet unit 23 are equal with 24 quantity of data buffer storage unit；The SPI
Control unit 20, data synchronisation unit 21, data identification unit 22, data group packet unit 23, data buffer storage unit 24 and DDR controls
Device unit 25 processed is sequentially connected electrically.
The SPI control units 20 be used for receive the digit pulse data that cytoanalyze issues beginning acquisition instructions and
Terminate acquisition instructions, and the instruction is transferred to data synchronisation unit 21.
The data synchronisation unit 21 be equipped with it is multiple, to start acquisition instructions as enable signal, each data synchronizes list
Member 21 includes a register 211, data synchronisation unit 21 will all the way digit pulse data buffer storage to corresponding register
In 211, and the railway digital pulse data and beginning acquisition instructions are exported to corresponding data identification unit 22；Multiple data are same
Step unit 21 works asynchronously, respectively by corresponding digit pulse data buffer storage to corresponding register 211, and by multi-path digital
Pulse data and beginning acquisition instructions are exported to corresponding multiple data identification units 22.
The data identification unit 22 is equipped with multiple, each data identification unit 22 one data synchronisation unit of correspondence
21, add a corresponding data identifier, and the number that data identifier will be added to for the corresponding data of digit pulse all the way
Word pulse data, which export, gives data corresponding group of packet unit 23；Multiple data identification units 22 work asynchronously, respectively corresponding
Digit pulse data interpolation data identifier, and export to corresponding multiple data group packet units 23.
The data group packet unit 23 is equipped with multiple, each data group packet unit 23 one data identification unit of correspondence
22, the data of digit pulse all the way for being added to data identifier are packaged into data packet, are exported to corresponding data buffer storage unit
24；Multiple data group packet units 23 work asynchronously, and are respectively packaged the corresponding digit pulse data for being added to data identifier
Into data packet, export to corresponding multiple data buffer storage units 24.
The data buffer storage unit 24 is equipped with multiple；Each data buffer storage unit 24 corresponds to a data group packet unit
23, including a buffer 241, the data packet of 23 output of corresponding data group packet unit is received, writes the data packet buffer 241
In；Multiple data buffer storage units 24 work asynchronously, and receive the data packet of 23 output of corresponding data group packet unit respectively, and will be multiple
Data packet is written in corresponding buffer 241.
The DDR controller unit 25 will be read for reading data from the buffer of the data buffer storage unit 24
In data storage out to 16 corresponding address of DDR storage modules.
Preferably, each data synchronisation unit 21 is set there are one register 211, the FPGA module 15 of this cytoanalyze
Interior to be equipped with multiple data synchronisation units 21, each data synchronisation unit 21 corresponds to a register 211；Each data buffer storage list
Member 24 includes a buffer 241, and multiple data buffer storage units 24, each data are equipped in the FPGA module of this cytoanalyze
Buffer unit 24 corresponds to a buffer 241.
Preferably, the write clock frequency of the buffer 241 of the data buffer storage unit 24 is the 1/ of ADC acquisition modules 14
N times, the clock cycle number needed for the group packet procedures of the data group packet unit 23 is n, and the n is that data group packet unit 23 is defeated
The quotient of the data packet bit wide gone out and input data bit wide, n are greater than 1 integer.Therefore, the write clock frequency of buffer 241
It can be adjusted by adjusting the bit wide of data packet.
Preferably, the data packet bit wide that the data buffer storage unit 24 is exported according to data group packet unit 23 caches to set
The bit wide of device 241 so that the bit wide of buffer 241 is equal to the bit wide of data packet.
Preferably, the mode that the data buffer 241 in the data buffer storage unit 24 reads and writes data is asynchronous read and write,
When data are read, data write-in can be carried out.
Preferably, the data identification unit 22 merges in data group packet unit 23, all the way the number of digit pulse data
According to the corresponding data identifier of packet.
Preferably, the data synchronisation unit 21 can with etc. FIFO (first in first out) buffers of quantity replace, per way
Word pulse data correspond to a FIFO buffer.
Preferably, the data buffer unit 24 can with etc. the FIFO buffers of quantity or the RAM of twoport (deposit at random
Access to memory) it replaces.
It is provided by the utility model can the operation principles of synchronous storage multiplex pulse data be：
The SPI control units are used for the pulse data that receiving host (cytoanalyze in the utility model) issues and open
Beginning acquisition instructions and terminate acquisition instructions, and pass through that this starts or END instruction control data synchronisation unit carries out adc data
Acquisition starts or acquisition terminates.
The data synchronisation unit is using the acquisition instructions that host issues as the enable signal of data buffer storage.When caching is enabled
When signal is effective, multichannel data is by synchronization caching to corresponding register.The data identification unit gives multiplex pulse data
Add data identifier, purpose is in order to distinguish the pulse signal what angle multichannel data is respectively.
Wherein, the purpose of the data group packet unit be in order to reduce data buffer write clock frequency and reduce pair
DDR writes the requirement of clock frequency.Multichannel data can synchronize one of key point of storage be buffer reading clock frequency it is necessary
Clock frequency is write more than buffer.The reading clock frequency of the buffer writes clock frequency equal to or less than DDR's.Number
It it is n times of input data bit wide according to group data packet bit wide of packet unit requirement output, n is the integer more than or equal to 1, then buffer
Clock frequency of writing be ADC acquisitions 1/n times of clock frequency.
The data buffer storage unit then sets the bit wide of buffer according to the data packet bit wide of data group packet module output,
Multichannel data synchronizes the key point second is that the bit wide of data buffer is necessarily equal to the bit wide of data packet of storage.The core of buffer
Heart problem is the situation that cannot occur overflowing, therefore it is required that the setting of the depth of data buffer combines the resource of FPGA and delays
The read-write rate of storage determines.
DDR controller unit mainly control from data buffer read data while, also the data of the reading are stored in
In the corresponding address of ddr particles.When data buffer is half-full, DDR controller unit from buffer read data packet, and by its
It is written in DDR memory.When acquiring END instruction arrival, DDR controller unit reads data all in buffer,
And it is written in DDR memory.Synchronous storage multichannel arteries and veins to be solved in the utility model is realized by the writing of above-mentioned module
Rush data.
Cytoanalyze provided by the utility model replaces microcontroller of the prior art with FPGA module, utilizes
The abundant logical resource of the parallel processing manner and FPGA of FPGA, multi-path digital umber of pulse is corresponded to using multiple data synchronisation units
According in the method for area throw-over degree, that realizes multi-path digital pulse data synchronizes storage.In addition, the write clock frequency of buffer
Rate can adjust by adjusting the bit wide of data packet, and can to adjust the bit wide of data packet in different application scenarios slow to adjust
The write clock frequency of storage.
The utility model has the advantage that：
(1) the utility model only achieves that multiplex pulse data with a FPGA module and a DDR storage module
Synchronous memory requirement, hardware cost decrease.
(2) for the utility model only by the use of a FPGA module as master controller, all data are all in a FPGA mould
It is handled in block, it is easy to control.
(3) using the parallel processing manner of FPGA module, the data of higher rate can be handled.
(4) according to the logical resource of FPGA module and the space resources of DDR storage modules, data processing can neatly be opened up
The quantity of channel realizes more data sync storage demands.
(5) according to application scenarios, the bit wide of data packet can flexibly be selected；Increase the bit wide of data packet, higher speed can be handled
The data of rate；Reduce the bit wide of data packet, the data of storage more multichannel can be synchronized.
The utility model type is described in detail above, it for those of ordinary skills, can basis
Above description is improved or converted, and all these modifications and variations should all belong to the guarantor of the appended claims for the utility model
Protect range.
Claims (3)
1. a kind of cytoanalyze that can synchronize storage multiplex pulse data, which is characterized in that including:It is light source production module, more
A optical signal receiver module, multiple signal processing modules, multiple ADC acquisition modules, FPGA module and DDR storage modules；Institute
It is equal to state optical signal receiver module, signal processing module and ADC acquisition module quantity；The optical signal receiver module, letter
Number processing module, ADC acquisition modules, FPGA module and DDR storage modules are sequentially connected electrically；
The light source production module is arranged on the side of the cell of cytoanalyze；
The optical signal receiver module is arranged on the opposite side of the cell of cytoanalyze, and the optical signal receiver module is set
Have multiple；One optical signal receiver module receives the optical signal across an angle of cell, and by the optical signal of the angle
Analog pulse electric signal all the way is converted into, is exported to corresponding signal processing module；The different optical signal of multiple placement locations connects
Receive the work of device module synchronization；
The signal processing module is equipped with multiple；One signal processing module corresponds to an optical signal receiver module, and export
To corresponding ADC acquisition modules；Multiple signal processing module synchronous workings；
The ADC acquisition modules are equipped with multiple, and ADC acquisition module corresponds to a signal processing module, will simulate arteries and veins all the way
It rushes electric signal and is converted into digit pulse data all the way, export to the FPGA module；Multiple ADC acquisition modules synchronous workings；
The FPGA module carries out data processing to multi-path digital pulse data, is then written in DDR storage modules；
The DDR storage modules are used to store digit pulse data.
2. cytoanalyze according to claim 1, which is characterized in that the FPGA modules include：SPI control units,
Multiple data synchronisation units, multiple data identification units, multiple data group packet units, multiple data buffer storage units and DDR controls
Device unit；The data synchronisation unit, data identification unit, data group packet unit and data buffer storage unit quantity are equal；It is described
SPI control units, data synchronisation unit, data identification unit, data group packet unit, data buffer storage unit and DDR controller list
Member is sequentially connected electrically.
3. cytoanalyze according to claim 2, which is characterized in that the data identification unit merges in data group packet
In unit.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109189717A (en) * | 2018-09-07 | 2019-01-11 | 郑州信大先进技术研究院 | A kind of multi-source data synchronous |
| WO2019119982A1 (en) * | 2017-12-21 | 2019-06-27 | 深圳市帝迈生物技术有限公司 | Cell analyzer capable of synchronously storing multi-path pulse data and control method therefor |
| CN112687157A (en) * | 2021-01-12 | 2021-04-20 | 上海理工大学 | Teaching experiment instrument of flow cytometry analysis technology |
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2017
- 2017-12-21 CN CN201721806219.6U patent/CN207586101U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019119982A1 (en) * | 2017-12-21 | 2019-06-27 | 深圳市帝迈生物技术有限公司 | Cell analyzer capable of synchronously storing multi-path pulse data and control method therefor |
| CN109946216A (en) * | 2017-12-21 | 2019-06-28 | 深圳市帝迈生物技术有限公司 | A kind of cytoanalyze and its control method that can synchronize storage multiplex pulse data |
| CN109189717A (en) * | 2018-09-07 | 2019-01-11 | 郑州信大先进技术研究院 | A kind of multi-source data synchronous |
| CN112687157A (en) * | 2021-01-12 | 2021-04-20 | 上海理工大学 | Teaching experiment instrument of flow cytometry analysis technology |
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