CN207573238U - A kind of charge pump for fpga chip - Google Patents
A kind of charge pump for fpga chip Download PDFInfo
- Publication number
- CN207573238U CN207573238U CN201721687629.3U CN201721687629U CN207573238U CN 207573238 U CN207573238 U CN 207573238U CN 201721687629 U CN201721687629 U CN 201721687629U CN 207573238 U CN207573238 U CN 207573238U
- Authority
- CN
- China
- Prior art keywords
- transistor
- gate
- drain
- source
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
Links
- 238000001514 detection method Methods 0.000 claims abstract description 18
- 238000012937 correction Methods 0.000 claims description 24
- 239000003990 capacitor Substances 0.000 claims description 8
- 238000007599 discharging Methods 0.000 claims description 8
- 230000003068 static effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 12
- 238000013461 design Methods 0.000 description 5
- 238000012544 monitoring process Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Landscapes
- Amplifiers (AREA)
Abstract
The utility model discloses a kind of charge pumps for fpga chip, and correcting circuit, output differential mode clear circuit, differential output circuit are mismatched including Differential input circuit, Commom-mode feedback circuit, electric current；The Differential input circuit connects the differential output circuit, for generating the final output voltage of charge pump；The differential output circuit includes two output terminals, Commom-mode feedback circuit is connected respectively and electric current mismatches correcting circuit, and detection level is mismatched for providing common mode detection level to the Commom-mode feedback circuit respectively, providing electric current to electric current mismatch correcting circuit；The Commom-mode feedback circuit connects Differential input circuit, for the common mode to be detected level compensation to the output terminal of Differential input circuit；The electric current mismatches correcting circuit and connects the differential output circuit, and two difference outputs of compensation are corresponded to for mismatching detection level according to the electric current of the difference output detected.The utility model improves the charge pump linearity.
Description
Technical Field
The utility model belongs to the clock control field, concretely relates to charge pump for FPGA chip.
Background
An FPGA (Field-Programmable Gate Array) is a logic device composed of many logic units, where the logic units include gates, lookup tables and flip-flops, and the FPGA has rich hardware resources, strong parallel processing capability and flexible reconfigurable capability, and is increasingly widely used in many fields such as data processing, communication, and network. Usually, there are multiple PLLs (Phase Locked loops) inside the FPGA. PLLs are used inside FPGAs to generate high quality clocks. A PLL is usually composed of a phase detector, a charge pump, a filter, a voltage controlled oscillator, and a frequency divider. Charge pumps are an important component of PLLs in FPGAs.
The charge pump usually has the problems of mismatched charge and discharge currents, leakage of a capacitor device, limited saturated output voltage and the like in the design. In one embodiment, referring to fig. 1 and 2, the charge pump operates in three states: lead, lag, lock. The specific working process is as follows: leading time up is 1, dn is 0; hysteresis time up is 0, dn is 1; when locking, up is 0 and dn is 0. The signals upb and dnb are the inverse of up and dn, respectively. Leading Mn6 to be conducted, Mn3 to be conducted, output node outn to discharge to the ground, outn potential to be reduced; mn5 is turned off, Mn4 is turned off, the output node is charged by Mp1, and the outp potential rises. When the delay time is delayed, Mn6 is disconnected, Mn3 is disconnected, an output node outn is charged by Mp2, and the potential is increased; mn5 is turned on, Mn4 is turned on, and the output node outp is discharged to the ground, and the potential is lowered. When the lock is performed, Mn6 is off, Mn3 is on, all the current of Mp2 flows into the ground through Mn2, and the outn potential is kept unchanged; mn5 is turned on, Mn4 is turned off, all the current of Mp1 flows into the ground through Mn1, and the outp potential is kept constant.
However, due to the adoption of differential output in the existing scheme, the common mode range of the output voltage of the existing scheme is not controlled, and when the common mode voltage is biased to the power supply voltage or the ground voltage, the circuit fails and cannot work normally; in addition, the current mirror adopts a single-tube structure, the output impedance is low, and the charge and discharge of the MOS tube are unequal due to different common-mode points; in addition to matching factors, the load capacitance leakage of the charge pump also causes common mode level drift.
SUMMERY OF THE UTILITY MODEL
In order to solve the above-mentioned problem that exists among the prior art, the utility model provides a charge pump for FPGA chip. The to-be-solved technical problem of the utility model is realized through following technical scheme:
a charge pump for an FPGA chip comprises a differential input circuit, a common-mode negative feedback circuit, a current mismatching correction circuit, an output differential mode zero clearing circuit and a differential output circuit;
the differential input circuit is connected with the differential output circuit and is used for generating the final output voltage of the charge pump;
the differential output circuit comprises two output ends which are respectively connected with the common mode negative feedback circuit and the current mismatch correction circuit and are used for respectively providing a common mode detection level for the common mode negative feedback circuit and a current mismatch detection level for the current mismatch correction circuit;
the common mode negative feedback circuit is connected with the differential input circuit and is used for compensating the common mode detection level to the output end of the differential input circuit so as to stabilize the common mode signal of the output end of the differential input circuit;
the current mismatch correction circuit is connected with the differential output circuit and is used for correspondingly compensating the two differential outputs according to the detected current mismatch detection level of the differential outputs so as to ensure that the two differential outputs can respectively ensure that the respective charging current and the respective discharging current are matched;
the output differential mode zero clearing circuit is connected with the common mode negative feedback circuit and is used for clearing differential mode signals output by the differential pair transistors of the common mode negative feedback circuit when the circuit is started to work.
Further, the device also comprises a bias circuit which is connected with the current mismatch correction circuit and used for providing bias current for the current mismatch correction circuit so as to enhance the matching of the output charging and discharging current.
The charge pump further comprises an enabling switch, wherein the enabling switch is connected with the bias circuit and the common-mode negative feedback circuit and is used for controlling the conduction or disconnection of the common-mode negative feedback direct current detection voltage of the charge pump from a voltage source to a ground end so as to reduce the static power consumption when the phase-locked loop is not enabled.
Further, the differential input circuit includes: the transistor comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first port, a second port, a third port and a fourth port; wherein,
the grid electrode of the first transistor is connected with a first port, the source electrode of the first transistor is connected with the source electrode of the second transistor and the drain electrode of the third transistor, and the drain electrode of the first transistor is connected with the differential output circuit;
the grid electrode of the second transistor is connected with a second port, and the drain electrode of the second transistor is connected with the differential output circuit;
the grid electrode of the third transistor is connected with the bias circuit and the grid electrode of the fourth transistor, and the source electrode of the third transistor is connected with the drain electrode of the fifth transistor;
the grid electrode of the fourth transistor is connected with the bias circuit, the source electrode of the fourth transistor is connected with the drain electrode of the sixth transistor, and the drain electrode of the fourth transistor is connected with the source electrode of the seventh transistor and the source electrode of the eighth transistor;
the grid electrode of the fifth transistor is connected with the bias circuit and the grid electrode of the sixth transistor, and the source electrode of the fifth transistor is connected with the ground terminal;
the grid electrode of the sixth transistor is connected with the bias circuit, and the source electrode of the sixth transistor is connected with a grounding end;
the grid electrode of the seventh transistor is connected with the third port, and the drain electrode of the seventh transistor is connected with the differential output circuit;
and the grid electrode of the eighth transistor is connected with a fourth port, and the drain electrode of the eighth transistor is connected with the differential output circuit.
Further, the current mismatch correction circuit includes: a first operational amplifier, a second operational amplifier, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a fortieth transistor, a forty-first transistor, a forty-fourth transistor, a forty-fifth transistor; wherein,
the non-inverting input end of the first operational amplifier is connected with the drain of the fortieth transistor and the drain of the ninth transistor, the inverting input end of the first operational amplifier is connected with the differential output circuit, the output end of the first operational amplifier is connected with the grid of the tenth transistor, and the source of the fortieth transistor is connected with the drain of the forty-fourth transistor; the source electrode of the ninth transistor is connected with the drain electrode of the tenth transistor, and the gate electrode of the ninth transistor is connected with the gate electrode of the eleventh transistor and the bias circuit; the source electrode of the tenth transistor is connected with a power supply end, and the grid electrode of the tenth transistor is also connected with the grid electrode of the twelfth transistor; the drain of the eleventh transistor is connected with the differential output circuit, the source of the eleventh transistor is connected with the drain of the twelfth transistor, and the gate of the eleventh transistor is connected with the gate of the thirteenth transistor; the source electrode of the twelfth transistor is connected with the power supply end; the gate of the thirteenth transistor is connected with the gate of the fourteenth transistor, the source of the thirteenth transistor is connected with the fifteenth transistor, the drain of the thirteenth transistor is connected with the non-inverting input end of the second operational amplifier and the drain of the forty-first transistor, and the source of the forty-first transistor is connected with the drain of the forty-fifth transistor; the inverting input end of the second operational amplifier is connected with the differential output circuit; the grid electrode of the fourteenth transistor is connected with the bias circuit, the source electrode of the fourteenth transistor is connected with the drain electrode of the sixteenth transistor, and the drain electrode of the fourteenth transistor is connected with the differential output circuit; the gate of the fifteenth transistor is connected to the output end of the second operational amplifier and the gate of the sixteenth transistor, and the source of the fifteenth transistor and the source of the sixteenth transistor are both connected to a power supply end.
Further, the bias circuit includes: a twenty-fifth transistor, a thirty-fourth transistor, a thirty-fifth transistor, a thirty-sixth transistor, a thirty-eighth transistor, a thirty-ninth transistor, a forty-second transistor, a forty-third transistor, a forty-sixth transistor; wherein,
the gate of the twenty-fifth transistor is connected with the fourth transistor, the source of the twenty-fifth transistor is connected with the drain of the thirty-fourth transistor, and the drain of the twenty-fifth transistor is connected with the fifth port and the output differential mode zero clearing circuit;
a thirty-fourth transistor gate is connected with the sixth transistor gate;
the source electrode of the thirty-fifth transistor is connected with the drain electrode of the thirty-sixth transistor, and the drain electrode of the thirty-fifth transistor is connected with the sixth port and the output differential mode zero clearing circuit;
the thirty-eighth transistor gate is connected with the thirty-eighth transistor drain, the thirty-ninth transistor gate, the forty-fourth transistor gate and the forty-first transistor gate, and the thirty-eighth transistor source is connected with the forty-second transistor source, the forty-third transistor source, the forty-fourth transistor source, the forty-fifth transistor source and the ground voltage terminal; the drain electrode of the thirty-eighth transistor is connected with the output end of the first current source;
the source of the thirty-ninth transistor is connected with the drain of the forty-third transistor, and the drain of the thirty-ninth transistor is connected with the drain of the forty-sixth transistor;
the gate of the forty-second transistor is connected with the gate of the forty-third transistor and the gate of the forty-fourth transistor and the gate of the forty-fifth transistor, and the drain of the forty-second transistor is connected with the output end of the second current source;
the gate of the forty-sixth transistor is connected to the drain of the forty-sixth transistor and the gate of the ninth transistor, and the source of the forty-sixth transistor is connected to the first current source input terminal, the second current source input terminal and the power supply terminal.
Further, the differential output circuit includes: a thirty-third transistor, a thirty-seventh transistor;
the gate of the thirty-third transistor is connected with the gate of a thirty-seventh transistor, and the drain of the thirty-third transistor is connected with the fifth port and the drain of the eleventh transistor;
the drain electrode of the thirty-seventh transistor is connected with the drain electrode of the fourteenth transistor and the sixth port.
Further, the common mode negative feedback circuit includes: a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twentieth transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirty-third transistor, a first resistor, and a second resistor; wherein,
the gate of the seventeenth transistor is connected with the fifth port, the source of the seventeenth transistor is connected with the source of the eighteenth transistor and the drain of the nineteenth transistor, and the drain of the seventeenth transistor is connected with the drain of the twentieth transistor, the drain of the twenty-first transistor and the gate of the twenty-first transistor;
the grid electrode of the eighteenth transistor is connected with a twenty-second transistor, one end of a first resistor, one end of a second resistor, the positive electrode of a first capacitor and a power supply voltage dividing end, the other end of the second resistor is connected with the power supply end, and the drain electrode of the eighteenth transistor is connected with the drain electrode of the twenty-second transistor, the drain electrode of the twenty-third transistor and the grid electrode of the twenty-fourth transistor;
the grid electrode of the nineteenth transistor is connected with the grid electrode of the twenty-fifth transistor and the grid electrode of the twenty-sixth transistor, and the source electrode of the nineteenth transistor is connected with the drain electrode of the twenty-seventh transistor;
the gate of the twentieth transistor is connected with a sixth port, and the source of the twentieth transistor is connected with the source of the twentieth transistor and the drain of the twenty-sixth transistor;
the source of the twenty-first transistor is connected with the source of a twenty-ninth transistor, the source of a thirty-third transistor, the source of a twenty-fourth transistor and the power supply end;
the source electrode of the twenty-second transistor is connected with the drain electrode of the twenty-sixth transistor;
a twenty-third transistor gate is connected with the gate of the fourteenth transistor and the gate of the thirty-third transistor, and a twenty-third transistor source is connected with the drain of the twenty-fourth transistor;
the gate of the twenty-fourth transistor is connected with the gate of the twenty-ninth transistor;
the gate of the twenty-sixth transistor is connected with the gate of a thirty-fifth transistor, and the source of the twenty-sixth transistor is connected with the drain of the thirty-second transistor;
the gate of the twenty-seventh transistor is connected with the gate of the thirty-second transistor and the gate of the thirty-fourth transistor, and the source of the twenty-seventh transistor is connected with the source of the thirty-fourth transistor, the source of the thirty-second transistor, the source of the thirty-sixth transistor, the source of the twenty-eighth transistor, the cathode of the first capacitor and the ground voltage terminal;
the grid electrode of the twenty-eighth transistor is connected with the drain electrode of the twenty-eighth transistor and the other end of the first resistor;
the gate of the twenty-ninth transistor is connected with the gate of the thirtieth transistor, and the drain of the twenty-ninth transistor is connected with the source of the thirty-third transistor, the drain of the eighth transistor and the drain of the second transistor;
the drain electrode of the thirtieth transistor is connected with the source electrode of the thirty-sixth transistor, the drain electrode of the first transistor and the drain electrode of the seventh transistor;
and the gate of the thirty-second transistor is connected with the gate of the thirty-sixth transistor.
Further, the enabling switch comprises a first enabling switch, a second enabling switch and a third enabling switch;
the first enabling switch is connected between the power supply end and the second resistor and used for controlling the connection or disconnection of the power supply end and the second resistor;
the second enable switch is connected between the gate of the forty-second transistor and the ground voltage terminal;
the third enable switch is connected between the thirty-eighth transistor gate and the ground voltage terminal.
Further, the first enable switch, the second enable switch, and the third enable switch are all transistor switches.
Compared with the prior art, the beneficial effects of the utility model are that:
the utility model discloses a charge pump for FPGA chip utilizes the common mode voltage of monitoring differential output circuit through the common mode negative feedback circuit of design, and the dynamic adjustment electric current guarantees that charge pump finally outputs common mode voltage and tends to the voltage of settlement throughout, guarantees that the circuit normally works; in addition, the utility model discloses, the electric leakage problem of the jumbo size electric capacity of back stage filter also can be solved; meanwhile, due to the introduction of the unmatched current correction circuit, when the output voltage is in any value, the matching performance of the charging current and the discharging current of the output end is improved, the linear single-step voltage step of the charge pump in the large-range output voltage is ensured, and the linearity of the charge pump is further improved.
Drawings
Fig. 1 is a schematic diagram of a prior art charge pump circuit.
Fig. 2 is a circuit diagram of a charge pump in one particular application of the prior art.
Fig. 3 is a block diagram of a charge pump module for an FPGA chip according to the present invention.
Fig. 4 is a block diagram of a charge pump module for an FPGA chip according to another embodiment of the present invention.
Fig. 5 is a circuit diagram of a charge pump for an FPGA chip according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of the advanced operating state of the charge pump according to an embodiment of the present invention.
Fig. 7 is a schematic diagram illustrating a hysteresis operation of the charge pump according to an embodiment of the present invention.
Fig. 8 is a schematic diagram of the working state of the charge pump lock according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the present invention is not limited thereto.
Example 1:
fig. 3 is a block diagram of a charge pump module for an FPGA chip according to an embodiment of the present invention, which includes a differential input circuit 1, a common mode negative feedback circuit 2, a current mismatch correction circuit 3, an output differential mode reset circuit 4, and a differential output circuit 5;
the differential input circuit 1 is connected with the differential output circuit 5 and used for generating the final output voltage of the charge pump;
the differential output circuit 5 comprises two output ends which are respectively connected with the common mode negative feedback circuit 2 and the current mismatch correction circuit 3 and are used for respectively providing a common mode detection level for the common mode negative feedback circuit 2 and a current mismatch detection level for the current mismatch correction circuit 3;
the common mode negative feedback circuit 2 is connected with the differential input circuit 1 and is used for compensating the common mode detection level to the output end of the differential input circuit 1 so as to stabilize the common mode signal of the output end of the differential input circuit 1;
the current mismatch correction circuit 3 is connected with the differential output circuit 5 and is used for correspondingly compensating the two differential outputs according to the detected current mismatch detection level of the differential outputs so as to ensure that the two differential outputs can respectively ensure that the charging current and the discharging current are matched;
the output differential mode zero clearing circuit 4 is connected with the common mode negative feedback circuit 2 and is used for clearing the differential mode signals output by the differential pair transistors of the common mode negative feedback circuit 2 when the circuit starts to work.
The utility model discloses a charge pump has weakened the influence that output voltage common mode changes and matches the electric current, has strengthened two output branch road separately charging current and discharging current's matching nature under different output voltage, promotes charge pump linearity.
In one embodiment, referring to fig. 4, a bias circuit 6 is further included, and the bias circuit 6 is connected to the current mismatch correction circuit 3 and is used for providing a bias current to the current mismatch correction circuit 3 to enhance the matching of the output charging and discharging currents. ,
in a specific embodiment, the phase-locked loop further comprises an enable switch 7, and the enable switch 7 is connected with the bias circuit 6 and the common mode negative feedback circuit 2 and is used for controlling the conduction or disconnection of the common mode negative feedback direct current detection voltage of the charge pump from a voltage source to a ground terminal so as to reduce static power consumption when the phase-locked loop is not enabled.
This embodiment provides a specific example to better describe the concept of the present invention, referring to the circuit diagram shown in fig. 5. The differential input circuit 1 includes: a first transistor xi7, a second transistor xi6, a third transistor xi5, a fourth transistor xi2, a fifth transistor xi4, a sixth transistor xi3, a seventh transistor xi0, an eighth transistor xi1, a first port dnb, a second port dn, a third port up, and a fourth port up; wherein,
the grid electrode of the first transistor xi7 is connected with the first port dnb, the source electrode of the first transistor xi7 is connected with the source electrode of the second transistor xi6 and the drain electrode of the third transistor xi5, and the drain electrode of the first transistor xi7 is connected with the differential output circuit 5;
the gate of the second transistor xi6 is connected to the second port dn, and the drain of the second transistor xi6 is connected to the differential output circuit 5;
the grid electrode of the third transistor xi5 is connected with the bias circuit 6 and the grid electrode of the fourth transistor xi2, and the source electrode of the third transistor xi5 is connected with the drain electrode of the fifth transistor xi 4;
the gate of the fourth transistor xi2 is connected to the bias circuit 6, the source of the fourth transistor xi2 is connected to the drain of the sixth transistor xi3, and the drain of the fourth transistor xi2 is connected to the source of the seventh transistor xi0 and the source of the eighth transistor xi 1;
the gate of the fifth transistor xi4 is connected to the bias circuit 6 and the gate of the sixth transistor xi3, and the source of the fifth transistor xi4 is connected to the ground;
the gate of the sixth transistor xi3 is connected to the bias circuit 6, and the source of the sixth transistor xi3 is connected to the ground;
the grid electrode of the seventh transistor xi0 is connected with a third port up, and the drain electrode of the seventh transistor xi0 is connected with the differential output circuit 5;
the gate of the eighth transistor xi1 is connected to the fourth port upb, and the drain of the eighth transistor xi1 is connected to the differential output circuit 5.
The current mismatch correction circuit 3 includes: a first operational amplifier I11, a second operational amplifier I12, a ninth transistor M3, a tenth transistor M2, an eleventh transistor M5, a twelfth transistor M6, a thirteenth transistor M11, a fourteenth transistor M10, a fifteenth transistor M13, a sixteenth transistor M12, a forty transistor M1, a forty-first transistor M9, a forty-fourth transistor M0, a forty-fifth transistor M8; wherein,
the non-inverting input end of the first operational amplifier I11 is connected with the drain of the fortieth transistor M1 and the drain of the ninth transistor M3, the inverting input end of the first operational amplifier I11 is connected with the differential output circuit 5, the output end of the first operational amplifier I11 is connected with the gate of the tenth transistor M2, and the source of the fortieth transistor M1 is connected with the drain of the forty-fourth transistor M0; the source of the ninth transistor M3 is connected to the drain of the tenth transistor M2, and the gate of the ninth transistor M3 is connected to the gate of the eleventh transistor M5 and the bias circuit 6; the source of the tenth transistor M2 is connected to a power supply terminal, and the gate of the tenth transistor M2 is also connected to the gate of a twelfth transistor M6; the drain of the eleventh transistor M5 is connected to the differential output circuit 5, the source of the eleventh transistor M5 is connected to the drain of the twelfth transistor M6, and the gate of the eleventh transistor M5 is connected to the gate of the thirteenth transistor M11; the source of the twelfth transistor M6 is connected to the power supply end; the gate of the thirteenth transistor M11 is connected to the gate of the fourteenth transistor M10, the source of the thirteenth transistor M11 is connected to the fifteenth transistor M13, the drain of the thirteenth transistor M11 is connected to the non-inverting input of the second operational amplifier I12 and the drain of the forty-first transistor M9, and the source of the forty-first transistor M9 is connected to the drain of the forty-fifth transistor M8; the inverting input end of the second operational amplifier I12 is connected with the differential output circuit 5; the gate of the fourteenth transistor M10 is connected to the bias circuit 6, the source of the fourteenth transistor M10 is connected to the drain of the sixteenth transistor M12, and the drain of the fourteenth transistor M10 is connected to the differential output circuit 5; the gate of the fifteenth transistor M13 is connected to the output terminal of the second operational amplifier I12 and the gate of the sixteenth transistor M12, and the source of the fifteenth transistor M13 and the source of the sixteenth transistor M12 are both connected to a power source terminal.
The bias circuit 6 includes: a twenty-fifth transistor xi8, a thirty-fourth transistor xi9, a thirty-fifth transistor xi11, a thirty-sixth transistor xi10, a thirty-eighth transistor xi56, a thirty-ninth transistor xi44, a forty-second transistor M4, a forty-third transistor xi45, a forty-sixth transistor xi 43; wherein,
the gate of the twenty-fifth transistor xi8 is connected to the fourth transistor xi2, the source of the twenty-fifth transistor xi8 is connected to the drain of the thirty-fourth transistor xi9, and the drain of the twenty-fifth transistor xi8 is connected to the fifth port cpi _ p and the output differential mode zero clearing circuit 4;
a thirty-fourth transistor xi9 gate is connected to the sixth transistor xi3 gate;
the source of the thirty-fifth transistor xi11 is connected to the drain of the thirty-sixth transistor xi10, and the drain of the thirty-fifth transistor xi11 is connected to the sixth port cpi _ n and the output differential mode zero clearing circuit 4;
the gate of the thirty-eighth transistor xi56 is connected with the drain of the thirty-eighth transistor xi56, the gate of the thirty-ninth transistor xi44, the gate of the forty-first transistor M1 and the gate of the forty-first transistor M9, and the source of the thirty-eighth transistor xi56 is connected with the source of the forty-second transistor M4, the source of the forty-third transistor xi45, the source of the forty-fourth transistor M0, the source of the forty-fifth transistor M8 and the ground voltage terminal; the drain of the thirty-eighth transistor xi56 is connected to the output terminal of the first current source I6;
the source of the thirty-ninth transistor xi44 is connected to the drain of the forty-third transistor xi45, and the drain of the thirty-ninth transistor xi44 is connected to the drain of the forty-sixth transistor xi 43;
the gate of the forty-second transistor M4 is connected with the gate of the forty-third transistor xi45, the gate of the forty-fourth transistor M0 and the gate of the forty-fifth transistor M8 are connected, and the drain of the forty-second transistor M4 is connected with the output end of a second current source I5;
the gate of the forty-sixth transistor xi43 is connected to the drain of the forty-sixth transistor xi43 and the gate of the ninth transistor M3, and the source of the forty-sixth transistor xi43 is connected to the input terminal of the first current source I6, the input terminal of the second current source I5 and the power supply terminal.
The differential output circuit 5 includes: a thirty-third transistor xi13, a thirty-seventh transistor xi 12;
the gate of the thirty-third transistor xi13 is connected to the gate of a thirty-seventh transistor xi12, and the drain of the thirty-third transistor xi13 is connected to the fifth port cpi _ p and the drain of the eleventh transistor M5;
the drain of the thirty-seventh transistor xi12 is connected to the drain of the fourteenth transistor M10 and the sixth port cpi _ n.
The common mode negative feedback circuit 2 includes: a seventeenth transistor xi42, an eighteenth transistor xi41, a nineteenth transistor xi38, a twentieth transistor xi39, a twenty-first transistor xi47, a twentieth transistor xi40, a twenty-third transistor xi48, a twenty-fourth transistor xi49, a twenty-seventh transistor xi37, a twenty-eighth transistor xi112, a twenty-ninth transistor xi14, a thirty-third transistor xi15, a thirty-second transistor xi36, a first resistor xi109, and a second resistor xi 105; wherein,
the gate of the seventeenth transistor xi42 is connected to the fifth port cpi _ p, the source of the seventeenth transistor xi42 is connected to the source of the eighteenth transistor xi41 and the drain of the nineteenth transistor xi38, and the drain of the seventeenth transistor xi42 is connected to the drain of the twentieth transistor xi39, the drain of the twenty-first transistor xi47 and the gate of the twenty-first transistor xi 47;
the gate of the eighteenth transistor xi41 is connected to the twenty-second transistor xi40, one end of a first resistor xi109, one end of a second resistor xi105, the anode of a first capacitor xi96 and a power supply voltage dividing end vcom, the other end of the second resistor xi105 is connected to the power supply end, and the drain of the eighteenth transistor xi41 is connected to the drain of the twenty-second transistor xi40, the drain of the twenty-third transistor xi48 and the gate of the twenty-fourth transistor xi 49;
the gate of the nineteenth transistor xi38 is connected with the gate of the twenty-fifth transistor xi8 and the gate of the twenty-sixth transistor xi35, and the source of the nineteenth transistor xi38 is connected with the drain of the twenty-seventh transistor xi 37;
the gate of the twentieth transistor xi39 is connected to the sixth port cpi _ n, and the source of the twentieth transistor xi39 is connected to the source of the twentieth transistor xi40 and the drain of the twenty-sixth transistor xi 35;
the source of the twenty-first transistor xi47 is connected with the source of a twenty-ninth transistor xi14, the source of a thirty-fourth transistor xi15, the source of a twenty-fourth transistor xi49 and the power supply end;
the source of the twenty-second transistor xi40 is connected with the drain of a twenty-sixth transistor xi 35;
the gate of the twenty-third transistor xi48 is connected to the gate of the fourteenth transistor M10 and the gate of the thirty-third transistor xi13, and the source of the twenty-third transistor xi48 is connected to the drain of the twenty-fourth transistor xi 49;
the gate of the twenty-fourth transistor xi49 is connected to the gate of the twenty-ninth transistor xi 14;
the gate of the twenty-sixth transistor xi35 is connected to the gate of a thirty-fifth transistor xi11, and the source of the twenty-sixth transistor xi35 is connected to the drain of the thirty-second transistor xi 36;
the gate of the twenty-seventh transistor xi37 is connected to the gate of the thirty-second transistor xi36 and the gate of the thirty-fourth transistor xi9, and the source of the twenty-seventh transistor xi37 is connected to the source of the thirty-fourth transistor xi9, the source of the thirty-second transistor xi36, the source of the thirty-sixth transistor xi10, the source of the twenty-eighth transistor xi112, the negative electrode of the first capacitor xi96 and the ground voltage terminal;
the grid electrode of the twenty-eighth transistor xi112 is connected with the drain electrode of the twenty-eighth transistor xi112 and the other end of the first resistor xi 109;
the gate of the twenty-ninth transistor xi14 is connected to the gate of the thirty-third transistor xi15, and the drain of the twenty-ninth transistor xi14 is connected to the source of the thirty-third transistor xi13, the drain of the eighth transistor xi1 and the drain of the second transistor xi 6;
the drain of the thirty-sixth transistor xi15 is connected to the source of a thirty-sixth transistor xi12, the drain of the first transistor xi7 and the drain of the seventh transistor xi 0;
the gate of the thirty-second transistor xi36 is connected to the gate of the thirty-sixth transistor xi 10.
In one embodiment, the enable switch 7 includes a first enable switch xi29, a second enable switch M7, a third enable switch xi 77;
the first enable switch xi29 is connected between the power supply terminal and the second resistor xi105, and is used for controlling the connection or disconnection of the power supply terminal and the second resistor xi 105;
the second enable switch M7 is connected between the gate of the forty-second transistor M4 and the ground voltage terminal;
the third enable switch xi77 is connected between the gate of the thirty-eighth transistor xi56 and the ground voltage terminal.
Preferably, the first enable switch xi29, the second enable switch M7, and the third enable switch xi77 are all transistor switches.
The working principle of the present invention is explained below for the above specific circuit diagram, the charge pump firstly controls the I8 transmission gate short circuit cpi _ p and cpi _ n port through cp _ rst port before working, and clears the differential mode signal of differential output, and ensures that the initial error of the charge pump is zero.
As shown in fig. 6-8, three operating states of the charge pump are sequentially corresponded: up (leading), dn (lagging), idle (locked). The leading time (Icp + Iup _ adj) > Icn, cpi _ p voltage rises; (Icp + Idn _ adj) < (Idnb + Iup + Icn), the cpi _ n voltage drops. At the lag time (Icp + Iup _ adj) < (Idn + Iupb + Icn), the cpi _ p voltage drops; the voltage (Icp + Idn _ adj) > Icn, cpi _ n rises. When the voltage is locked (Icp + Iup _ adj) — (Iupb + Icn), the cpi _ p voltage is unchanged; (Icp + Idn _ adj) — (Idnb + Icn), and the cpi _ n voltage is constant. In FIG. 6, Icn is xi9 and xi10 in the schematic diagram. The capacitor in the dashed box is part of the low pass filter of the next stage module of the charge pump.
Specifically, vcom is a divided voltage of the power supply voltage, and the power supply voltage is fixed, so vcom is a set fixed voltage value. Differential pairs xi 39-xi 42 monitor the common mode voltage of the output terminals cpi _ p and cpi _ n. When the common-mode voltage is lower than the vcomm, the currents of xi37 and xi36 are mostly increased through xi40 and xi41, i.e. the current of xi 49. And xi14 and xi15 currents are proportional to xi49 current, so that the currents flowing through the output terminals cpi _ p and cpi _ n are larger than the pull-down currents of xi9 and xi10, the cpi _ p and cpi _ n common-mode voltage rises, and the adjustment is stopped until the common-mode voltages of cpi _ p and cpi _ n are equal. The negative feedback circuit can stabilize the output common-mode voltage, so that the final output common-mode voltage is equal to the vcom voltage selected by design. When the charge pump detects that two input clocks of a PLL (phase-locked loop) have frequency difference or phase difference, the voltage of the output cpi _ p and cpi _ n of the charge pump circuit respectively moves to a power supply voltage and a ground voltage, when the two input clock frequencies or phases of the PLL have sudden change, the large signal response of the circuit can have enough margin so as not to cause that cpi _ p and cpi _ n rush to the power supply voltage and the ground voltage to generate nonlinear distortion, the utility model discloses select the vcom voltage to be half of the power supply voltage. When differential output is not in the middle of the output common mode range, the charge and discharge branch road of charge pump can lead to the circuit to mismatch because output impedance is limited, the utility model discloses an add the current mismatch correction circuit through detecting cpi _ p and cpi _ n voltage respectively, the partly electric current of dynamic compensation gets into cpi _ p and cpi _ n and holds, guarantees all to have better linearity at whole voltage range. Meanwhile, a sleeve current mirror in the circuit increases the output impedance of the output end, so that the output current is weakly related to the output voltage, and the current consistency in different output voltages is ensured. The voltage division branch and the current source branch are influenced by xi29, M7 and xi77, pwdnbb of the circuit controls the three MOS tubes, the path of the charge pump circuit from a power supply to the ground is closed, and static power consumption of the charge pump circuit is eliminated.
The utility model discloses a charge pump for FPGA chip utilizes the common mode voltage of monitoring differential output circuit through the common mode negative feedback circuit of design, and the dynamic adjustment electric current guarantees that charge pump finally outputs common mode voltage and tends to the voltage of settlement throughout, guarantees that the circuit normally works; in addition, the utility model discloses, the electric leakage problem of the jumbo size electric capacity of back stage filter also can be solved; meanwhile, due to the introduction of the unmatched current correction circuit, when the output voltage is in any value, the matching performance of the charging current and the discharging current of the output end is improved, the linear single-step voltage step of the charge pump in the large-range output voltage is ensured, and the linearity of the charge pump is further improved.
The foregoing is a more detailed description of the present invention, taken in conjunction with the specific preferred embodiments thereof, and it is not intended that the invention be limited to the specific embodiments shown and described. To the utility model belongs to the technical field of ordinary technical personnel, do not deviate from the utility model discloses under the prerequisite of design, can also make a plurality of simple deductions or replacement, all should regard as belonging to the utility model discloses a protection scope.
Claims (10)
1. A charge pump for an FPGA chip is characterized by comprising a differential input circuit (1), a common-mode negative feedback circuit (2), a current mismatching correction circuit (3), an output differential mode zero clearing circuit (4) and a differential output circuit (5);
the differential input circuit (1) is connected with the differential output circuit (5) and is used for generating the final output voltage of the charge pump;
the differential output circuit (5) comprises two output ends which are respectively connected with the common mode negative feedback circuit (2) and the current mismatching correction circuit (3) and are used for respectively providing a common mode detection level for the common mode negative feedback circuit (2) and providing a current mismatching detection level for the current mismatching correction circuit (3);
the common-mode negative feedback circuit (2) is connected with the differential input circuit (1) and is used for compensating the common-mode detection level to the output end of the differential input circuit (1) so as to stabilize the common-mode signal of the output end of the differential input circuit (1);
the current mismatch correction circuit (3) is connected with the differential output circuit (5) and is used for correspondingly compensating the two differential outputs according to the detected current mismatch detection level of the differential outputs so as to ensure that the two differential outputs can respectively ensure that the respective charging current and the discharging current are matched;
the output differential mode zero clearing circuit (4) is connected with the common mode negative feedback circuit (2) and is used for clearing differential mode signals output by differential pair transistors of the common mode negative feedback circuit (2) when the circuit starts to work.
2. The charge pump for the FPGA chip of claim 1, further comprising a bias circuit (6), said bias circuit (6) being connected to said current mismatch correction circuit (3) for providing a bias current to said current mismatch correction circuit (3) to enhance matching of output charge and discharge currents.
3. The charge pump for the FPGA chip of claim 2, further comprising an enable switch (7), wherein the enable switch (7) connects the bias circuit (6) and the common mode negative feedback circuit (2) for controlling the conduction or disconnection of the common mode negative feedback DC detection voltage of the charge pump from a voltage source to a ground terminal to reduce static power consumption when the phase locked loop is not enabled.
4. Charge pump for FPGA chips according to claim 3, characterized in that said differential input circuit (1) comprises: a first transistor (xi7), a second transistor (xi6), a third transistor (xi5), a fourth transistor (xi2), a fifth transistor (xi4), a sixth transistor (xi3), a seventh transistor (xi0), an eighth transistor (xi1), a first port (dnb), a second port (dn), a third port (up), and a fourth port (upb); wherein,
the gate of the first transistor (xi7) is connected with the first port (dnb), the source of the first transistor (xi7) is connected with the source of the second transistor (xi6) and the drain of the third transistor (xi5), and the drain of the first transistor (xi7) is connected with the differential output circuit (5);
the gate of the second transistor (xi6) is connected with a second port (dn), and the drain of the second transistor (xi6) is connected with the differential output circuit (5);
the grid electrode of the third transistor (xi5) is connected with the grid electrodes of the bias circuit (6) and the fourth transistor (xi2), and the source electrode of the third transistor (xi5) is connected with the drain electrode of the fifth transistor (xi 4);
the gate of the fourth transistor (xi2) is connected with the bias circuit (6), the source of the fourth transistor (xi2) is connected with the drain of the sixth transistor (xi3), and the drain of the fourth transistor (xi2) is connected with the source of the seventh transistor (xi0) and the source of the eighth transistor (xi 1);
the gate of the fifth transistor (xi4) is connected with the gates of the bias circuit (6) and the sixth transistor (xi3), and the source of the fifth transistor (xi4) is connected with the ground terminal;
the gate of the sixth transistor (xi3) is connected with the bias circuit (6), and the source of the sixth transistor (xi3) is connected with the ground terminal;
the gate of the seventh transistor (xi0) is connected with the third port (up), and the drain of the seventh transistor (xi0) is connected with the differential output circuit (5);
the gate of the eighth transistor (xi1) is connected to the fourth port (upb), and the drain of the eighth transistor (xi1) is connected to the differential output circuit (5).
5. Charge pump for FPGA chips according to claim 4, characterized in that the current mismatch correction circuit (3) comprises: a first operational amplifier (I11), a second operational amplifier (I12), a ninth transistor (M3), a tenth transistor (M2), an eleventh transistor (M5), a twelfth transistor (M6), a thirteenth transistor (M11), a fourteenth transistor (M10), a fifteenth transistor (M13), a sixteenth transistor (M12), a fortieth transistor (M1), a fortieth transistor (M9), a forty-fourth transistor (M0), a forty-fifth transistor (M8); wherein,
the non-inverting input end of the first operational amplifier (I11) is connected with the drain of the fortieth transistor (M1) and the drain of the ninth transistor (M3), the inverting input end of the first operational amplifier (I11) is connected with the differential output circuit (5), the output end of the first operational amplifier (I11) is connected with the gate of the tenth transistor (M2), and the source of the fortieth transistor (M1) is connected with the drain of the forty-fourth transistor (M0); the source of the ninth transistor (M3) is connected with the drain of the tenth transistor (M2), and the gate of the ninth transistor (M3) is connected with the gate of the eleventh transistor (M5) and the bias circuit (6); the source of the tenth transistor (M2) is connected with a power supply end, and the gate of the tenth transistor (M2) is also connected with the gate of a twelfth transistor (M6); the drain of the eleventh transistor (M5) is connected with the differential output circuit (5), the source of the eleventh transistor (M5) is connected with the drain of the twelfth transistor (M6), and the gate of the eleventh transistor (M5) is connected with the gate of the thirteenth transistor (M11); the source of the twelfth transistor (M6) is connected with the power supply end; the gate of the thirteenth transistor (M11) is connected with the gate of the fourteenth transistor (M10), the source of the thirteenth transistor (M11) is connected with the fifteenth transistor (M13), the drain of the thirteenth transistor (M11) is connected with the non-inverting input end of the second operational amplifier (I12), the drain of the forty-first transistor (M9), and the source of the forty-first transistor (M9) is connected with the drain of the forty-fifth transistor (M8); the inverting input end of the second operational amplifier (I12) is connected with the differential output circuit (5); the gate of the fourteenth transistor (M10) is connected with the bias circuit (6), the source of the fourteenth transistor (M10) is connected with the drain of the sixteenth transistor (M12), and the drain of the fourteenth transistor (M10) is connected with the differential output circuit (5); the gate of the fifteenth transistor (M13) is connected with the output end of the second operational amplifier (I12) and the gate of the sixteenth transistor (M12), and the source of the fifteenth transistor (M13) and the source of the sixteenth transistor (M12) are both connected with a power supply end.
6. Charge pump for FPGA chips according to claim 5, characterized in that the biasing circuit (6) comprises: a twenty-fifth transistor (xi8), a thirty-fourth transistor (xi9), a thirty-fifth transistor (xi11), a thirty-sixth transistor (xi10), a thirty-eighth transistor (xi56), a thirty-ninth transistor (xi44), a forty-second transistor (M4), a forty-third transistor (xi45), a forty-sixth transistor (xi 43); wherein,
the gate of the twenty-fifth transistor (xi8) is connected with the fourth transistor (xi2), the source of the twenty-fifth transistor (xi8) is connected with the drain of the thirty-fourth transistor (xi9), and the drain of the twenty-fifth transistor (xi8) is connected with the fifth port (cpi _ p) and the output differential mode zero clearing circuit (4);
a thirty-fourth transistor (xi9) gate is connected with the sixth transistor (xi3) gate;
the source of the thirty-fifth transistor (xi11) is connected with the drain of the thirty-sixth transistor (xi10), and the drain of the thirty-fifth transistor (xi11) is connected with a sixth port (cpi _ n) and the output differential mode zero clearing circuit (4);
the gate of the thirty-eighth transistor (xi56) is connected with the drain of the thirty-eighth transistor (xi56), the gate of the thirty-ninth transistor (xi44), the gate of the forty-first transistor (M1) and the gate of the forty-first transistor (M9), and the source of the thirty-eighth transistor (xi56) is connected with the source of the forty-second transistor (M4), the source of the forty-third transistor (xi45), the source of the forty-fourth transistor (M0), the source of the forty-fifth transistor (M8) and the ground voltage terminal; the drain electrode of the thirty-eighth transistor (xi56) is connected with the output end of the first current source (I6);
the source of the thirty-ninth transistor (xi44) is connected with the drain of the forty-third transistor (xi45), and the drain of the thirty-ninth transistor (xi44) is connected with the drain of the forty-sixth transistor (xi 43);
the gate of the forty-second transistor (M4) is connected with the gate of the forty-third transistor (xi45) and is connected with the gate of the forty-fourth transistor (M0) and the gate of the forty-fifth transistor (M8), and the drain of the forty-second transistor (M4) is connected with the output end of a second current source (I5);
the gate of the forty-sixth transistor (xi43) is connected to the drain of the forty-sixth transistor (xi43) and the gate of the ninth transistor (M3), and the source of the forty-sixth transistor (xi43) is connected to the input terminal of the first current source (I6), the input terminal of the second current source (I5) and the power supply terminal.
7. Charge pump for FPGA chips according to claim 6, characterized in that said differential output circuit (5) comprises: a thirty-third transistor (xi13), a thirty-seventh transistor (xi 12);
the gate of the thirty-third transistor (xi13) is connected with the gate of a thirty-seventh transistor (xi12), and the drain of the thirty-third transistor (xi13) is connected with the fifth port (cpi _ p) and the drain of the eleventh transistor (M5);
the drain of the thirty-seventh transistor (xi12) is connected to the drain of the fourteenth transistor (M10) and the sixth port (cpi _ n).
8. The charge pump for FPGA chips of claim 7, wherein said common mode negative feedback circuit (2) comprises: a seventeenth transistor (xi42), an eighteenth transistor (xi41), a nineteenth transistor (xi38), a twentieth transistor (xi39), a twenty-first transistor (xi47), a twentieth transistor (xi40), a twenty-third transistor (xi48), a twenty-fourth transistor (xi49), a twenty-seventh transistor (xi37), a twenty-eighth transistor (xi112), a twenty-ninth transistor (xi14), a thirty transistor (xi15), a thirty transistor (xi36), a first resistor (xi109), a second resistor (xi105), wherein,
the gate of the seventeenth transistor (xi42) is connected with the fifth port (cpi _ p), the source of the seventeenth transistor (xi42) is connected with the source of the eighteenth transistor (xi41) and the drain of the nineteenth transistor (xi38), and the drain of the seventeenth transistor (xi42) is connected with the drain of the twentieth transistor (xi39), the drain of the twenty-first transistor (xi47) and the gate of the twenty-first transistor (xi 47);
the gate of the eighteenth transistor (xi41) is connected with one end of a second transistor (xi40), one end of a first resistor (xi109), one end of a second resistor (xi105), the anode of a first capacitor (xi96) and a power supply voltage dividing end (vcom), the other end of the second resistor (xi105) is connected with the power supply end, and the drain of the eighteenth transistor (xi41) is connected with the drain of the second transistor (xi40), the drain of a twenty-third transistor (xi48) and the gate of a twenty-fourth transistor (xi 49);
the gate of the nineteenth transistor (xi38) is connected with the gates of the twenty-fifth transistor (xi8) and the twenty-sixth transistor (xi35), and the source of the nineteenth transistor (xi38) is connected with the drain of the twenty-seventh transistor (xi 37);
the gate of the twentieth transistor (xi39) is connected to the sixth port (cpi _ n), the source of the twentieth transistor (xi39) is connected to the source of the twentieth transistor (xi40) and the drain of the twenty-sixth transistor (xi 35);
the source of the twenty-first transistor (xi47) is connected with the source of a twenty-ninth transistor (xi14), the source of a thirtieth transistor (xi15), the source of a twenty-fourth transistor (xi49) and the power supply end;
the source of the twenty-second transistor (xi40) is connected with the drain of a twenty-sixth transistor (xi 35);
the gate of the twenty-third transistor (xi48) is connected with the gates of the fourteenth transistor (M10) and the thirty-third transistor (xi13), and the source of the twenty-third transistor (xi48) is connected with the drain of the twenty-fourth transistor (xi 49);
the gate of the twenty-fourth transistor (xi49) is connected with the gate of the twenty-ninth transistor (xi 14);
the gate of the twenty-sixth transistor (xi35) is connected with the gate of a thirty-fifth transistor (xi11), and the source of the twenty-sixth transistor (xi35) is connected with the drain of the thirty-second transistor (xi 36);
the gate of the twenty-seventh transistor (xi37) is connected to the gate of the thirty-second transistor (xi36), the gate of the thirty-fourth transistor (xi9), and the source of the twenty-seventh transistor (xi37) is connected to the source of the thirty-fourth transistor (xi9), the source of the thirty-second transistor (xi36), the source of the thirty-sixth transistor (xi10), the source of the twenty-eighth transistor (xi112), the cathode of the first capacitor (xi96), and the ground voltage terminal;
the gate of the twenty-eighth transistor (xi112) is connected with the drain of the twenty-eighth transistor (xi112) and the other end of the first resistor (xi 109);
the gate of the twenty-ninth transistor (xi14) is connected to the gate of the thirtieth transistor (xi15), and the drain of the twenty-ninth transistor (xi14) is connected to the source of the thirty-third transistor (xi13), the drain of the eighth transistor (xi1) and the drain of the second transistor (xi 6);
the drain of the thirtieth transistor (xi15) is connected with the source of a thirty-sixth transistor (xi12), the drain of the first transistor (xi7) and the drain of the seventh transistor (xi 0);
the gate of the thirty-second transistor (xi36) is connected with the gate of the thirty-sixth transistor (xi 10).
9. The charge pump for FPGA chips of claim 8, wherein said enable switch (7) comprises a first enable switch (xi29), a second enable switch (M7), a third enable switch (xi 77);
the first enabling switch (xi29) is connected between the power supply end and the second resistor (xi105) and is used for controlling the connection or disconnection of the power supply end and the second resistor (xi 105);
the second enable switch (M7) is connected between the gate of the forty-second transistor (M4) and the ground voltage terminal;
the third enable switch (xi77) is connected between the thirty-eighth transistor (xi56) gate and the ground voltage terminal.
10. The charge pump for FPGA chips of claim 9, wherein said first enable switch (xi29), said second enable switch (M7), and said third enable switch (xi77) are all transistor switches.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721687629.3U CN207573238U (en) | 2017-12-06 | 2017-12-06 | A kind of charge pump for fpga chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721687629.3U CN207573238U (en) | 2017-12-06 | 2017-12-06 | A kind of charge pump for fpga chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207573238U true CN207573238U (en) | 2018-07-03 |
Family
ID=62687189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721687629.3U Withdrawn - After Issue CN207573238U (en) | 2017-12-06 | 2017-12-06 | A kind of charge pump for fpga chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207573238U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107749709A (en) * | 2017-12-06 | 2018-03-02 | 西安智多晶微电子有限公司 | A kind of charge pump for fpga chip |
-
2017
- 2017-12-06 CN CN201721687629.3U patent/CN207573238U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107749709A (en) * | 2017-12-06 | 2018-03-02 | 西安智多晶微电子有限公司 | A kind of charge pump for fpga chip |
| CN107749709B (en) * | 2017-12-06 | 2023-07-07 | 西安智多晶微电子有限公司 | Charge pump for FPGA chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106685415B (en) | Charge pump circuit and phase-locked loop | |
| CN107749709B (en) | Charge pump for FPGA chip | |
| US20080191783A1 (en) | Symmetric charge pump replica bias detector | |
| CN103346784B (en) | A kind of matching type charge pump circuit for phase-locked loop | |
| CN107846217A (en) | Self-correction circuit | |
| US20070109031A1 (en) | Charge pump circuit with regulated current output | |
| TWI684329B (en) | Voltage regulator based loop filter for loop circuit and loop filtering method | |
| CN107896108B (en) | Charge pump circuit for phase locked loop | |
| CN101414784A (en) | Charge pump | |
| CN102097933B (en) | Charge pump and method thereof | |
| CN112383304B (en) | Charge pump phase-locked loop based on unipolar thin film transistor, chip and method | |
| CN207573238U (en) | A kind of charge pump for fpga chip | |
| CN113839649B (en) | Relaxation oscillator, integrated circuit and electronic device | |
| CN103683937B (en) | Voltage conversion circuit | |
| CN202617095U (en) | Phase locked loop charge pump circuit with low current mismatch | |
| CN102130681B (en) | A kind of differential phase lock loop | |
| CN110719088A (en) | Clock generating circuit and hybrid circuit | |
| US9083359B2 (en) | Lock detector based on charge pump | |
| CN102739043B (en) | Charge pump circuit | |
| CN103036423B (en) | Charge pump circuit used for phase-locked loop | |
| CN111262580A (en) | Low stray phase-current conversion circuit based on floating voltage domain | |
| US8368443B1 (en) | Differential charge pump circuit | |
| US8149031B1 (en) | Duty-cycle feedback charge pump | |
| CN103887966B (en) | Charge pump realizes circuit | |
| US9136831B2 (en) | Frequency to voltage converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Charge pump used for field programmable gate array (FPGA) chip Effective date of registration: 20180824 Granted publication date: 20180703 Pledgee: Pudong Development Bank of Shanghai Limited by Share Ltd. Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, INC. Registration number: 2018610000136 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20201228 Granted publication date: 20180703 Pledgee: Pudong Development Bank of Shanghai Limited by Share Ltd. Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, Inc. Registration number: 2018610000136 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20180703 Effective date of abandoning: 20230707 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20180703 Effective date of abandoning: 20230707 |
|
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |