CN207557403U - Automate electric wire detection device - Google Patents
Automate electric wire detection device Download PDFInfo
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- CN207557403U CN207557403U CN201721853056.7U CN201721853056U CN207557403U CN 207557403 U CN207557403 U CN 207557403U CN 201721853056 U CN201721853056 U CN 201721853056U CN 207557403 U CN207557403 U CN 207557403U
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Abstract
The utility model discloses automation electric wire detection device, main contents are：The CCD driving circuits are connect respectively with X to ccd sensor and Y-direction ccd sensor, X is connect to ccd sensor with the first pre-amplification circuit, first pre-amplification circuit is connect with the first low-pass filter circuit, first low-pass filter circuit is connect with the first A/D conversion circuits, first A/D conversion circuits are connect with the first FIFO devices, Y-direction ccd sensor is connect with the second pre-amplification circuit, second pre-amplification circuit is connect with the second low-pass filter circuit, and the second low-pass filter circuit is connect with the 2nd A/D conversion circuits.The utility model is simple in structure, using embedded computer technology, hardware circuit module designing technique, it is extended convenient for Measurement channel, it realizes the continuity test of electric wire and Insulation test can rapidly potential faults existing for detection device electric wire, shortening detection time improves detection efficiency in time.
Description
Technical field
The utility model is related to electric wire detection technique field, specifically, more particularly to automating electric wire detection device.
Background technology
Electric wire is the physical medium interconnected between electronic equipment and equipment subelement, is used for transmission the important letter such as signal, energy
Breath, is component part indispensable in electronics and system.Its reliability connected directly affects the synthesis of electronic equipment
Performance, and electric wire communication failure is also as one of major failure reason of electronic device works exception, it is therefore, how efficiently complete
It is examined into electric wire and the inspection of fault location electric wire focuses primarily upon break-make and examines and insulating properties inspection.Traditional method of inspection is
Manually carry out pointwise test using multimeter or buzzer, this method be only applicable to smallest number, small core number electric wire routine inspection,
And there are the shortcomings such as accuracy is poor, testing efficiency is low, can not adapt to high-volume, multiple core cord is examined and the quick row of cable malfunction
It looks into.
Utility model content
The technical problem to be solved by the utility model is to the deficiencies in for the above-mentioned prior art, disclose automation
Electric wire detection device, it is simple in structure, using embedded computer technology, hardware circuit module designing technique, convenient for measuring
Channel extends, and realizes the continuity test of electric wire and Insulation test can rapidly failure existing for detection device electric wire be hidden in time
Suffer from, shorten detection time, improve detection efficiency.
Technical solution is used by the utility model solves its technical problem：Electric wire detection device is automated, including CCD
Driving circuit, X are to ccd sensor, the first pre-amplification circuit, the first low-pass filter circuit, the first A/D conversion circuits, first
FIFO devices, clock circuit, reset circuit, dsp controller, the 2nd FIFO devices, the 2nd A/D conversion circuits, the second low-pass filtering electricity
Road, the second pre-amplification circuit, Y-direction ccd sensor and CPLD devices, the CCD driving circuits are respectively with X to ccd sensor and Y
Connected to ccd sensor, the X connect to ccd sensor with the first pre-amplification circuit, first pre-amplification circuit and
First low-pass filter circuit connects, and first low-pass filter circuit is connect with the first A/D conversion circuits, and the first A/D turns
It changes circuit to connect with the first FIFO devices, the Y-direction ccd sensor is connect with the second pre-amplification circuit, is put before described second
Big circuit is connect with the second low-pass filter circuit, and second low-pass filter circuit is connect with the 2nd A/D conversion circuits, and described the
Two A/D conversion circuits are connect with the 2nd FIFO devices, and the first FIFO devices and the 2nd FIFO devices are all connect with dsp controller, institute
State clock circuit and reset circuit all connect with dsp controller, the CPLD devices respectively with the first FIFO devices and the 2nd FIFO devices
It is connected, the CPLD devices are connect respectively with CCD driving circuits, the first A/D conversion circuits and the 2nd A/D conversion circuits.
As a kind of preferred embodiment of the utility model, first pre-amplification circuit by resistance R1, resistance R2,
Resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance R11, capacitance C1, capacitance
C2, capacitance C3 and operational amplifier LM318 compositions, after the capacitance C1 and capacitance C2 parallel connections left end respectively with power pins+12V
It is connected with resistance R3 right ends, the resistance R3 left ends are connect with the collector of upper triode, the resistance R1 right ends and upper three pole
The base stage connection of pipe, the resistance R2 right ends are connect with the base stage of lower triode, the collection of the resistance R6 left ends and lower triode
Electrode connects, and the resistance R6 right ends connect with power pins+12V, and the resistance R4 left ends and resistance R5 left ends are all with upper three
The emitter connection of pole pipe, the positive input terminal of the resistance R4 right ends and resistance R9 left ends all with operational amplifier LM318 are connect,
The emitter of the resistance R7 left ends and resistance R8 left ends all with lower triode is connect, the capacitance C2 right ends, resistance R10 right ends
It is connect with output terminal of the resistance R11 left ends all with operational amplifier LM318, the resistance R7 right ends, capacitance C2 left ends and resistance
Negative input end of the R10 left ends all with operational amplifier LM318 is connect.
As a kind of preferred embodiment of the utility model, first low-pass filter circuit is by resistance R12, resistance
R13, resistance Rf, capacitance C4, capacitance C5 and operational amplifier LM318 compositions, the resistance R12 right ends and resistance R13 left ends are all
It is connect with capacitance C4 left ends, the resistance R13 right ends and capacitance C5 upper ends all connect with the positive input terminal of operational amplifier LM318
It connects, the resistance Rf left ends are connect with the negative input end of operational amplifier LM318, and the capacitance C4 right ends and resistance Rf right ends are all
It is connect with the output terminal of operational amplifier LM318.
As a kind of preferred embodiment of the utility model, the clock circuit is by capacitance C21, capacitance C22 and crystal oscillator
Composition, the capacitance C21 upper ends are connect with crystal oscillator upper end, and the capacitance C22 lower ends are connect with crystal oscillator lower end, the capacitance C21
Lower end and capacitance C22 upper ends are all grounded.
The utility model is made of ccd sensor and driving, slave computer and host computer three parts.The device uses CCD
Sensor is used for receiving the image information of X-ray transmission wire cross-sectional, and driving pulse is provided by CPLD devices, and in addition A/D is converted
The logic control of device and data buffer FIFO are also completed by CPLD devices.
The order acquired being sent by host computer, at this point, DSP receives the acquisition of host computer by serial line interface,
Then instruction is sent out to CPLD, CPLD is enable to start transmission and meets the time sequential pulse that TCD1206 is worked normally.CCD is through driving
A/D converter is sent into after the preprocessed the regulation of electrical circuit of raw video signal exported afterwards.It samples, quantify, encode through A/D converter
Data afterwards are written into FIFO, and in this process, the clock signal of A/D converter, the write signal of FIFO are sent by CPLD,
After a frame of ccd sensor is converted by carrying the image-sensitive member signal of wire cross-sectional information, A/D converter enabled and
The read-write of FIFO is controlled by DSP, meanwhile, DSP is by continuously transmitting the control of serial line interface to complete the high speed of data.When
After one frame signal end of transmission, then from host computer to DSP transmission acquisitions, repeat the above-mentioned course of work.
The utility model has the following advantages compared with prior art：It is simple in structure, using embedded computer technology, firmly
Part circuit modular designing technique extends convenient for Measurement channel, and the continuity test and Insulation test for realizing electric wire can be fast in time
Potential faults existing for fast ground detection device electric wire, shorten detection time, improve detection efficiency.
Description of the drawings
Fig. 1 is a kind of structure diagram of specific embodiment of the utility model；
Fig. 2 is a kind of circuit diagram of first pre-amplification circuit of specific embodiment of the utility model；
Fig. 3 is a kind of circuit diagram of first low-pass filter circuit of specific embodiment of the utility model；
Fig. 4 is a kind of circuit diagram of the first A/D conversion circuits of specific embodiment of the utility model；
Fig. 5 is a kind of circuit diagram of specific embodiment clock circuit of the utility model；
Fig. 6 is a kind of circuit diagram of specific embodiment reset circuit of the utility model.
Reference sign：
1：CCD driving circuits, 2：X is to ccd sensor, and 3：First pre-amplification circuit, 4：First low-pass filter circuit, 5：
First A/D conversion circuits, 6：First FIFO devices, 7：Clock circuit, 8：Reset circuit, 9：Dsp controller, 10：2nd FIFO devices,
11：2nd A/D conversion circuits, 12：Second low-pass filter circuit, 13：Second pre-amplification circuit, 14：Y-direction ccd sensor,
15：CPLD devices；
R1、R2、R3、R4、R5、R6、R7、R8、R9、R10、R11、R12、R13、Rf、R25：Resistance, C1, C2, C3, C4,
C5、C8、C9、C10、C11、C12、C13、C14、C15、C16、C21、C22、C23、C24：Capacitance, LM318：Operational amplifier,
TLC5510：Analog-digital converter, IDT72230：Data buffer storage chip, S1：Reset button.
Specific embodiment
Specific embodiment of the present invention is described with reference to the accompanying drawings and embodiments：
It should be noted that structure, ratio, size for illustrating in this specification institute attached drawing etc., only coordinating explanation
So that those skilled in the art understands and reads, it is enforceable to be not limited to the utility model for the revealed content of book
Qualifications, the modification of any structure, the change of proportionate relationship or the adjustment of size, can be generated not influencing the utility model
The effect of and the purpose that can reach under, should all still fall and obtain the range that can cover in the revealed technology contents of the utility model
It is interior.
Meanwhile cited such as " on ", " under " in this specification, "left", "right", " centre " and " one " term, also
Only understanding rather than to limit the enforceable range of the utility model for ease of narration, relativeness is altered or modified,
In the case where changing technology contents without essence, when being also considered as the enforceable scope of the utility model.
As shown in Figure 1, it illustrates specific embodiment of the present utility model；As shown in the figure, disclosed in the utility model
A kind of automation electric wire detection device, including CCD driving circuits 1, X to ccd sensor 2, the first pre-amplification circuit 3, first
Low-pass filter circuit 4, the first A/D conversion circuits 5, the first FIFO devices 6, clock circuit 7, reset circuit 8, dsp controller 9,
Two FIFO devices 10, the 2nd A/D conversion circuits 11, the second low-pass filter circuit 12, the second pre-amplification circuit 13, Y-direction CCD sensings
Device 14 and CPLD devices 15, the CCD driving circuits 1 are connect respectively with X to ccd sensor 2 and Y-direction ccd sensor 14, the X
It is connect to ccd sensor 2 with the first pre-amplification circuit 3,3 and first low-pass filter circuit 4 of the first pre-amplification circuit
Connection, first low-pass filter circuit 4 are connect with the first A/D conversion circuits 5, the first A/D conversion circuits 5 and first
FIFO devices 6 connect, and the Y-direction ccd sensor 14 is connect with the second pre-amplification circuit 13, second pre-amplification circuit 13
It being connect with the second low-pass filter circuit 12, second low-pass filter circuit 12 is connect with the 2nd A/D conversion circuits 11, and described
Two A/D conversion circuits 11 are connect with the 2nd FIFO devices 10, the first FIFO devices 6 and the 2nd FIFO devices 10 all with dsp controller 9
Connection, the clock circuit 7 and reset circuit 8 all connect with dsp controller 9, the CPLD devices 15 respectively with the first FIFO devices 6
It is connected with the 2nd FIFO devices 10, the CPLD devices 15 turn respectively with CCD driving circuits 1, the first A/D conversion circuits 5 and the 2nd A/D
Circuit 11 is changed to connect.
Preferably, first pre-amplification circuit 3 is by resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance
R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance R11, capacitance C1, capacitance C2, capacitance C3 and operational amplifier LM318
Left end is connect respectively with power pins+12V and resistance R3 right ends after composition, the capacitance C1 and capacitance C2 parallel connections, the resistance
R3 left ends are connect with the collector of upper triode, and the resistance R1 right ends are connect with the base stage of upper triode, and the resistance R2 is right
End connect with the base stage of lower triode, the resistance R6 left ends are connect with the collector of lower triode, the resistance R6 right ends and
Power pins+12V connections, the emitter of the resistance R4 left ends and resistance R5 left ends all with upper triode are connect, the resistance
The positive input terminal of R4 right ends and resistance R9 left ends all with operational amplifier LM318 is connect, and the resistance R7 left ends and resistance R8 are left
The emitter all with lower triode is held to connect, the capacitance C2 right ends, resistance R10 right ends and resistance R11 left ends are all put with operation
The output terminal connection of big device LM318, the resistance R7 right ends, capacitance C2 left ends and resistance R10 left ends all with operational amplifier
The negative input end connection of LM318.
Preferably, first low-pass filter circuit 4 by resistance R12, resistance R13, resistance Rf, capacitance C4, capacitance C5 and
Operational amplifier LM318 is formed, and the resistance R12 right ends and resistance R13 left ends are all connect with capacitance C4 left ends, the resistance
The positive input terminal of R13 right ends and capacitance C5 upper ends all with operational amplifier LM318 is connect, the resistance Rf left ends and operation amplifier
The negative input end connection of device LM318, the capacitance C4 right ends and resistance Rf right ends all connect with the output terminal of operational amplifier LM318
It connects.
Preferably, the clock circuit 7 is made of capacitance C21, capacitance C22 and crystal oscillator, the capacitance C21 upper ends and crystal oscillator
Upper end connects, and the capacitance C22 lower ends are connect with crystal oscillator lower end, and the capacitance C21 lower ends and capacitance C22 upper ends are all grounded.
The utility model preferred embodiment is explained in detail above in conjunction with attached drawing, but the utility model is not limited to
The above embodiment within the knowledge of a person skilled in the art, can also not depart from the utility model
It is made a variety of changes under the premise of objective.Many other changes can be made and change by not departing from the conception and scope of the utility model
Type.It should be appreciated that the utility model is not limited to specific embodiment, the scope of the utility model is limited by appended claims
It is fixed.
Claims (4)
1. automate electric wire detection device, it is characterised in that：Including CCD driving circuits, X to ccd sensor, the first preposition amplification
Circuit, the first low-pass filter circuit, the first A/D conversion circuits, the first FIFO devices, clock circuit, reset circuit, dsp controller,
2nd FIFO devices, the 2nd A/D conversion circuits, the second low-pass filter circuit, the second pre-amplification circuit, Y-direction ccd sensor and
CPLD devices, the CCD driving circuits are connect respectively with X to ccd sensor and Y-direction ccd sensor, the X to ccd sensor with
First pre-amplification circuit connects, and first pre-amplification circuit is connect with the first low-pass filter circuit, first low pass
Filter circuit is connect with the first A/D conversion circuits, and the first A/D conversion circuits are connect with the first FIFO devices, the Y-direction CCD
Sensor is connect with the second pre-amplification circuit, and second pre-amplification circuit is connect with the second low-pass filter circuit, described
Second low-pass filter circuit is connect with the 2nd A/D conversion circuits, and the 2nd A/D conversion circuits are connect with the 2nd FIFO devices, institute
State the first FIFO devices and the 2nd FIFO devices all connect with dsp controller, the clock circuit and reset circuit all with dsp controller
Connection, the CPLD devices are connected respectively with the first FIFO devices and the 2nd FIFO devices, the CPLD devices respectively with CCD driving circuits,
First A/D conversion circuits and the connection of the 2nd A/D conversion circuits.
2. automation electric wire detection device as described in claim 1, it is characterised in that：First pre-amplification circuit is by electricity
Hinder R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance R11,
Capacitance C1, capacitance C2, capacitance C3 and operational amplifier LM318 compositions, after the capacitance C1 and capacitance C2 parallel connections left end respectively with
Power pins+12V is connected with resistance R3 right ends, and the resistance R3 left ends are connect with the collector of upper triode, the resistance R1
Right end is connect with the base stage of upper triode, and the resistance R2 right ends are connect with the base stage of lower triode, the resistance R6 left ends with
The collector connection of lower triode, the resistance R6 right ends are connect with power pins+12V, the resistance R4 left ends and resistance R5
Emitter of the left end all with upper triode is connect, and the resistance R4 right ends and resistance R9 left ends are all with operational amplifier LM318's
Positive input terminal connects, and the emitter of the resistance R7 left ends and resistance R8 left ends all with lower triode is connect, and the capacitance C2 is right
End, the output terminal of resistance R10 right ends and resistance R11 left ends all with operational amplifier LM318 are connect, the resistance R7 right ends, electricity
Hold the negative input end of C2 left ends and resistance R10 left ends all with operational amplifier LM318 to connect.
3. automation electric wire detection device as described in claim 1, it is characterised in that：First low-pass filter circuit is by electricity
Hinder R12, resistance R13, resistance Rf, capacitance C4, capacitance C5 and operational amplifier LM318 compositions, the resistance R12 right ends and resistance
R13 left ends are all connect with capacitance C4 left ends, the resistance R13 right ends and capacitance C5 upper ends all with operational amplifier LM318 just
Input terminal connects, and the resistance Rf left ends are connect with the negative input end of operational amplifier LM318, the capacitance C4 right ends and resistance
Output terminal of the Rf right ends all with operational amplifier LM318 is connect.
4. automation electric wire detection device as described in claim 1, it is characterised in that：The clock circuit is by capacitance C21, electricity
Holding C22 and crystal oscillator composition, the capacitance C21 upper ends are connect with crystal oscillator upper end, and the capacitance C22 lower ends are connect with crystal oscillator lower end,
The capacitance C21 lower ends and capacitance C22 upper ends are all grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721853056.7U CN207557403U (en) | 2017-12-26 | 2017-12-26 | Automate electric wire detection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721853056.7U CN207557403U (en) | 2017-12-26 | 2017-12-26 | Automate electric wire detection device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207557403U true CN207557403U (en) | 2018-06-29 |
Family
ID=62660701
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721853056.7U Expired - Fee Related CN207557403U (en) | 2017-12-26 | 2017-12-26 | Automate electric wire detection device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207557403U (en) |
-
2017
- 2017-12-26 CN CN201721853056.7U patent/CN207557403U/en not_active Expired - Fee Related
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| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180629 Termination date: 20181226 |
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| CF01 | Termination of patent right due to non-payment of annual fee |