CN207490577U - A kind of intelligent solar energy storage timing automatically wakes up protection board in 24 hours - Google Patents
A kind of intelligent solar energy storage timing automatically wakes up protection board in 24 hours Download PDFInfo
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- CN207490577U CN207490577U CN201721724931.1U CN201721724931U CN207490577U CN 207490577 U CN207490577 U CN 207490577U CN 201721724931 U CN201721724931 U CN 201721724931U CN 207490577 U CN207490577 U CN 207490577U
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- 238000004146 energy storage Methods 0.000 title claims abstract description 11
- 239000000654 additive Substances 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims description 24
- 238000007689 inspection Methods 0.000 claims description 9
- 230000005611 electricity Effects 0.000 abstract description 7
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052744 lithium Inorganic materials 0.000 abstract description 2
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
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- 238000005516 engineering process Methods 0.000 description 3
- 241001424688 Enceliopsis Species 0.000 description 2
- 230000037007 arousal Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000002618 waking effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
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Abstract
The utility model discloses a kind of intelligent solar energy storage timings to automatically wake up protection board in 24 hours; including discharge loop, charge circuit, electric discharge overcurrent and short-circuit detecting circuit, overdischarge additives for overcharge protection circuit, auto sleep and timing 24 hours and external voltage wake-up circuit; discharge loop with electric discharge overcurrent and short-circuit detecting circuit, overdischarge additives for overcharge protection circuit, auto sleep and timing 24 hours and external voltage wake-up circuit be electrically connected, overdischarge additives for overcharge protection circuit is electrically connected with charge circuit.The utility model has 6 economize on electricity core series connection defencive functions；The various defencive functions being charged and discharged；The overcurrent of hardware, short-circuit protection function；Auto sleep shut-off function, external voltage input wakes up or 24 hours functions of automatically turning on electric discharge MOS of timing, reduces stand-by power consumption, and can improve lithium battery working efficiency makes equipment task time more permanent, while avoids battery because the big appearance of power consumption is without electrical phenomena.
Description
Technical field
The utility model is related to power technique fields more particularly to a kind of intelligent solar energy storage timing 24 hours are automatic
Wake up protection board.
Background technology
At present, for appear on the market upper solar energy protection board and online equipment when stand-by power consumption it is big, during rainy days, sunray is not
For foot without solar energy, equipment is in standby mode and power consumption 1.2A or so, treats that chance causes battery drain serious for a long time, leads to electricity
The phenomenon that pond out of power.
In order to overcome the problems, such as that existing solar energy protection board standby power consumption is big, need a according to load equipment operating current
State set-point size and the 24 hours protection boards for automatically waking up and waking up manually in auto sleep interval for closing output.It realizes
When cloudy day is without sunray, protection board intelligently closes output, and reaches stand-by power consumption electric current and drop to μ A ranks by A ranks, so as to
Improve solar energy storage batteries service efficiency.
Utility model content
In view of the drawbacks described above of the prior art, the technical problem to be solved by the utility model is to provide a kind of intelligent
Solar energy storage timing automatically wakes up protection board in 24 hours, to solve the deficiencies in the prior art.
To achieve the above object, the utility model provides a kind of intelligent solar energy storage timing and automatically wakes up for 24 hours
Protection board, including discharge loop, charge circuit, electric discharge overcurrent and short-circuit detecting circuit, overdischarge additives for overcharge protection circuit, automatic
Suspend mode and timing 24 hours and external voltage wake-up circuit, the discharge loop are put with electric discharge overcurrent and short-circuit detecting circuit, mistake
Electric additives for overcharge protection circuit, auto sleep and timing 24 hours and the electrical connection of external voltage wake-up circuit, the overdischarge overcharges
Electric protection circuit is electrically connected with charge circuit, wherein：
The discharge loop include sequentially connected battery anode, load anode, load cathode, charging MOS (M4~
M6), electric discharge MOS (M1~M3), inspection leakage resistance (RN1~2), battery electrode；
The charge circuit includes sequentially connected charger anode, battery anode, battery electrode, inspection leakage resistance
(RN1~2), electric discharge MOS (M1~M3), charging MOS (M4~M6), charger cathode；
It is S-8261ABPMD-G3P- that the electric discharge overcurrent and short-circuit detecting circuit, which include chip U11, the chip U11,
The grid of the 1 foot connection metal-oxide-semiconductor Q16 of T2S, the chip U11, the source electrode ground connection of the metal-oxide-semiconductor Q16, the metal-oxide-semiconductor Q16's
Input terminal 5,6 feet of drain electrode connection NAND gate U7C, 4 foot of output terminal of the NOT gate U7C pass through diode D5 connection NOT gates U7A
13 foot of input terminal, 11 foot of output terminal of the NAND gate U7A passes through 1 foot of input terminal of resistance R35 connection NAND gates U7D, institute
10 foot of output terminal of 2 foot of the input terminal connection NAND gate U7B of NAND gate U7D is stated, 3 foot of output terminal of the NAND gate U7D passes through
Resistance R43 connections electric discharge MOS (M1~M3) grid, the electric discharge MOS (M1~M3) connect resistance R29 between grid and source electrode；
The overdischarge additives for overcharge protection circuit includes chip U1, and the chip U1 is S-8261ABMMD-G3M-T2S, institute
1 foot for stating chip U1 passes through the base stage of resistance RD1 connection PNP triodes Q1, the collector connection NPN of the PNP triode Q1
Triode Q13 base stages, 3 collector of NPN triode Q1 connects 13 foot of input terminal of NAND gate U7A by resistance R34, described
11 foot of output terminal of NAND gate U7A passes through 1 foot of input terminal of resistance R35 connection NAND gates U7D, the input of the NAND gate U7D
10 foot of output terminal of 2 feet connection NAND gate U7B is held, 3 foot of output terminal of the NAND gate U7D passes through resistance R43 connections electric discharge MOS
(M1~M3) grid, the electric discharge MOS (M1~M3) connect resistance R29 between grid and source electrode；3 feet of the chip U1 pass through
The base stage of resistance RC1 connection PNP triodes Q2, the collector of the PNP triode Q2 pass through resistance R16, diode D1 connections
7 base stage of NPN triode Q1, the collector of the NPN triode Q1 7 connect the grid of charging MOS (M4~M6) with emitter respectively
Pole and source electrode；
The auto sleep and timing 24 hours and external voltage wake-up circuit be including microcontroller U8, the microcontroller U8
Microcontroller is EM78P301-8, and the 2 foot output terminal K2 of the microcontroller U8 pass through the grid of resistance R45 connection metal-oxide-semiconductors Q19, institute
The drain electrode of metal-oxide-semiconductor Q19 is stated by the grid of resistance R48 connection metal-oxide-semiconductors Q20, input terminal 8,9 feet of the NAND gate U7B pass through
Capacitance C15 is sequentially connected resistance R26, R50, R27, power supply VCC, the F1-2 ends connection metal-oxide-semiconductor between described resistance R26, R50
The source electrode of Q20, the drain electrode of the F1-1 ends connection metal-oxide-semiconductor Q20 between described resistance R50, R27；The 6 feet input of the microcontroller U8
Hold K1 connection photoelectrical coupler U10 output terminals, the photoelectrical coupler U10 input terminals connection electric socket J2.
A kind of above-mentioned intelligent solar energy storage timing automatically wakes up protection board for 24 hours, and the overdischarge overcharge is protected
Protection circuit is identical be sequentially connected in series 6 groups.
The beneficial effects of the utility model are：
The utility model has 6 economize on electricity core series connection defencive functions；The various defencive functions being charged and discharged；The mistake of hardware
Stream, short-circuit protection function；Auto sleep shut-off function, external voltage input wakes up or timing automatically turns on electric discharge in 24 hours
The function of MOS reduces stand-by power consumption, and can improve lithium battery working efficiency makes equipment task time more permanent, while avoid electricity
Pond is because the big appearance of power consumption is without electrical phenomena.
The technique effect of the design of the utility model, concrete structure and generation is made furtherly below with reference to attached drawing
It is bright, to be fully understood from the purpose of this utility model, feature and effect.
Description of the drawings
Fig. 1 is the overall structure block diagram of the utility model.
Fig. 2 is the discharge loop, charge circuit, electric discharge overcurrent and short-circuit detecting circuit schematic diagram of the utility model.
Fig. 3 be the utility model auto sleep and timing 24 hours and external voltage wake-up circuit in control circuit principle
Figure.
Fig. 4 is the overdischarge additives for overcharge protection circuit diagram of the utility model.
Fig. 5 be the utility model auto sleep and timing 24 hours and external voltage wake-up circuit in Fundamentals of Mono-Chip Computers
Figure.
Specific embodiment
As shown in Figure 1, a kind of intelligent solar energy storage timing automatically wakes up protection board in 24 hours, including discharge loop 1,
Charge circuit 2, electric discharge overcurrent and short-circuit detecting circuit 3, overdischarge additives for overcharge protection circuit 4, auto sleep and periodically 24 hours
And external voltage wake-up circuit 5, the discharge loop 1 and electric discharge overcurrent and short-circuit detecting circuit 3, overdischarge additives for overcharge protection electricity
Road 4, auto sleep and timing 24 hours and external voltage wake-up circuit 5 be electrically connected, the overdischarge additives for overcharge protection circuit 4 with
Charge circuit 2 is electrically connected, wherein：
As shown in Fig. 2, the discharge loop 1 includes sequentially connected battery anode, load anode, load cathode, fills
Electric MOS (M4~M6), electric discharge MOS (M1~M3), inspection leakage resistance (RN1~2), battery electrode；
It is born as shown in Fig. 2, the charge circuit 2 includes sequentially connected charger anode, battery anode, battery pack
Pole, inspection leakage resistance (RN1~2), electric discharge MOS (M1~M3), charging MOS (M4~M6), charger cathode；
As shown in Fig. 2, it is S- that the electric discharge overcurrent and short-circuit detecting circuit 3, which include chip U11, the chip U11,
The grid of the 1 foot connection metal-oxide-semiconductor Q16 of 8261ABPMD-G3P-T2S, the chip U11, the source electrode ground connection of the metal-oxide-semiconductor Q16,
Input terminal 5,6 feet of the drain electrode connection NAND gate U7C of the metal-oxide-semiconductor Q16,4 foot of output terminal of the NOT gate U7C pass through diode
13 foot of input terminal of D5 connection NOT gates U7A, 11 foot of output terminal of the NAND gate U7A pass through resistance R35 connection NAND gates U7D's
1 foot of input terminal, 10 foot of output terminal of 2 foot of the input terminal connection NAND gate U7B of the NAND gate U7D, the NAND gate U7D's is defeated
3 foot of outlet is connected by resistance R43 connections electric discharge MOS (M1~M3) grid, the electric discharge MOS (M1~M3) between grid and source electrode
Connecting resistance R29；
As shown in Figure 2,4, it is S- that the overdischarge additives for overcharge protection circuit 4, which includes chip U1, the chip U1,
1 foot of 8261ABMMD-G3M-T2S, the chip U1 pass through the base stage of resistance RD1 connection PNP triodes Q1, tri- poles of PNP
Collector connection 3 base stage of NPN triode Q1 of pipe Q1,3 collector of NPN triode Q1 connect NAND gate by resistance R34
13 foot of input terminal of U7A, 11 foot of output terminal of the NAND gate U7A by 1 foot of input terminal of resistance R35 connection NAND gates U7D,
10 foot of output terminal of 2 foot of the input terminal connection NAND gate U7B of the NAND gate U7D, 3 foot of output terminal of the NAND gate U7D lead to
Resistance R43 connections electric discharge MOS (M1~M3) grid is crossed, the electric discharge MOS (M1~M3) connects resistance between grid and source electrode
R29；3 feet of the chip U1 are led to by the base stage of resistance RC1 connection PNP triodes Q2, the collector of the PNP triode Q2
Resistance R16,7 base stage of diode D1 connections NPN triode Q1 are crossed, the collector of the NPN triode Q1 7 connects respectively with emitter
Connect the grid and source electrode of charging MOS (M4~M6)；
As shown in Fig. 2,3,5, the auto sleep and timing 24 hours and external voltage wake-up circuit 5 include microcontroller
U8, it is EM78P301-8 that the microcontroller U8, which is microcontroller, and the 2 foot output terminal K2 of the microcontroller U8 are connected by resistance R45
The grid of metal-oxide-semiconductor Q19, the drain electrode of the metal-oxide-semiconductor Q19 pass through the grid of resistance R48 connection metal-oxide-semiconductors Q20, the NAND gate U7B
Input terminal 8,9 feet resistance R26, R50, R27, power supply VCC are sequentially connected by capacitance C15, between described resistance R26, R50
The source electrode of F1-2 ends connection metal-oxide-semiconductor Q20, the drain electrode of the F1-1 ends connection metal-oxide-semiconductor Q20 between described resistance R50, R27；The list
The 6 foot input terminal K1 connection photoelectrical coupler U10 output terminals of piece machine U8, the photoelectrical coupler U10 input terminals connection power supply connect
Socket J2.
In the present embodiment, the chip U11 is S-8261ABPMD-G3P-T2S.
In the present embodiment, the chip U1 is S-8261ABMMD-G3M-T2S.
In the present embodiment, the chip U8 is microcontroller EM78P301-8.
In the present embodiment, the overdischarge additives for overcharge protection circuit 4 is identical be sequentially connected in series 6 groups.
The operation principle of the utility model is：
Charge circuit：From charger anode → battery anode → battery electrode → inspection leakage resistance (RN1~2) → electric discharge
MOS (M1~M3) → charging MOS (M4~M6) → charger cathode.
6 groups of overdischarge additives for overcharge protection circuits 4 detect the voltage for the core that often economizes on electricity, by taking one of which as an example, as shown in figure 4,
When detecting battery core voltage higher than overcharging electro-detection voltage value and when reaching overcharge delay time, the 3rd foot output low level pair
The GS pole tensions of triode Q2 conductings → Q17 is connected → MOS that charges (M4~M6) answered are pulled low 0.3V or so (CE poles of Q17
Pressure drop) → charging MOS (M4~M6) cut-off → cut-out charge circuit.
Discharge loop：From battery anode → load anode → load cathode → charging MOS (M4~M6) → electric discharge MOS
(M1~M3) → inspection leakage resistance (RN1~2) → battery electrode.
6 groups of overdischarge additives for overcharge protection circuits 4 detect the voltage for the core that often economizes on electricity, by taking one of which as an example, as shown in figure 4,
When detecting battery core voltage less than overdischarge detection voltage value and reaching overdischarge delay time, the 1st foot output low level pair
The triode Q 1 answered is connected → and every 13 foot of Q13 conductings → U7 is pulled low, and because U7 is 4 NAND gate IC, logical relation is defeated for two
Enter in foot and export high level (can thering is 0 1) as long as there are one for low level, so the 11 feet output high level of U7 is coupled through R35
1 foot for making U7 is high level；In addition, J2 ends K+ after the power is turned on, in the case that K- does not have voltage, U7 the 8th, 9 feet for low level →
3 feet that then 2 feet of U7 are high level → U7 are low level, and → the GS pole tensions of electric discharge MOS (M1~M3) are dragged down by R29 → discharges
MOS (M1~M3) cut-off → cut-out discharge loop.
U11 detects IC for electric discharge overcurrent and discharge short；
When the voltage at RN1~RN2 both ends is coupled to through R25 the 2nd foot of U11, when the both end voltage of inspection leakage resistance is more than U11
Electric discharge overcurrent, short-circuit detecting voltage setting value and beyond electric discharge overcurrent, short-circuit delay time, the 1 foot output low level of U11 →
5,6 feet of Q16 cut-offs → U7 by R53 resistance draw high for high level → U7 4 feet export low level → U7 13 feet be pulled low →
The 11 feet output high level of U7 makes 1 foot of U7 be high level through R35 couplings；In addition, J2 ends K+, K- do not have the feelings of voltage after the power is turned on
Under condition, U7 the 8th, 3 feet that 9 feet are low level → then 2 feet of U7 are high level → U7 be low level → electric discharge MOS (M1~M3)
GS pole tensions drag down → discharge MOS (M1~M3) cut-off → cut-out discharge loop by R29, so as to fulfill electric discharge overcurrent and short circuit
Function and protecting.
By the fully automated suspend mode of microcontroller U8 and timing 24 hours and external voltage arousal function；
When the voltage at RN1~RN2 both ends is coupled to through R24 the 3rd foot of U8, calculates, detect defeated through A/D conversions inside IC
When going out the continuous 10 minutes≤1.2A of electric current, the 12nd foot of the 2nd foot K2 outputs low level → Q19 cut-offs → Q20 cut-offs → U7 of U8
11 feet for low level → U7 export high level makes 1 foot of U7 be high level through R35 couplings；In addition, J2 ends K+, K- do not have after the power is turned on
In the case of having voltage, U7 the 8th, 3 feet that 9 feet are low level → then 2 feet of U7 are high level → U7 be low level → electric discharge
The GS pole tensions of MOS (M1~M3) drag down → discharge MOS (M1~M3) cut-off → cut-out discharge loop by R29, so as to fulfill certainly
Dynamic sleep mode；
By U8 timer internal timing, timing 24 hours after suspend mode, the 2 foot K2 output high level of U8 the, Q19 conductings →
The 11 feet output high level that the 12nd foot of Q20 conductings → U7 is high level → U7 makes 1 foot of U7 be low level through R35 couplings；Separately
External Q20 is connected moment, U7 the 8th, 9 feet 3 feet of high impulse level → then 2 feet of U7 are low level → U7 are coupled as through C15
For high level, → the GS pole tensions of electric discharge MOS (M1~M3) are drawn high by R29 → MOS that discharges (M1~M3) conducting → opening is discharged back
Road, so as to fulfill 24 hours automatic wake-up functions of timing；
External voltage inputs arousal function；
After there are the access of 25V voltages in J2 ports, optocoupler diode current flow and inside optocoupler triode CE poles inside U10
It is high level that the 6th foot K1 of conducting → U8, which are the 2nd foot K 2 of low level → U8, and the 12nd foot of Q19 conductings → Q20 conductings → U7 is height
The 11 feet output high level of level → U7 makes 1 foot of U7 be low level through R35 couplings；In addition Q20 be connected moment, U7 the 8th,
3 feet that 9 feet are coupled as high impulse level → then 2 feet of U7 are low level → U7 through C15 are high level → electric discharge MOS (M1~M3)
GS pole tensions draw high → discharge MOS (M1~M3) conducting → opening discharge loop by R29, so as to fulfill external voltage input call out
Awake function.
The preferred embodiment of the utility model described in detail above.It should be appreciated that the ordinary skill people of this field
Member according to the present utility model can conceive without creative work makes many modifications and variations.Therefore, all this technology necks
Technical staff passes through logic analysis, reasoning or limited reality on the basis of existing technology according to the design of the utility model in domain
Available technical solution is tested, it all should be in the protection domain being defined in the patent claims.
Claims (2)
1. a kind of intelligent solar energy storage timing automatically wakes up protection board in 24 hours, it is characterised in that：Including discharge loop
(1), charge circuit (2), electric discharge overcurrent and short-circuit detecting circuit (3), overdischarge additives for overcharge protection circuit (4), auto sleep and
Periodically 24 hours and external voltage wake-up circuit (5), the discharge loop (1) and electric discharge overcurrent and short-circuit detecting circuit (3), mistake
Electric discharge additives for overcharge protection circuit (4), auto sleep and periodically 24 hours and external voltage wake-up circuit (5) electrical connection, the mistake
Electric discharge additives for overcharge protection circuit (4) is electrically connected with charge circuit (2), wherein：
The discharge loop (1) including sequentially connected battery anode, load anode, load cathode, charging MOS (M4~
M6), electric discharge MOS (M1~M3), inspection leakage resistance (RN1~2), battery electrode；
The charge circuit (2) includes sequentially connected charger anode, battery anode, battery electrode, inspection leakage resistance
(RN1~2), electric discharge MOS (M1~M3), charging MOS (M4~M6), charger cathode；
The electric discharge overcurrent and short-circuit detecting circuit (3) include chip U11, and the chip U11 is S-8261ABPMD-G3P-
The grid of the 1 foot connection metal-oxide-semiconductor Q16 of T2S, the chip U11, the source electrode ground connection of the metal-oxide-semiconductor Q16, the metal-oxide-semiconductor Q16's
Input terminal 5,6 feet of drain electrode connection NAND gate U7C, 4 foot of output terminal of the NOT gate U7C pass through diode D5 connection NOT gates U7A
13 foot of input terminal, 11 foot of output terminal of the NAND gate U7A passes through 1 foot of input terminal of resistance R35 connection NAND gates U7D, institute
10 foot of output terminal of 2 foot of the input terminal connection NAND gate U7B of NAND gate U7D is stated, 3 foot of output terminal of the NAND gate U7D passes through
Resistance R43 connections electric discharge MOS (M1~M3) grid, the electric discharge MOS (M1~M3) connect resistance R29 between grid and source electrode；
The overdischarge additives for overcharge protection circuit (4) includes chip U1, and the chip U1 is S-8261ABMMD-G3M-T2S, institute
1 foot for stating chip U1 passes through the base stage of resistance RD1 connection PNP triodes Q1, the collector connection NPN of the PNP triode Q1
Triode Q13 base stages, 3 collector of NPN triode Q1 connects 13 foot of input terminal of NAND gate U7A by resistance R34, described
11 foot of output terminal of NAND gate U7A passes through 1 foot of input terminal of resistance R35 connection NAND gates U7D, the input of the NAND gate U7D
10 foot of output terminal of 2 feet connection NAND gate U7B is held, 3 foot of output terminal of the NAND gate U7D passes through resistance R43 connections electric discharge MOS
(M1~M3) grid, the electric discharge MOS (M1~M3) connect resistance R29 between grid and source electrode；3 feet of the chip U1 pass through
The base stage of resistance RC1 connection PNP triodes Q2, the collector of the PNP triode Q2 pass through resistance R16, diode D1 connections
7 base stage of NPN triode Q1, the collector of the NPN triode Q1 7 connect the grid of charging MOS (M4~M6) with emitter respectively
Pole and source electrode；
The auto sleep and timing 24 hours and external voltage wake-up circuit (5) include microcontroller U8, the microcontroller U8 is
Microcontroller is EM78P301-8, and the 2 foot output terminal K2 of the microcontroller U8 pass through the grid of resistance R45 connection metal-oxide-semiconductors Q19, institute
The drain electrode of metal-oxide-semiconductor Q19 is stated by the grid of resistance R48 connection metal-oxide-semiconductors Q20, input terminal 8,9 feet of the NAND gate U7B pass through
Capacitance C15 is sequentially connected resistance R26, R50, R27, power supply VCC, the F1-2 ends connection metal-oxide-semiconductor between described resistance R26, R50
The source electrode of Q20, the drain electrode of the F1-1 ends connection metal-oxide-semiconductor Q20 between described resistance R50, R27；The 6 feet input of the microcontroller U8
Hold K1 connection photoelectrical coupler U10 output terminals, the photoelectrical coupler U10 input terminals connection electric socket J2.
2. a kind of intelligent solar energy storage timing as described in claim 1 automatically wakes up protection board in 24 hours, feature exists
In：The overdischarge additives for overcharge protection circuit (4) is identical be sequentially connected in series 6 groups.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721724931.1U CN207490577U (en) | 2017-12-12 | 2017-12-12 | A kind of intelligent solar energy storage timing automatically wakes up protection board in 24 hours |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721724931.1U CN207490577U (en) | 2017-12-12 | 2017-12-12 | A kind of intelligent solar energy storage timing automatically wakes up protection board in 24 hours |
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| Publication Number | Publication Date |
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| CN207490577U true CN207490577U (en) | 2018-06-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201721724931.1U Expired - Fee Related CN207490577U (en) | 2017-12-12 | 2017-12-12 | A kind of intelligent solar energy storage timing automatically wakes up protection board in 24 hours |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113300432A (en) * | 2021-06-07 | 2021-08-24 | 苏州众鑫凯能源科技有限公司 | Method for detecting charging signal of cathode of battery protection board |
-
2017
- 2017-12-12 CN CN201721724931.1U patent/CN207490577U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113300432A (en) * | 2021-06-07 | 2021-08-24 | 苏州众鑫凯能源科技有限公司 | Method for detecting charging signal of cathode of battery protection board |
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