CN207489847U - The chip-packaging structure of EMI protection - Google Patents
The chip-packaging structure of EMI protection Download PDFInfo
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- CN207489847U CN207489847U CN201721321272.7U CN201721321272U CN207489847U CN 207489847 U CN207489847 U CN 207489847U CN 201721321272 U CN201721321272 U CN 201721321272U CN 207489847 U CN207489847 U CN 207489847U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
The utility model provides a kind of chip-packaging structure of EMI protection, and encapsulating structure includes the first re-wiring layer, has opposite first surface and second surface；First metal coupling is electrically connected to the first surface of the first re-wiring layer；First semiconductor chip is electrically connected to the second surface of the first re-wiring layer；First capsulation material layer is formed in the periphery of the first semiconductor chip；Shielding protection layer is formed in the periphery of the first capsulation material layer, and jointly coats the first semiconductor chip and the first capsulation material layer with the first re-wiring layer, the metallicity particle including organic material layer and in organic material layer.Through the above scheme; using containing the organic material layer of metallicity particle as shielding protection layer; the making of Molding (plastic packaging) technique may be used; closure is good; it is at low cost; it is not required to carry out vacuum sputtering, and different semiconductor chips can be encapsulated simultaneously, improves protection effect and packaging efficiency.
Description
Technical field
The utility model belongs to technical field of semiconductor encapsulation, more particularly to a kind of chip-packaging structure of EMI protection.
Background technology
As the function of integrated circuit is increasingly stronger, performance and integrated level is higher and higher and novel integrated circuit goes out
Existing, encapsulation technology plays an increasingly important role in IC products, shared in the value of entire electronic system
Ratio it is increasing.Meanwhile as integrated circuit feature size reaches nanoscale, transistor to more high density, it is higher when
Clock frequency develops, and encapsulation also develops to more highdensity direction.
Since fan-out wafer grade encapsulates (Fan-Out Wafer Level Package, FOWLP) technology due to small-sized
Change, low cost and the advantages that high integration and with better performance and higher energy efficiency, the encapsulation of fan-out wafer grade
(FOWLP) technology has become the important packaging method of the electronic equipments such as movement/wireless network of high request, is most to send out at present
One of encapsulation technology of exhibition prospect.
However, the portability of command, control, communications, and information terminal, digitlization, make the EMI/RFI of system inhibit problem more prominent, it must
Operation of the semiconductor chip (also will be called " semiconductor wafer ") for including integrated circuit from integrated circuit can be influenced must be protected
Electromagnetic wave influence.In addition, while semiconductor chip operates, integrated circuit can generate electromagnetic wave, and the electromagnetic wave also may be used
It can influence human body, that is, the electromagnetic wave generated from the integrated circuit of semiconductor chip may influence other semiconductor chips, Qi Ta electricity
Subsystem or human body, so as to cause other semiconductor chips or other electronic systems failure or lead to ill.Cause
This, it may be necessary to shielding semiconductor chip (or electronic system) so that the electricity generated from semiconductor chip (or electronic system)
Magnetic wave or high-frequency noise are not propagated outward.
Therefore it provides the chip-packaging structure and packaging method of a kind of EMI/RFI protection of good performance are current to solve
The problems such as effective EMI/RFI protection or complicated and of high cost protection packaging technology cannot be carried out to device, is necessary.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of EMI/RFI protection
Chip-packaging structure, for solving that in the prior art device cannot be carried out effective EMI/RFI protection or protection packaging technology
The problem of waiting complicated and of high cost.
In order to achieve the above objects and other related objects, the utility model provides a kind of chip-packaging structure of EMI protection,
The encapsulating structure includes：
First re-wiring layer has opposite first surface and second surface；
First metal coupling is electrically connected to the first surface of first re-wiring layer；
First semiconductor chip is electrically connected to the second surface of first re-wiring layer, and first semiconductor
The front of chip is in contact with the second surface of first re-wiring layer；
First capsulation material layer is formed in the periphery of first semiconductor chip；And
Shielding protection layer is formed in the periphery of the first capsulation material layer, and the shielding protection layer and described first
Re-wiring layer jointly coats first semiconductor chip and the first capsulation material layer, wherein, the shielding is anti-
Sheath includes organic material layer and the metallicity particle in the organic material layer.
As a kind of preferred embodiment of the utility model, the encapsulating structure further includes several electrical connectors and the second half
Conductor chip, second semiconductor chip are electrically connected, and described via the electrical connector with first re-wiring layer
Second semiconductor chip is located in the space that the shielding protection layer and first re-wiring layer surround and with described first
Semiconductor chip mutually insulate.
As a kind of preferred embodiment of the utility model, second semiconductor chip and the first semiconductor core on piece
Under be correspondingly arranged, and second semiconductor chip is electrically connected by the second re-wiring layer and the second metal coupling with described
One end of part is electrically connected, and the other end of the electrical connector is electrically connected with first re-wiring layer, by described second
Semiconductor chip is electrically drawn.
As a kind of preferred embodiment of the utility model, the encapsulating structure further includes one layer of buffer layer and one layer of insulation
Layer, the buffer layer is located at surface of first semiconductor chip far from the first re-wiring layer side, and extends and cover
Cover the first capsulation material layer around first semiconductor chip, the insulating layer is located at the buffer layer and described the
Between two re-wiring layers.
As a kind of preferred embodiment of the utility model, the periphery of second semiconductor chip is formed with the second plastic packaging material
The bed of material.
As a kind of preferred embodiment of the utility model, the back side of first semiconductor chip is formed with one layer of bonding die
Film.
As a kind of preferred embodiment of the utility model, the back side of first semiconductor chip is formed with one layer of buffering
Layer, and the buffer layer extends over the first capsulation material layer around first semiconductor chip.
As a kind of preferred embodiment of the utility model, first re-wiring layer include patterned dielectric layer and
Patterned metal wiring layer；First metal coupling include copper post, positioned at the copper post upper surface metal barrier with
And the solder bump on the metal barrier.
As a kind of preferred embodiment of the utility model, the organic material layer in the shielding material layer includes epoxy
Resin；The metallicity particle in the shielding material layer includes magnetic bead；The material of the first capsulation material layer is selected from poly-
Any one in acid imide, silica gel and epoxy resin.
The utility model also provides a kind of chip packaging method of EMI protection, includes the following steps：
1) carrier is provided；
2) the first semiconductor chip is engaged in the upper surface of the carrier, and the back side of first semiconductor chip with
The upper surface of the carrier is in contact；
3) first semiconductor chip is encapsulated using encapsulating material, to form the first capsulation material layer；
4) the first re-wiring layer is made in the upper surface of the first capsulation material layer, and in first rewiring
The first metal coupling is made on layer, electrically to draw first semiconductor chip；
5) carrier is removed, and be engaged in the structure after the carrier is removed on an adhesive layer, and with described the
The side of one metal coupling is in contact with the upper surface of the adhesive layer；And
6) shielding protection layer is formed in the first capsulation material layer periphery, the shielding protection layer and described first is again
Wiring layer jointly coats first semiconductor chip and the first capsulation material layer, wherein, the shielding protection layer
Metallicity particle including organic material layer and in the organic material layer.
As a kind of preferred embodiment of the utility model, step 1) further includes step：One is formed in the carrier upper surface
Layer peeling layer.
As a kind of preferred embodiment of the utility model, step 1) further includes step：One is formed in the carrier upper surface
Layer buffer layer.
As a kind of preferred embodiment of the utility model, in step 2), by bonding die film by first semiconductor chip
Adhere on the upper surface of the carrier.
As a kind of preferred embodiment of the utility model, in step 3), first semiconductor is encapsulated using encapsulating material
The method of chip includes any one in compression forming, Transfer molding, fluid-tight molding, vacuum lamination and spin coating；Institute
It states encapsulating material and includes any one in polyimides, silica gel and epoxy resin.
As a kind of preferred embodiment of the utility model, in step 6), the method for forming the shielding protection layer includes pressure
Shorten any one in type, Transfer molding, fluid-tight molding, vacuum lamination and spin coating into.
As a kind of preferred embodiment of the utility model,
Step 2) further includes：Make several electrical connectors in the upper surface of the carrier, the electrical connector have with
The first end and the second end opposite with the first end that the carrier is in contact, and the electrical connector and described the first half
There is spacing between conductor chip；
In step 4), first re-wiring layer is in contact with the second end of the electrical connector, the electrical connector
It is electrically connected by first re-wiring layer with first metal coupling；
Step is further included between step 5) and step 6)：
A) one second semiconductor chip is provided, and the second re-wiring layer and the second capsulation material layer are jointly by described second
Semiconductor chip coats, and second semiconductor chip is by second re-wiring layer and positioned at the described second cloth again
The second metal coupling on line layer is connected with the second end of the electrical connector；
In step 6), the shielding protection layer is also formed into the periphery of the second capsulation material layer, the shielding protection
Layer and first re-wiring layer jointly by first semiconductor chip, second semiconductor chip, described be electrically connected
Part, second metal coupling, the first capsulation material layer and the second capsulation material layer cladding.
As a kind of preferred embodiment of the utility model, step 1) is further included forms one layer of buffering in the carrier upper surface
The step of layer, and further include step after step 5)：After structure after removal carrier is engaged on the adhesive layer, in described
Opening is formed on buffer layer, to expose the second end of the electrical connector.
As a kind of preferred embodiment of the utility model, the second re-wiring layer described in step a) is led with described the first half
Between the back side of body chip there is spacing, step is further included in step 6)：In forming a layer insulating in the spacing.
As described above, the chip-packaging structure of the EMI protection of the utility model, has the advantages that：
1) chip package of the EMI protection of the utility model uses the organic material layer for containing metallicity particle as shielding
Protective layer, and chip multilayer magnetic bead may be used in metallicity particle, can effectively inhibit computer, automotive electronics, facsimile machine, number
The electromagnetism or radio frequency interference in the fields such as formula mobile communication；
2) Molding may be used in the forming method of shielding protection layer in the chip package of the EMI protection of the utility model
(plastic packaging) technique makes, and closure is more preferable, and simple process and low cost, does not need to carry out vacuum sputter (sputtering) processing procedure；
3) the fan-out package structure of the utility model can be packaged with the semiconductor chip of different function simultaneously, and rationally
Design different chips and its layout between shielding protection layer, it is cost-effective and improve whole protection effect and encapsulation effect
Rate.
Description of the drawings
Fig. 1 is shown as providing the structure diagram of carrier in the chip packaging method of the EMI protection of the utility model.
Fig. 2 is shown as being formed the structure diagram of peeling layer in the chip packaging method of the EMI protection of the utility model.
Fig. 3 is shown as being formed the structure diagram of buffer layer in the chip packaging method of the EMI protection of the utility model.
Fig. 4 is shown as in the chip packaging method of the EMI protection of the utility model on the first semiconductor core chip bonding carrier
Schematic diagram.
Fig. 5 is shown as being formed the structure diagram of bonding die film in the chip packaging method of the EMI protection of the utility model.
Fig. 6 is shown as being formed the structure of the first capsulation material layer in the chip packaging method of the EMI protection of the utility model
Schematic diagram.
Fig. 7 is shown as forming the first re-wiring layer and first in the chip packaging method of the EMI protection of the utility model
The structure diagram of metal coupling.
Fig. 8 is shown as structure after carrier will be removed in the chip packaging method of the EMI protection of the utility model and engages adhesive layer
Schematic diagram.
Fig. 9 is shown as being formed the structural representation of shielding protection layer in the chip packaging method of the EMI protection of the utility model
Figure.
Figure 10 is shown as a kind of encapsulating structure obtained in the chip packaging method of the EMI protection of the utility model signal
Figure.
Figure 11 is shown as being formed the structural representation of electrical connector in the chip packaging method of the EMI protection of the utility model
Figure.
Figure 12 is shown as being formed electrical connector in the chip packaging method of the EMI protection of the utility model and the first half leads
Structure diagram after body chip.
Figure 13 be shown as being formed in the chip packaging method of the EMI protection of the utility model first to be encapsulated in material layer same
When covering electrical connector and the first semiconductor chip structure diagram.
Figure 14 is shown as the first re-wiring layer in the chip packaging method of the EMI protection of the utility model and is electrically connected simultaneously
The structure diagram of first semiconductor chip and electrical connector.
Figure 15 is shown as being formed the structure of opening on the buffer layer in the chip packaging method of the EMI protection of the utility model
Schematic diagram.
Figure 16 is shown as providing the structure of the second semiconductor chip in the chip packaging method of the EMI protection of the utility model
Schematic diagram.
Figure 17 is shown as forming shielding protection layer in the chip packaging method of the EMI protection of the utility model encapsulates the simultaneously
The structure diagram of semiconductor chip and the second semiconductor chip.
Another encapsulating structure that Figure 18 is shown as obtaining in the chip packaging method of the EMI protection of the utility model shows
It is intended to.
Component label instructions
201 carriers
202 peeling layers
203 buffer layers
204 first semiconductor chips
2041 metal pads
205 bonding die films
206 first capsulation material layers
207 first re-wiring layers
2071 patterned metal wiring layers
2072 patterned dielectric layers
208 first metal couplings
209 adhesive layers
210 retainer rings
211 shielding protection layers
2111 organic material layers
2112 metallicity particles
212 electrical connectors
213 openings
214 second metal couplings
215 second semiconductor chips
216 second capsulation material layers
217 insulating layers
Specific embodiment
Illustrate the embodiment of the utility model below by way of specific specific example, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints with answering
With carrying out various modifications or alterations under the spirit without departing from the utility model.
It please refers to Fig.1 to Figure 17.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though when only display is with related component in the utility model rather than according to actual implementation in diagram
Component count, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during actual implementation
Become, and its assembly layout form may also be increasingly complex.
The utility model provides a kind of chip packaging method of EMI protection, includes the following steps：
1) carrier is provided；
2) the first semiconductor chip is engaged in the upper surface of the carrier, and the back side of first semiconductor chip with
The upper surface of the carrier is in contact；
3) first semiconductor chip is encapsulated using encapsulating material, to form the first capsulation material layer；
4) the first re-wiring layer is made in the upper surface of the first capsulation material layer, and in first rewiring
The first metal coupling is made on layer, electrically to draw first semiconductor chip；
5) carrier is removed, and be engaged in the structure after the carrier is removed on an adhesive layer, and with described the
The side of one metal coupling is in contact with the upper surface of the adhesive layer；And
6) shielding protection layer is formed in the first capsulation material layer periphery, the shielding protection layer and described first is again
Wiring layer jointly coats first semiconductor chip and the first capsulation material layer, wherein, the shielding protection layer
Metallicity particle including organic material layer and in the organic material layer.
The chip packaging method of the EMI protection of the utility model is described in detail below in conjunction with attached drawing.
As shown in Figures 1 to 3, step 1) is carried out, a carrier 201 is provided；
Specifically, the carrier 201 can be glass carrier, ceramic monolith or wafer etc., do not limit herein.
As an example, step is further included in step 1)：One layer of peeling layer 202 is formed in 201 upper surface of carrier.
As an example, step is further included in step 1)：One layer of buffer layer 203 is formed in 201 upper surface of carrier.
Specifically, when the surface of the carrier 201 is formed with the peeling layer 202, subsequent step 2) in described
Semiconductor chip 204 is engaged in the surface of the peeling layer 202, i.e., described peeling layer 202 is located at first semiconductor core
Between 204 back side of piece and the carrier 201.The peeling layer 202 is used to facilitate the stripping of chip structure.
Similarly, when the surface of the carrier 201 is formed with the buffer layer 203, subsequent step 2) in described first
Semiconductor chip 204 is engaged in the surface of the buffer layer 203.Further, the upper surface elder generation shape in the carrier 201 is further included
Into one layer of peeling layer 202, the step of forming one layer of buffer layer 203 then at the surface of the peeling layer 202, the buffer layer 203
Material include but not limited to PI (polyimides) material, as buffer layer, since release layer (peeling layer) can not
In circuit manufacture procedure above, so need plus one layer PI layer, meanwhile, the buffer layer 203 can be also used for subsequently effectively in electricity
Metal coupling is formed on connector 212, improves the stability that metal coupling is formed.
As shown in Figures 4 and 5, step 2) is carried out, the first semiconductor chip 204 is engaged in the upper surface of the carrier 201,
And the back side of first semiconductor chip 204 is in contact with the upper surface of the carrier 201；
It should be noted that " back side " refers to chip (such as described first semiconductor chip 204) and gold thereon
Belong to the opposite another surface of weld pad 2041, have metal pad 2041 is defined as front on one side, wherein, the semiconductor chip
204 can be any one semiconductor functional chip, front be formed with the metal pad for drawing inside function device electricity
2041, the upper surface of the metal pad 2041 is exposed to the upper surface of the semiconductor chip 204, the metal pad 2041
The upper surface of upper surface and the semiconductor chip 204 can the semiconductor chip 204 can also be protruded from flush
Upper surface.
As an example, in step 2), first semiconductor chip 204 is adhered on by the carrier by bonding die film 205
201 upper surface.
Specifically, the bonding die film 205 can be DAF (die-attach film) or BSL films, it is preferable that the bonding die
Film 205 is the laminated construction for including the first glue-line, high thermal conductive resin layer and the second glue-line, first glue-line, the high heat conduction
Resin layer and second glue-line are sequentially stacked, since first semiconductor chip 204 and the carrier 201 are (or described
Peeling layer 202 or the buffer layer 203) between be provided with bonding die film 205, first semiconductor chip 204 can be enhanced
Adhesion strength between the carrier 201 (either the peeling layer 202 either the buffer layer 203) is being shifted or is being cut
Deng during, first semiconductor chip 204 will not shake, so as to ensure the stability of structure.
As shown in fig. 6, carrying out step 3), first semiconductor chip 204 is encapsulated using encapsulating material, to form first
Capsulation material layer 206；
As an example, in step 3), include being compressed into using the method that encapsulating material encapsulates first semiconductor chip
Any one in type, Transfer molding, fluid-tight molding, vacuum lamination and spin coating；It is sub- that the encapsulating material includes polyamides
Any one in amine, silica gel and epoxy resin.
As an example, the material of the first capsulation material layer 206 is in polyimides, silica gel and epoxy resin
Any one.
Specifically, being formed after the first capsulation material layer 206, further include and its upper surface is planarized, with sudden and violent
Expose the metal pad 2041 of first semiconductor chip 204, the flatening process includes but not limited to chemical machinery and grinds
Mill.
As shown in fig. 7, carrying out step 4), the first rewiring is made in the upper surface of the first capsulation material layer 206
Layer 207, and in making the first metal coupling 208 on first re-wiring layer 207, electrically to draw first semiconductor
Chip 204；
As an example, first re-wiring layer 207 includes patterned dielectric layer 2072 and patterned metal
Wiring layer 2071；First metal coupling 208 include copper post, positioned at the copper post upper surface metal barrier and be located at
Solder bump on the metal barrier.
Specifically, in step 4), make first re-wiring layer 207 and include step：
4-1) there is first semiconductor chip in exposing using chemical vapor deposition method or physical gas-phase deposition
Dielectric layer is formed in 204 positive one sides, and the dielectric layer is performed etching, to form patterned dielectric layer 2072；
4-2) using chemical vapor deposition method, evaporation process, sputtering technology, electroplating technology or chemical plating process in described
Patterned dielectric layer surface forms metal layer, and the metal layer is performed etching, to form patterned metal wiring layer
2072。
Further, the material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorus silicon glass
The combination of one or more of glass, fluorine-containing glass, the material of the metal wiring layer are included in copper, aluminium, nickel, gold, silver, titanium
One or more kinds of combinations.In the present embodiment, the dielectric layer is selected as polyimides (PI), the metal wiring layer
Material selection be copper.
It should be noted that the re-wiring layer 207 can include the multiple dielectric layers stacked gradually and multiple gold
Belong to wiring layer, according to line demand, each layer metal wiring layer is realized by each dielectric layer being patterned or being made through-hole
Between interconnection, to realize the line demand of different function.
Specifically, in step 4), make first metal coupling 208 and include step：
A) using galvanoplastic copper post is formed in 207 surface of the first re-wiring layer；
B) using galvanoplastic metal barrier is formed in the copper post surface；And
C) solder metal is formed, and using high temperature reflow processes in described in the metal barrier layer surface using galvanoplastic
Metal barrier layer surface forms solder bump.
Further, the metal barrier includes nickel layer, and the material of the solder bump includes one in lead, tin and silver
Kind or the alloy for including any one above-mentioned solder metal.The copper post of high quality can be prepared using galvanoplastic, improves metal
The quality of convex block 208, the metal barrier can stop the diffusion of solder metal, improve the electrical property of metal coupling 208.
As shown in figure 8, carrying out step 5), the carrier 201 is removed, and be engaged in one by the structure after the carrier is removed
On adhesive layer 209, and the side with first metal coupling 208 is in contact with the upper surface of the adhesive layer 209；
As an example, further including step in step 5), a retainer ring 210 is provided, the adhesive layer 209 is fixed on described
In retainer ring 210.
Specifically, the adhesive layer 209 includes one kind in adhesive tape and gummy polymer layers.The sticky polymer object
Can be heat-curable glue or uv-curable glue.In the present embodiment, the adhesive layer 209 is selected as one-sided sticking sticky glue
Band.
In addition, the material of the retainer ring 210 includes one kind in glass, metal, semiconductor, polymer and ceramics.
In the present embodiment, the material of the retainer ring 210 is glass, using glass as retainer ring 210, in the follow-up and adhesive layer
During 209 separation, it is easier to remove, improves the efficiency and stability of separation.
The shape of the retainer ring 210 can be round, rectangle or the shape needed for other.The adhesive layer 209 can
Think biadhesive or one-sided sticking adhesive layer, in the present embodiment, the adhesive layer 209 is one-sided sticking adhesive layer,
Have it is sticking be adhesively fixed on one side in the retainer ring 210, the adhesive layer 210 is fixed, prevents its warpage etc. existing
The generation of elephant improves stability.
As shown in Fig. 9~10, step 6) is carried out, shielding protection layer is formed in 206 periphery of the first capsulation material layer
211, the shielding protection layer 211 is with first re-wiring layer 207 jointly by first semiconductor chip 204 and institute
The first capsulation material layer 206 is stated to coat, wherein, the shielding protection layer 211 includes organic material layer 2111 and positioned at described
Metallicity particle 2112 in organic material layer 2111.
As an example, the organic material layer 2111 in the shielding material layer 211 includes epoxy resin；The shielding
The metallicity particle 2112 in material layer 211 includes magnetic bead.
As an example, in step 6), the method that forms the shielding protection layer 211 include compression forming, transfer modling into
Any one in type, fluid-tight molding, vacuum lamination and spin coating.
It should be noted that the shielding protection layer 211 is as one layer of electromagnetism or the protective layer of radio frequency interference, it is preferable that
The shielding protection layer is not in direct contact with the semiconductor chip, wherein, the metallicity particle 2112 can be existing
The arbitrary particle with metalline, the effect with shielding, such as arbitrary metallic of the prior art, such as iron, copper,
Preferably nanogold attribute particle, it is of course also possible to have other particles of metallicity, it such as can be with selected as magnetic bead, into one
Step, can effectively inhibit computer, automotive electronics, biography with selected as multilayer sheet type magnetic bead using chip multilayer magnetic bead (MLCB)
The electromagnetism in fields or the radio frequency interferences (EMI/RFI) such as prototype, digital mobile communication, and with small size, highly reliable magnetic cup
The characteristics of covering, being assembled suitable for high-density circuit board, mainboard, bus, clock line, sound card, video card, network interface card in laptop and
Whether power unit, the plurality of specifications chip magnetic bead being required for including low speed, high speed, high current type, chip magnetic bead can
Think ferrite bean.In addition, the organic material layer 2111 can be arbitrary organic material layer of the prior art, it can be with
Metallicity particle is coated, the shielding protection layer is collectively formed, in the present embodiment, the organic material layer selected as epoxy
Resin (epoxy).
Specifically, the organic material of liquid can be mixed with metallicity particle, then by molding (plastic packaging) be made by
Its plastic packaging shields semiconductor chip packaging in the position for needing shielding protection of the application, it is preferable that in the present embodiment,
It is the existing liquid mixing material made to select material quotient, its plastic packaging then is formed the shielding protection material using plastic package process
The bed of material 211.So as to using arbitrary plastic package process, such as compression forming, Transfer molding, fluid-tight molding, vacuum lamination and rotation
Any one in painting, it may not be necessary to vacuum sputter processing procedures, so as to greatly cost-effective, simplify technique, meanwhile,
EMI protection closure after it is encapsulated is more preferable.
As shown in Figure 11~18, as an example, packaging method provided by the utility model, further include while led the second half
The step of body chip package, it is of course also possible to for multiple other semiconductor chips, depending on actual demand, specially：
As shown in figure 11, step 2) further includes：Several electrical connectors 212 are made in the upper surface of the carrier, it is described
Electrical connector 212 has the first end 2121 being in contact with the carrier 201 and the second end opposite with the first end
2122, and there is spacing between the electrical connector 212 and first semiconductor chip 204；
In step 4), first re-wiring layer 207 is in contact with the second end 2122 of the electrical connector 212, institute
Electrical connector 212 is stated to be electrically connected with first metal coupling 208 by first re-wiring layer 207；
Step is further included between step 5) and step 6)：
A) one second semiconductor chip 215, and the second re-wiring layer (not shown) and the second capsulation material are provided
Layer 216 jointly coats second semiconductor chip 215, and second semiconductor chip 215 passes through the described second cloth again
2122 phase of second end of line layer and the second metal coupling 214 and the electrical connector on second re-wiring layer
Connection；
In step 6), the shielding protection layer 211 is also formed into the periphery of the second capsulation material layer 216, the screen
Protective layer 211 is covered with first re-wiring layer 207 jointly by first semiconductor chip 204, second semiconductor
Chip 215, the electrical connector 212, second metal coupling 214, the first capsulation material layer 206 and described second
Capsulation material layer 216 coats.
Specifically, it in the present embodiment, also achieves the semiconductor chip packaging of at least two different function together
Encapsulation, wherein, the topology layout between the function of chip, quantity and different chips can be set according to actual demand,
In this exemplary encapsulating structure, second semiconductor chip 215 and first semiconductor chip 204 can finally lead to
It crosses first re-wiring layer 207 and realizes electrical extraction, not only reached effective EMI protection encapsulation, but also can be with saving components
Space is achieved different chip effects, is a kind of novel encapsulating structure.
Specifically, the electrical connector 212 can be the structure of the realizations such as copper post electrical connection, it is preferable that the electrical connection
Part 212 is formed in the surface of the carrier 201 prior to first semiconductor chip 204, so as to effective protection chip, prevents
Chip only is destroyed in chip fabrication processes, there is spacing between the electrical connector and first semiconductor chip, it is described
4 are set as depending on the quantity of electrical connector can be according to actual demand, in this example.
As an example, in step 1), further include in 201 upper surface of carrier forms one layer of buffer layer 203 the step of, step
It is rapid 5) to further include step later：After it will remove the structure after the carrier and be engaged on an adhesive layer, in the buffer layer
Opening 213 is formed on 203, to expose the second end of the electrical connector 212.
Specifically, in this example, also in 204 back side of the first semiconductor chip and surrounding first capsulation material layer 206
Surface is formed with one layer of buffer layer 203, and the buffer layer 203 is also covered with the end face of the electrical connector 212, is used for simultaneously
Ensure the realization of circuit manufacture procedure below, when forming the second semiconductor chip, it is also necessary to be opened on the buffer layer 203
Mouthful, the end of electrical connector is exposed, so that second metal coupling 214 can be set to this, consequently facilitating realizing
The electrical connection of second semiconductor chip.
As an example, in step a), between the back side of second re-wiring layer and first semiconductor chip 204
With spacing, in step 6), further include in layer insulating 217 are formed in the spacing the step of.
Specifically, when second semiconductor chip 215 is set, it is preferable that the second semiconductor that will be provided
There is spacing, and when the first semiconductor back surface is formed with the bonding die film 205 between the structure of chip and the first semiconductor chip
Or during buffer layer 203, when second semiconductor surface is formed with the second re-wiring layer, the second re-wiring layer and bonding die
There is spacing, it is preferable that before shielding protection layer 211 is formed, the spacing is filled into full insulation between film or buffer layer
Material forms a layer insulating 217, component failure is prevented, it is further preferred that four peripheral end portion of the insulating layer 217 and institute
The madial wall for stating shielding protection layer is in contact, to reach effective insulation.
As shown in Figure 10 and 18, the utility model also provides a kind of chip-packaging structure of EMI protection, wherein, the EMI
The chip-packaging structure of protection includes but not limited to the obtained structure of packaging method using the utility model, the encapsulation knot
Structure includes：First re-wiring layer 207, the first metal coupling 208, the first semiconductor chip 204, the first capsulation material layer 206
And shielding protection layer 211, wherein：
First re-wiring layer 207 has opposite first surface and second surface；
First metal coupling 208 is electrically connected to the first surface of first re-wiring layer 207；
First semiconductor chip 204 is electrically connected to the second surface of first re-wiring layer 207；
First capsulation material layer 206 is formed in the periphery of first semiconductor chip 204；And
Shielding protection layer 211, is formed in the periphery of the first capsulation material layer 206, and the shielding protection layer 211 with
Shown first re-wiring layer 207 jointly wraps first semiconductor chip 204 and the first capsulation material layer 206
It covers, wherein, the shielding protection layer 211 includes organic material layer 2111 and the metal in the organic material layer 2111
Property particle 2112.As shown in Figure 10.
As an example, the organic material layer 2111 in the shielding material layer 211 includes epoxy resin；The shielding
The metallicity particle 2112 in material layer 211 includes magnetic bead；It is sub- that the material of the first capsulation material layer 206 is selected from polyamides
Any one in amine, silica gel and epoxy resin.
It should be noted that the shielding protection layer 211 is as one layer of electromagnetism or the protective layer of radio frequency interference, it is preferable that
The shielding protection layer is not in direct contact with the semiconductor chip, wherein, the metallicity particle 2112 can be existing
The arbitrary particle with metalline, the effect with shielding, such as arbitrary metallic of the prior art, such as iron, copper,
Preferably nanogold attribute particle, it is of course also possible to have other particles of metallicity, it such as can be with selected as magnetic bead, into one
Step, can with selected as multilayer sheet type magnetic bead, using chip multilayer magnetic bead (MLCB) can effectively inhibit as computer, automotive electronics,
The electromagnetism or radio frequency interference in the fields such as facsimile machine and digital mobile communication, and there is small size, highly reliable magnetic screen, fit
In high-density circuit board assembles the characteristics of, mainboard, bus, clock line, sound card, video card, network interface card and power supply in laptop
Part, the plurality of specifications chip magnetic bead being required for including low speed, high speed, high current type, chip magnetic bead are to be
Ferrite bean.In addition, the organic material layer 2111 can be arbitrary organic material layer of the prior art, it can will be golden
Attribute particle coats, and the shielding protection layer is collectively formed, in the present embodiment, the organic material layer selected as epoxy resin
(epoxy)。
As an example, as shown in figure 18, the encapsulating structure further includes several 212 and second semiconductor cores of electrical connector
Piece 215, second semiconductor chip 215 are electrically connected via the electrical connector 212 with first re-wiring layer 207,
And second semiconductor chip 215 is located at the space that the shielding protection layer 211 is surrounded with first re-wiring layer 207
It is interior and with 204 phase of the first semiconductor chip insulate.
As an example, the periphery of second semiconductor chip 215 is formed with the second capsulation material layer 216.
As an example, second semiconductor chip 215 is correspondingly arranged with first semiconductor chip about 204, and
Second semiconductor chip 215 passes through the second re-wiring layer and the second metal coupling 214 and the electrical connector 212
One end is connected, and the other end of the electrical connector 212 is connected with first re-wiring layer 207, by described second
Semiconductor chip 215 is electrically drawn.
As an example, the encapsulating structure further includes one layer of 203 and one layer insulating 217 of buffer layer, the buffer layer
203 are located at surface of first semiconductor chip 204 far from 207 side of the first re-wiring layer, and extend over institute
State the first capsulation material layer 206 around the first semiconductor chip, the insulating layer 217 be located at the buffer layer 203 with
Between second re-wiring layer.
Specifically, it in the present embodiment, also achieves the semiconductor chip packaging of at least two different function together
Encapsulation, wherein, the topology layout between the function of chip, quantity and different chips can be set according to actual demand,
In this exemplary encapsulating structure, second semiconductor chip 215 and first semiconductor chip 204 can finally lead to
It crosses first re-wiring layer 207 and realizes electrical extraction, not only reached effective EMI protection encapsulation, but also can be with saving components
Space is achieved different chip effects, is a kind of novel encapsulating structure.
Specifically, the material of the buffer layer 203 includes but not limited to PI (polyimides) material, buffer layer is used as,
Due to release layer (peeling layer) can not in circuit manufacture procedure above, so need plus one layer PI layers, meanwhile, the buffering
Layer 203 can be also used for subsequently effectively forming metal coupling on electrical connector 212, improve the stabilization that metal coupling is formed
Property.In addition, the insulating layer 217 can prevent component failure, it is further preferred that four peripheral end portion of the insulating layer 217 with
The madial wall of the shielding protection layer is in contact, to reach effective insulation.
As an example, surface of first semiconductor chip 204 far from 207 side of the first re-wiring layer is formed
There is one layer of bonding die film 205.
As an example, surface of first semiconductor chip 204 far from 207 side of the first re-wiring layer is formed
There is one layer of buffer layer 203, and the buffer layer 203 extends over first modeling around first semiconductor chip 204
Closure material layer 206.
As an example, first re-wiring layer 207 includes patterned dielectric layer 2071 and patterned metal
Wiring layer 2072；First metal coupling 208 include copper post, positioned at the copper post upper surface metal barrier and be located at
Solder bump on the metal barrier.
Specifically, the bonding die film 205 can be DAF (die-attach film) or BSL films, it is preferable that the bonding die
Film 205 is the laminated construction for including the first glue-line, high thermal conductive resin layer and the second glue-line, first glue-line, the high heat conduction
Resin layer and second glue-line are sequentially stacked, since first semiconductor chip 204 and the carrier 201 are (or described
Peeling layer 202 or the buffer layer 203) between be provided with bonding die film 205, first semiconductor chip 204 can be enhanced
Adhesion strength between the carrier 201 (either the peeling layer 202 either the buffer layer 203) is being shifted or is being cut
Deng during, first semiconductor chip 204 will not shake, so as to ensure the stability of structure.
In addition, the material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, contain
The combination of one or more of fluorine glass, the material of the metal wiring layer include one in copper, aluminium, nickel, gold, silver, titanium
Kind or two or more combinations.The metal barrier includes nickel layer, and the material of the solder bump includes one in lead, tin and silver
Kind or the alloy for including any one above-mentioned solder metal.
In conclusion the utility model provides a kind of chip-packaging structure of EMI protection, encapsulating structure includes first again
Wiring layer has opposite first surface and second surface；First metal coupling is electrically connected to first re-wiring layer
First surface；First semiconductor chip is electrically connected to the second surface of first re-wiring layer；First capsulation material layer,
It is formed in the periphery of first semiconductor chip；And shielding protection layer, the periphery of the first capsulation material layer is formed in,
And the shielding protection layer and shown first re-wiring layer are jointly by first semiconductor chip and first plastic packaging
Material layer coats, wherein, the shielding protection layer includes organic material layer and the metallicity in the organic material layer
Particle.Through the above scheme, the chip package of the EMI protection of the utility model uses the organic material layer containing metallicity particle
As shielding protection layer, and chip multilayer magnetic bead may be used in metallicity particle, can effectively inhibit computer, automotive electronics, biography
The electromagnetism or radio frequency interference in the fields such as prototype, digital mobile communication；It is shielded in the chip package of the EMI protection of the utility model
The making of Molding (plastic packaging) technique may be used in the forming method of protective layer, and closure is more preferable, and simple process and low cost, no
It needs to carry out vacuum sputter (sputtering) processing procedure；The fan-out package structure of the utility model can be packaged with different work(simultaneously
Can semiconductor chip, and rationally design different chips and its layout between shielding protection layer, it is cost-effective and improve
Whole protection effect and packaging efficiency.So the utility model effectively overcomes various shortcoming of the prior art and has height
Spend industrial utilization.
The above embodiments are only illustrative of the principle and efficacy of the utility model, new not for this practicality is limited
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications completed under refreshing and technological thought or change, should be covered by the claim of the utility model.
Claims (9)
1. a kind of chip-packaging structure of EMI protection, which is characterized in that the encapsulating structure includes：
First re-wiring layer has opposite first surface and second surface；
First metal coupling is electrically connected to the first surface of first re-wiring layer；
First semiconductor chip is electrically connected to the second surface of first re-wiring layer, and first semiconductor chip
Front be in contact with the second surface of first re-wiring layer；
First capsulation material layer is formed in the periphery of first semiconductor chip；And
Shielding protection layer is formed in the periphery of the first capsulation material layer, and the shielding protection layer and described first is again
Wiring layer jointly coats first semiconductor chip and the first capsulation material layer, wherein, the shielding protection layer
Metallicity particle including organic material layer and in the organic material layer.
2. the chip-packaging structure of EMI protection according to claim 1, which is characterized in that the encapsulating structure further includes
Several electrical connectors and the second semiconductor chip, second semiconductor chip is via the electrical connector and first weight
New route layer is electrically connected, and second semiconductor chip is located at the shielding protection layer and is surrounded with first re-wiring layer
Space in and mutually insulate with first semiconductor chip.
3. the chip-packaging structure of EMI protection according to claim 2, which is characterized in that second semiconductor chip
It is correspondingly arranged up and down, and second semiconductor chip passes through the second re-wiring layer and the with first semiconductor chip
One end of two metal couplings and the electrical connector is electrically connected, the other end of the electrical connector and first rewiring
Layer electrical connection, second semiconductor chip is electrically drawn.
4. the chip-packaging structure of EMI protection according to claim 3, which is characterized in that the encapsulating structure further includes
One layer of buffer layer and a layer insulating, the buffer layer are located at first semiconductor chip far from first rewiring
The surface of layer side, and extend over the first capsulation material layer around first semiconductor chip, the insulating layer
Between the buffer layer and second re-wiring layer.
5. the chip-packaging structure of EMI protection according to claim 2, which is characterized in that second semiconductor chip
Periphery be formed with the second capsulation material layer.
6. the chip-packaging structure of EMI protection according to claim 1, which is characterized in that first semiconductor chip
The back side be formed with one layer of bonding die film.
7. the chip-packaging structure of EMI protection according to claim 1, which is characterized in that first semiconductor chip
The back side be formed with one layer of buffer layer, and the buffer layer extends over first modeling around first semiconductor chip
Closure material layer.
8. the chip-packaging structure of EMI protection according to claim 1, which is characterized in that first re-wiring layer
Including patterned dielectric layer and patterned metal wiring layer；First metal coupling includes copper post, positioned at the copper
The metal barrier of column upper surface and the solder bump on the metal barrier.
9. according to the chip-packaging structure of EMI protection according to any one of claims 1 to 8, which is characterized in that the shielding
The organic material layer in protective layer includes epoxy resin；The metallicity particle in the shielding protection layer includes magnetic
Pearl；Any one of the material of the first capsulation material layer in polyimides, silica gel and epoxy resin.
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| CN201721321272.7U CN207489847U (en) | 2017-10-13 | 2017-10-13 | The chip-packaging structure of EMI protection |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107680912A (en) * | 2017-10-13 | 2018-02-09 | 中芯长电半导体（江阴）有限公司 | The chip-packaging structure and method for packing of EMI protection |
| CN110752189A (en) * | 2019-10-23 | 2020-02-04 | 杭州见闻录科技有限公司 | EMI shielding material, EMI shielding process and communication module product |
| CN111883437A (en) * | 2020-07-03 | 2020-11-03 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
| CN112435970A (en) * | 2020-09-30 | 2021-03-02 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
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- 2017-10-13 CN CN201721321272.7U patent/CN207489847U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107680912A (en) * | 2017-10-13 | 2018-02-09 | 中芯长电半导体（江阴）有限公司 | The chip-packaging structure and method for packing of EMI protection |
| CN110752189A (en) * | 2019-10-23 | 2020-02-04 | 杭州见闻录科技有限公司 | EMI shielding material, EMI shielding process and communication module product |
| US11770920B2 (en) | 2019-10-23 | 2023-09-26 | Huzhou Jianwenlu Technology Co., Ltd. | EMI shielding material, EMI shielding process, and communication module product |
| CN111883437A (en) * | 2020-07-03 | 2020-11-03 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
| CN112435970A (en) * | 2020-09-30 | 2021-03-02 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
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