CN207425848U

CN207425848U - Semiconductor package

Info

Publication number: CN207425848U
Application number: CN201721575743.7U
Authority: CN
Inventors: 华良
Original assignee: HANGZHOU YOUWANG TECHNOLOGY Co Ltd
Current assignee: HANGZHOU YOUWANG TECHNOLOGY Co Ltd
Priority date: 2017-11-22
Filing date: 2017-11-22
Publication date: 2018-05-29
Anticipated expiration: 2027-11-22

Abstract

A kind of semiconductor package is disclosed, including：Bottom plate, including chip Ji Dao；Packaging body covers the chip Ji Dao；And multiple pins, the multiple pin includes the first pin being arranged in order from one side and the second pin to N pins, N is the integer more than 2, first pin is connected with the chip Ji Dao, each in second pin to the N pins is included with chip Ji Dao bonding regions be bonded and the exposed region outside the packaging body, and the width of at least one bonding region in second pin to the N pins is more than the width of its exposed region.Said structure improves the power output capacity of semiconductor package, so as to which the fan-out capability of chip in itself is not achieved in the current output capability for solving the problems, such as high power device.

Description

Semiconductor package

Technical field

The utility model is related to field of semiconductor package, relate more specifically to a kind of semiconductor package.

Background technology

In recent years, with the raising of field of power electronics demand, it can realize conversion and control the semiconductor work(of flow of electrical power Rate device is just extensively studied and develops, especially need realize power switch device, such as can control it is high-power and Realize high performance power metal-oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), Power bipolar transistor (Bipolar Junction Transistor, BJT), insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) etc..

Semiconductor power device will carry out the various Power Processing tasks such as frequency conversion, transformation, unsteady flow, power management, it is necessary to have There are processing high voltage, high current ability.

In electric field, two adjacent conductors or a conductor measure most with adjacent motor casing surface along insulating surface Short distance under different service conditions, since the insulating materials around conductor is electrically polarized, causes insulating materials to present charged Phenomenon, the radius of this live zone is creepage distance.

Semiconductor power device encapsulation of the prior art, each lead pin pitch is equal, is arranged even if being misplaced using front and rear foot, Also it is only the creepage distance for improving printed circuit board (PCB) (Printed Circuit Board, PCB) pad, fails resolver The inadequate situation of creepage distance between part pin itself, making product, there are integrity problems.

In addition, the current terminal pin bonding region of power device is smaller, the diameter using aluminum steel is limited, cannot more be used More conductor in parallel bondings, make the current output capability of high power device be typically not capable of the fan-out capability of chip in itself.

Utility model content

In view of this, the purpose of this utility model is to provide a kind of semiconductor package, solves high power device The current output capability the problem of fan-out capability of chip in itself is not achieved.

According to a kind of semiconductor package provided by the utility model, including：Bottom plate, including chip Ji Dao；Packaging body, Cover the chip Ji Dao；And multiple pins, the multiple pin include the first pin being arranged in order from one side and the Two pins are the integer more than 2 to N pins, N, and first pin is connected with the chip Ji Dao, and second pin is extremely Each in the N pins includes and the chip Ji Dao bonding regions being bonded and the exposure outside the packaging body Area, the width of at least one bonding region in second pin to the N pins are more than the width of its exposed region.

Preferably, one of them in second pin to the N pins be current terminal pin, the electric current end pipe The width of the bonding region of foot is more than the width of its exposed region.

Preferably, the chip Ji Dao is equipped with power chip, and the bonding region of the current terminal pin passes through key in parallel Conducting wire is closed with the power chip to be connected.

Preferably, first pin is the power end or high-pressure side of the semiconductor package.

Preferably, the distance between first pin and second pin are more than second pin to the N The distance between adjacent pin in pin.

Preferably, second pin the distance between adjacent pin into the N pins is identical.

Preferably, the distance between first pin and second pin are managed for second pin to the N Twice of the distance between adjacent pin in foot.

Preferably, the multiple pin Heterogeneous Permutation successively.

Preferably, the odd number pin in the multiple pin is located at the first plane, and even number pin is located at and described the The second different plane of one level.

Preferably, the end of the exposed region of the multiple pin is concordant.

Preferably, mounting hole is further included on the bottom plate, the mounting hole is outside the packaging body.

Semiconductor package according to the present utility model, each in second pin to the N pins include Be covered in the packaging body and with the chip Ji Dao bonding regions being bonded and the exposed region outside the packaging body, The width of at least one bonding region in second pin to the N pins is more than the width of its exposed region.Wherein, institute One of them in the second pin to the N pins is stated as current terminal pin, the width of the bonding region of the current terminal pin is big In the width of its exposed region, in addition, the bonding region of the current terminal pin can pass through bonding lead in parallel and chip Ji Dao On power chip be connected.Bonding region of the utility model because increasing semiconductor package current terminal pin, using more leading Line bonding in parallel improves the fan-out capability of power device, so as to which the current output capability for solving high power device is not achieved The problem of chip fan-out capability in itself.

In a preferred embodiment, the distance between first pin and second pin are more than second pin The distance between to adjacent pin in the N pins, first pin for the semiconductor package power end or High-pressure side.By increasing lead pin pitch, and make several pins Heterogeneous Permutation successively, significantly improve power end or high-pressure side and phase Climb piezoelectric voltage between adjacent pin, solve the problems, such as power device because climb it is electric caused by fail.

Description of the drawings

By the description referring to the drawings to the utility model embodiment, above-mentioned and other mesh of the utility model , feature and advantage will be apparent from.

Fig. 1 shows the stereogram of the semiconductor package according to the utility model first embodiment；

Fig. 2 and Fig. 3 shows the front view of the semiconductor package according to the utility model first embodiment；

Fig. 4 shows the front view of the semiconductor package according to the utility model second embodiment.

Specific embodiment

Hereinafter reference will be made to the drawings is more fully described the utility model.In various figures, identical element is using similar Reference numeral represent.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.It in addition, may in figure Some well known parts are not shown.

Many specific details of the utility model, such as the structure of component, material, size, place is described hereinafter Science and engineering skill and technology, to be more clearly understood that the utility model.But just as the skilled person will understand, The utility model can not be realized according to these specific details.

It should be appreciated that when describing the structure of component, it is known as when by a floor, a region positioned at another floor, another area When domain " above " or " top ", can refer to above another layer, another region or its with another layer, it is another Also comprising other layers or region between a region.Also, if by part turnover, this layer, a region will be located at it is another Layer, another region " following " or " lower section ".

Fig. 1 shows the stereogram of the semiconductor package according to the utility model first embodiment, and Fig. 2 and Fig. 3 are shown The front view of the semiconductor package, the semiconductor package 100, including bottom plate 110, multiple pins 120 and encapsulation Body 130.Wherein in the front view of Fig. 2, the cross-section of packaging body 130 is shown, in the front view of Fig. 3, by packaging body 130 whole removals are shown.

Bottom plate 110 is used for the chip to be packaged as substrate-loading, can be the plate of rule, this Outer Bottom Plating 110 also leads to Often also serve as heat sink, the preferable metal material of thermal conductivity can be selected in material, is, for example, copper, to improve the thermal diffusivity of encapsulating structure Energy.Certainly if necessary, insulating layer can also be increased on it.It can include chip base island 111 on bottom plate 110.

The material of packaging body 130 can be resin, ceramics etc., be, for example, that epoxy resin is formed, packaging body 130 is located at bottom plate 110 at least partially, and chip base island 111 is covered.

In the present embodiment, mounting hole 112 is further included on bottom plate 110, bottom plate 110 is generally rectangular plate, and packaging body 130 covers The part surface in bottom plate 110 is covered, chip base island 111 is all covered, and mounting hole 112 is installed outside packaging body 130 Hole 112 is used for the installation of entire semiconductor package 100.

Above-mentioned multiple pins 120 can include the first pin 120a and the second pin 120b that are arranged in order from one side To N pins, N is the integer more than 2.In this application, the arrangement that term " N pins " refers in above-mentioned multiple pins 120 is suitable In sequence, the pin of the opposite side opposite with the first pin 120a.Such as in the present embodiment, the quantity of multiple pins 120 can be with Six, including be arranged in order to the left from right side the first pin 120a, the second pin 120b, three-prong 120c, the 4th Pin 120d, the 5th pin 120e and the 6th pin 120f, wherein the 6th pin 120f, that is, above-mentioned N pins.

Unlike the prior art, in the utility model, the first pin 120a is connected with chip base island 111, and second Each bonding region 121 for including being bonded with chip base island 111 in pin 120b to the 6th pin 120f and exposed to encapsulation Exposed region 122 outside body 130, the width of the bonding region 121 of at least one pin in the second pin 120b to the 6th pin 120f Degree is more than the width of its exposed region 122.

One of them in second pin 120b to the 6th pin 120f could be provided as current terminal pin, the present embodiment In, current terminal pin is, for example, the 4th pin 120d, the width of the bonding region 121 of the 4th pin 120d as current terminal pin More than the width of its exposed region 122, the shape of the bonding region 121 of the 4th pin 120d is, for example, greater area of rectangle.

Chip base island 111 is equipped with power chip 113, in the present embodiment, the 4th pin as current terminal pin The bonding region 121 of 120d is connected by bonding lead 140 in parallel with power chip 113, bonding lead 140 can be copper wire, Aluminum steel, alloy wire etc..

The bonding region 121 of current terminal pin of the utility model because increasing semiconductor package 100, using parallel connection It is connected by bonding lead 140 with power chip 113, improves the power output capacity of semiconductor package 100, so as to solve The problem of fan-out capability of chip in itself is not achieved in the current output capability of high power device of having determined.

Packaging body 130 can also cover the bonding region of multiple pins 120 in addition to the chip base island 111 on covering bottom plate 110 121, so that packaging body 130 jointly protects the bonding region 121 on chip base island 111 and multiple pins 120 with bottom plate 110 Shield, ensures the stability being bonded between the bonding region 121 of multiple pins 120 and chip base island 111.

The exposed region 122 of multiple pins 120 can be in that strip extends, and outside above-mentioned packaging body 130, be used for It is attached with other devices or circuit, realizes the actual electrical applications of semiconductor package 100.Preferably, it is above-mentioned multiple The end of the exposed region 122 of pin 120 is concordant.In the present embodiment, the end of the exposed region 122 of multiple pins 120 concordantly refers to more The end of a 120 exposed region of pin is extended at the identical distance in 130 same surface of distance packaged body.

Further in the present embodiment, the distance between the first pin 120a and the second pin 120b can be more than second Pin 120b the distance between adjacent pins into the 6th pin 120f.In the utility model, the spacing between adjacent pin Refer to the wherein one side of one of pin to the distance of the correspondence one side of another pin, be, for example, one of them in adjacent pin The left side of pin is to the distance in the left side of another pin.Wherein, the first pin 120a can be the work(of semiconductor package 100 Rate end pipe foot or high-pressure side pin by increasing the spacing between the first pin 120a and other pins, improve power end pin Or the creepage distance between high-pressure side pin and adjacent pin, when semiconductor package 100 is semiconductor power device, solve Power device fails caused by climbing electric problem.

In above-mentioned multiple pins 120, the distance between the first pin 120a and the second pin 120b be, for example, D1, second Pin 120b can be identical the distance between per adjacent pin into the 6th pin 120f, such as is D2.Preferably, this implementation The distance between the first pin 120a and second pin 120b D1 are adjacent into the 6th pin 120f for the second pin 120b in example Twice of the distance between pin D2.

Multiple pins 120 can Heterogeneous Permutation successively, in the utility model, Heterogeneous Permutation refers to often multiple pins 120 successively The end of adjacent pin is located at Different Plane, and plurality of pin 120 front and rear can be arranged in order, such as in the present embodiment First pin 120a, three-prong 120c, the 5th pin 120e are located at the first plane, the second pin 120b, the 4th pin 120d, 6th pin 120f is located at the second plane with the first plane different height.It these are only the one of multiple 120 Heterogeneous Permutations of pin Kind example, in other embodiments, multiple pins 120 can be arranged according to the plane for being located at more different heights respectively, E.g. the first pin 120a, the 4th pin 120d are located at the first plane, and the second pin 120b, the 5th pin 120e are located at second Plane, three-prong 120c, the 6th pin 120f are located at the 3rd plane, and the first plane, the second plane and the 3rd plane are located at Different height.

It is understood that the quantity of above-mentioned multiple pins 120 can be not limited to include six, also may be used according to actual needs To be other quantity.In addition, putting in order for multiple pins can not also be limited to the arrangement mode of first embodiment.Such as scheming In the front view of the semiconductor package 200 of the second embodiment of replacement shown in 4, equally include bottom plate 210, multiple pins 220 and packaging body 230, chip Ji Dao and mounting hole 212 can be included on bottom plate 210, packaging body 230 covers the chip base Island.The quantity of multiple pins 220 still can be six, however unlike first embodiment, multiple pipes of the present embodiment Foot 220 includes the first pin 220a being arranged in order to the right from left side, the second pin 220b, three-prong 220c, the 4th pipe Foot 220d, the 5th pin 220e and the 6th pin 220f, wherein the 6th pin 220f, that is, above-mentioned N pins.Wherein, first Pin 220a is connected directly with chip Ji Dao, and each in the second pin 220b to the 6th pin 220f includes and chip base island key The bonding region of conjunction and the exposed region outside the packaging body, at least one in the second pin 220b to the 6th pin 220f A pin is, for example, the 4th pin 220d, and the width of bonding region is more than the width of its exposed region, which could be provided as electricity End pipe foot is flowed, is connected with the power chip that chip Ji Dao is equipped with by bonding lead in parallel so that semiconductor package 200 power output capacity improves, and the fan-out capability of chip in itself is not achieved in the current output capability for solving high power device The problem of.The distance between first pin 220a and the second pin 220b can be more than the second pin 220b to the 6th pin 220f In the distance between adjacent pin.Further, in above-mentioned multiple pins 220, the first pin 220a and the second pin 220b The distance between be, for example, D3, the second pin 220b can be identical per the distance between adjacent pin into the 6th pin 220f, Such as it is D4.The distance between the first pin 220a and the second pin 220b D3 are the second pin 220b to the in the present embodiment Twice of the distance between adjacent pin D4 in six pin 220f.Yet further, the first pin 220a can be semiconductor package The power end pin of assembling structure 200 or high-pressure side pin by increasing the spacing between the first pin 220a and other pins, carry Creepage distance between high power end pipe foot or high-pressure side pin and adjacent pin, when semiconductor package 200 is semiconductor work( During rate device, solve the problems, such as power device because climb it is electric caused by fail.

It should be noted that herein, relational terms such as first and second and the like are used merely to a reality Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation In any this actual relation or order.Moreover, term " comprising ", "comprising" or its any other variant are intended to Non-exclusive inclusion, so that process, method, article or equipment including a series of elements not only will including those Element, but also including other elements that are not explicitly listed or further include as this process, method, article or equipment Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that Also there are other identical elements in process, method, article or equipment including the element.

Embodiment according to the utility model as described above, these embodiments there is no all details of detailed descriptionthe, Also it is only the specific embodiment not limit the utility model.Obviously, as described above, many modification and change can be made Change.This specification is chosen and specifically describes these embodiments, and being should in order to preferably explain the principle and reality of the utility model With so that skilled artisan can repairing using the utility model and on the basis of the utility model well Change use.The utility model is limited only by the claims and their full scope and equivalents.

Claims

1. a kind of semiconductor package, which is characterized in that including：

Bottom plate, including chip Ji Dao；

Packaging body covers the chip Ji Dao；And

Multiple pins, the multiple pin include the first pin being arranged in order from one side and the second pin to N pins, N To be more than 2 integer, first pin is connected with the chip Ji Dao, every in second pin to the N pins A bonding region including being bonded with the chip Ji Dao and the exposed region outside the packaging body, second pin is extremely The width of at least one bonding region in the N pins is more than the width of its exposed region.

2. semiconductor package according to claim 1, which is characterized in that second pin to the N pins In one of them for current terminal pin, the width of the bonding region of the current terminal pin is more than the width of its exposed region.

3. semiconductor package according to claim 2, which is characterized in that the chip Ji Dao is equipped with power core Piece, the bonding region of the current terminal pin are connected by bonding lead in parallel with the power chip.

4. semiconductor package according to claim 1, which is characterized in that first pin is the semiconductor package The power end or high-pressure side of assembling structure.

5. semiconductor package according to claim 1, which is characterized in that first pin and second pin The distance between be more than second pin the distance between adjacent pin into the N pins.

6. semiconductor package according to claim 5, which is characterized in that second pin to the N pins In the distance between adjacent pin it is identical.

7. semiconductor package according to claim 6, which is characterized in that first pin and second pin The distance between be second pin into the N pins twice of the distance between adjacent pin.

8. semiconductor package according to claim 1, which is characterized in that the multiple pin Heterogeneous Permutation successively.

9. semiconductor package according to claim 8, which is characterized in that the odd number pin in the multiple pin Positioned at the first plane, even number pin is located at second plane different from first level.

10. semiconductor package according to claim 1, which is characterized in that the end of the exposed region of the multiple pin Portion is concordant.

11. semiconductor package according to claim 1, which is characterized in that mounting hole, institute are further included on the bottom plate Mounting hole is stated outside the packaging body.