CN207368994U - A kind of bilayer spot welded type electrode mask - Google Patents
A kind of bilayer spot welded type electrode mask Download PDFInfo
- Publication number
- CN207368994U CN207368994U CN201721847790.2U CN201721847790U CN207368994U CN 207368994 U CN207368994 U CN 207368994U CN 201721847790 U CN201721847790 U CN 201721847790U CN 207368994 U CN207368994 U CN 207368994U
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- China
- Prior art keywords
- mask plate
- wafer orientation
- slot
- mould
- orientation mould
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- Expired - Fee Related
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Abstract
The utility model discloses a kind of double-deck spot welded type electrode mask, it includes upper mask plate（1）, lower mask plate（2）With wafer orientation mould（3）, the upper mask plate（1）With lower mask plate（2）On offer electrode slot in array distribution（4）, wafer orientation mould（3）On offer chip mounting slot in array distribution（5）, the lower mask plate（2）Outer edge and wafer orientation mould（3）Outer edge it is concordant, lower mask plate（2）Outer edge and wafer orientation mould（3）Between through spot-welded in one, two neighboring chip mounting slot（5）Between be distributed pad（6）.The beneficial effects of the utility model are：The compact-sized, input that improves regulated efficiency, decrease special gauge, the tramp metal avoided the occurrence of bits multilayer cannot be completely superposed phenomenon.
Description
Technical field
Electronic information and quartz crystal component are the utility model is related to, particularly a kind of double-deck spot welded type electrode mask.
Background technology
Traditional electrode mask is made of separated wafer orientation mould, top electrode mask and bottom electrode mask.During work,
First wafer orientation mould, bottom electrode mask must be fixed with special auxiliary fixture, chip is put into wafer orientation mould, manually
Adjust position.Finally, wafer orientation mould, upper/lower electrode mask are manually adjusted to aligning and coinciding completely.
Such layering mask arrangement can have the phenomenon that gap, multilayer cannot be completely superposed with tramp metal bits, layering,
Ultimately result in electrode obscure, misplace, spot, bubble etc. it is bad.Simultaneously as to the high request manually adjusted, as carrier is thrown
Enter the increase of amount, a large amount of special auxiliary fixtures need to be equipped with, and these gauges can take considerable time assembling, adjustment, operation
It is inconvenient, take time and effort it is follow-up can also serious influence production efficiency.
Utility model content
The purpose of the utility model is to overcome the shortcomings that the prior art, there is provided a kind of compact-sized, raising regulated efficiency,
The input for decreasing special gauge, the tramp metal avoided the occurrence of bits multilayer cannot be completely superposed the double-deck spot welded type electricity of phenomenon
Pole mask.
The purpose of this utility model is achieved through the following technical solutions：A kind of bilayer spot welded type electrode mask, it includes
The electricity in array distribution is offered on upper mask plate, lower mask plate and wafer orientation mould, the upper mask plate and lower mask plate
Pole slot, the chip mounting slot in array distribution is offered on wafer orientation mould, and the outer edge of the lower mask plate is determined with chip
The outer edge of position mould is concordant, through spot-welded in one, two neighboring crystalline substance between the outer edge and wafer orientation mould of lower mask plate
It is distributed pad between piece mounting groove, pad is also along the edge distribution of wafer orientation mould, the slot electrode on lower mask plate
Hole is corresponding with chip mounting slot, and the upper mask plate is covered at wafer orientation mould top surface, the edge and chip of upper mask plate
The edge of positioning mould is concordant, and the electrode slot on upper mask plate is connected with chip mounting slot.
The electrode slot rectangular array is uniformly distributed.
The utility model has the following advantages：The utility model is applied in big quantity, high accuracy, continuity plating mould, is kept away
Exempt from the phenomenon that the tramp metal bits, multilayer that traditional approach is likely to occur cannot be completely superposed.Adjustment only needs simple right up and down
Together, 50% or so is improved compared to traditional contraposition regulated efficiency, decreases the input of special gauge.
Brief description of the drawings
Fig. 1 is the structure diagram of the utility model；
Fig. 2 is lower mask plate and the schematic diagram after the covering of wafer orientation mould；
Fig. 3 connects rear schematic diagram for lower mask plate with wafer orientation die welding；
In figure, the upper mask plates of 1-, mask plate under 2-, 3- wafer orientation moulds, 4- electrode slots, 5- chip mounting slots, 6- welderings
Contact.
Embodiment
The utility model is further described below in conjunction with the accompanying drawings, the scope of protection of the utility model be not limited to
It is lower described：
As shown in Fig. 1 ~ 3, a kind of bilayer spot welded type electrode mask, it determines including upper mask plate 1, lower mask plate 2 and chip
Position mould 3, the electrode slot 4 in array distribution is offered on the upper mask plate 1 and lower mask plate 2, and electrode slot 4 is rectangular
Array is uniformly distributed, and the chip mounting slot 5 in array distribution, the outer edge of the lower mask plate 2 are offered on wafer orientation mould 3
It is concordant with the outer edge of wafer orientation mould 3, through spot-welded in one between the outer edge and wafer orientation mould 3 of lower mask plate 2,
Be distributed pad 6 between two neighboring chip mounting slot 5, pad 6 also along wafer orientation mould 3 edge distribution, under cover
Electrode slot 4 in template 2 is corresponding with chip mounting slot 5, and the upper mask plate 1 is covered in 3 top surface of wafer orientation mould, on
The edge of mask plate 1 is concordant with the edge of wafer orientation mould 3, and the electrode slot 4 on upper mask plate 1 connects with chip mounting slot 5
It is logical.
The course of work of the utility model is as follows：Mask plate 1 is removed, then by size and the suitable quartz wafer of thickness
It is put into chip mounting slot 5, covers upper mask plate 1 in 3 top surface of wafer orientation mould after installation is complete, adjusting its position makes
It is concordant with the edge of lower mask plate 2, so as to quickly realize that upper mask plate 1 is overlapped with lower mask plate 2.Due to lower mask plate 2 with
3 seamless welding of wafer orientation mould, while aligning accuracy reaches 0.01mm, ensure that between lower mask plate 2 and wafer orientation mould 3 not
Can tramp metal bits, while by original three layers of adjustment, become in order to which both sides adjust, avoid that multilayer cannot be completely superposed shows
As.In addition, adjustment only needs simply to make mask plate alignment up and down, reduce adjustment process, effect is adjusted compared to traditional contraposition
Rate improves 50% or so, decreases the input of special gauge.
Claims (2)
- A kind of 1. bilayer spot welded type electrode mask, it is characterised in that：It includes upper mask plate（1）, lower mask plate（2）Determine with chip Position mould（3）, the upper mask plate（1）With lower mask plate（2）On offer electrode slot in array distribution（4）, chip is fixed Position mould（3）On offer chip mounting slot in array distribution（5）, the lower mask plate（2）Outer edge and wafer orientation mould （3）Outer edge it is concordant, lower mask plate（2）Outer edge and wafer orientation mould（3）Between through spot-welded in one, adjacent two A chip mounting slot（5）Between be distributed pad（6）, pad（6）Also along wafer orientation mould（3）Edge distribution, under Mask plate（2）On electrode slot（4）With chip mounting slot（5）It is corresponding, the upper mask plate（1）Cover in wafer orientation mould （3）Top surface, upper mask plate（1）Edge and wafer orientation mould（3）Edge it is concordant, and upper mask plate（1）On slot electrode Hole（4）With chip mounting slot（5）Connection.
- A kind of 2. double-deck spot welded type electrode mask according to claim 1, it is characterised in that：The electrode slot（4） Rectangular array is uniformly distributed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721847790.2U CN207368994U (en) | 2017-12-26 | 2017-12-26 | A kind of bilayer spot welded type electrode mask |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721847790.2U CN207368994U (en) | 2017-12-26 | 2017-12-26 | A kind of bilayer spot welded type electrode mask |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207368994U true CN207368994U (en) | 2018-05-15 |
Family
ID=62344200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721847790.2U Expired - Fee Related CN207368994U (en) | 2017-12-26 | 2017-12-26 | A kind of bilayer spot welded type electrode mask |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207368994U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107888157A (en) * | 2017-12-26 | 2018-04-06 | 东晶锐康晶体（成都）有限公司 | A kind of double-deck spot welded type electrode mask |
-
2017
- 2017-12-26 CN CN201721847790.2U patent/CN207368994U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107888157A (en) * | 2017-12-26 | 2018-04-06 | 东晶锐康晶体（成都）有限公司 | A kind of double-deck spot welded type electrode mask |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180515 Termination date: 20191226 |