CN207337649U - A kind of LXI data collectors of high-speed transfer - Google Patents
A kind of LXI data collectors of high-speed transfer Download PDFInfo
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- CN207337649U CN207337649U CN201721397473.5U CN201721397473U CN207337649U CN 207337649 U CN207337649 U CN 207337649U CN 201721397473 U CN201721397473 U CN 201721397473U CN 207337649 U CN207337649 U CN 207337649U
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Abstract
The utility model provides a kind of LXI data collectors of high-speed transfer, solves the problems such as existing LXI collectors transmission speed is slow, service requirement is high, equipment construction cost is high.The utility model includes the first mainboard and the second mainboard；First mainboard includes fpga chip, multi-channel A/D conversion circuits, the first dma controller, the first FIFO memory and the first HSSI High-Speed Serial Interface；Include the processor of the second dma controller, the second FIFO memory, the first HSSI High-Speed Serial Interface, output interface and model Atom E3826 on second mainboard；First HSSI High-Speed Serial Interface is connected by high-speed serial bus with the second HSSI High-Speed Serial Interface；The model MBT 2210 of second mainboard.The utility model is realized to be transmitted in collection, is solved the problems, such as time delay, is significantly improved the performance of collector, improve the transmission speed of collector, simplify user's operation, suitable for promoting the use of.
Description
Technical field
Data acquisition technology field is the utility model is related to, particularly a kind of LXI data collectors of high-speed transfer.
Background technology
In modern industrial production and field of scientific study, the application of data collecting system is more and more extensive, and data are adopted
The main task of collecting system is collection various analog quantity, switching value or data flows, digital quantity is converted thereof into, by computer to adopting
The data of collection are stored, are analyzed, printed, handled, and such as in industrial production and the every profession and trade of scientific and technical research, are usually needed
Various data are acquired, such as the collection of liquid level, temperature, pressure, frequency information.
Existing LXI (in instrument lead by LAN based Extensions for Instrumentation, local area network technology
The extension in domain) collector is divided into two types, and a kind of is the 100000000 net equipment that low speed can be met the requirements, and is chiefly used in supporting scanning
Class or low speed collecting device；Second, high speed class (speed about 40MB/s) collector, needs kilomega network to support, and in the sampling of collector
When speed or parallel channel reache a certain level, it is necessary to increase independent local cache so that the transmission speed of equipment is not
The ability of kilomega network can be farthest played, while add the construction cost of equipment.
Utility model content
In view of the above-mentioned problems of the prior art, the utility model, which provides a kind of transmission speed, can reach 100MB/s, letter
Change user's operation, improve equipment performance, the LXI data collectors of the high-speed transfer of the transmission speed of raising collector.
A kind of LXI data collectors of high-speed transfer, including the first mainboard and the second mainboard for being connected with the first mainboard.
First mainboard includes fpga chip, the first dma controller, the first FIFO memory, multi-channel A/D conversion electricity
Road and the first HSSI High-Speed Serial Interface；First dma controller and the first HSSI High-Speed Serial Interface is connected with fpga chip respectively；
The signal output part of the multi-channel A/D conversion circuits and the signal input part of fpga chip connect；First FIFO is deposited
The data input pin of reservoir and the signal output part of fpga chip connect；The data output end of first FIFO memory with
The input terminal connection of first dma controller；The input of the output terminal and the first HSSI High-Speed Serial Interface of first dma controller
End connection.
Second mainboard includes the second HSSI High-Speed Serial Interface, output interface, the second dma controller, the 2nd FIFO and deposits
The processor of reservoir and model Atom E3826；Output interface, the second dma controller and second HSSI High-Speed Serial Interface
It is connected respectively with processor；The signal output part of second HSSI High-Speed Serial Interface and the signal input part of processor connect；
The data input pin of second FIFO memory and the output terminal of processor connect；The number of second FIFO memory
It is connected according to output terminal with the input terminal of the second dma controller；The output terminal of second dma controller and output interface it is defeated
Enter end connection.
The signal output part of first HSSI High-Speed Serial Interface passes through high-speed serial bus and the second HSSI High-Speed Serial Interface
Signal input part connection.
Preferably, first mainboard further includes the I/O interfaces for being connected and being sequentially connected in series with fpga chip respectively, letter
Number sub-circuit, signal amplification circuit and signal conditioning circuit；The signal output part of the signal conditioning circuit and multi-channel A/D
The signal input part connection of conversion circuit.
Preferably, the first clock circuit and first being connected respectively with fpga chip is further included on first mainboard
Data storage；The second clock circuit being connected respectively with processor and the storage of the second data are further included on second mainboard
Device.
Preferably, the model MBT-2210 of second mainboard.
Preferably, first HSSI High-Speed Serial Interface and the second HSSI High-Speed Serial Interface be PCI-E interface and/or
USB3.0 interfaces.
Preferably, the fpga chip is EP3C40 chips.
Preferably, first dma controller and the second dma controller is more than 1；Each first DMA controls
Device processed has unique corresponding one group of first FIFO memory；Each second dma controller has unique corresponding one group of the 2nd FIFO
Memory.
The method of work of the LXI data collectors of above-mentioned high-speed transfer, comprises the following steps：
1) multichannel original data stream is gathered, multichannel original data stream is converted into more ways of digital signal by analog signal
According to stream, be ranked up by fpga chip and by multiplex data stream, then for every circuit-switched data stream interpolation data label after, will be per road
Data flow and its corresponding data label are stored in the first FIFO memory respectively；
2) the first dma controller read step 1) in data block in the first FIFO memory of deposit, and by the number of reading
Processor is transmitted to according to block；
3) data block obtained in step 2) is stored in the second FIFO memory by processor, is then controlled by the 2nd DMA
Device becomes per circuit-switched data stream and its corresponding data label after being reduced；
4) every circuit-switched data stream by reduction in step 3) is sent to master control PC machine by output interface respectively.
Compared with prior art, the utility model has the advantages that：
1) being used cooperatively by the first mainboard and the second mainboard, using open source hardware platform, improves the stabilization of hardware
Property, the construction cost of hardware is reduced, solving the data of available data collector needs to start to pass after completing to gather
The problem of defeated, realize and transmitted in collection, and solves the problems, such as time delay, meanwhile, parallel control signal pattern is introduced, is realized
Control and data transfer parallel processing, significantly improve the performance of collector；
2) HSSI High-Speed Serial Interface PCI-E interface and/or USB3.0 interfaces and high-speed serial bus are used as data transmission route
Footpath, improves the transmission speed of collector, and power-assisted lifts the overall performance of collector；
3) all parts are used cooperatively in the first mainboard and the second mainboard, solve the data collision of Multi-Channel Parallel Acquisition
Problem, simplifies user's operation, abandons traditional caching form, is realized using FIFO memory and dma controller direct
High speed data transfer so that equipment performance is greatly improved；
4) method of work of collector causes the speed ability of collector to be obviously improved in the utility model, can be preferably
Support the test automation platform of structure a new generation, meet the needs of user is to quickly obtaining test result and to more high sampling rate
Continuous acquisition demand, suitable for promoting the use of.
Brief description of the drawings
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, drawings in the following description are only
It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor
Under, other attached drawings can also be obtained according to these attached drawings.
Fig. 1 is the structure diagram of embodiment.
Fig. 2 is the work flow diagram of embodiment.
Embodiment
The utility model is described in further detail with reference to the accompanying drawings and examples, and the embodiment of the utility model includes
But it is not limited to the following example.
Embodiment
As shown in Figure 1, a kind of LXI data collectors of high-speed transfer, including the first mainboard and it is connected with the first mainboard
Second mainboard.
First mainboard includes fpga chip, the first DMA (Direct Memory Access) controller, the first FIFO
(First In First Out, first in first out) memory, multi-channel A/D conversion circuits and first HSSI High-Speed Serial Interface；First DMA
Controller and the first HSSI High-Speed Serial Interface are connected with fpga chip respectively；The signal output part and FPGA of multi-channel A/D conversion circuits
The signal input part connection of chip；The data input pin of first FIFO memory and the signal output part of fpga chip connect；The
The data output end of one FIFO memory is connected with the input terminal of the first dma controller；The output terminal of first dma controller and
The input terminal connection of one HSSI High-Speed Serial Interface.In the present embodiment, the first mainboard further includes first be connected respectively with fpga chip
Clock circuit and the first data storage；Second mainboard further includes the second clock circuit being connected respectively with processor and the second number
According to memory；Fpga chip is exquisite EP3C40 chips portable, control efficiency is high.
Using the first FIFO memory, i.e., it is a number in the first FIFO memory to improve the efficiency of transmission of data
As soon as being furnished with a buffering area according to stream and its corresponding data label, a buffering area is used exclusively for the memory block of transmission data；
When writing data to the first FIFO memory, system does not transmit data to external equipment directly, but transmits data to
Buffering area forms data block；Buffering area records data automatically, and when buffering area is full, data are continued to be sent to another by system to be delayed
Rush area；When reading data from the first FIFO memory, system really directly reads data block from buffering area；Work as buffering
When area is idle, system reads data automatically at data source, and reads data as much as possible and be full of buffering area.
In the present embodiment, it is thin that the first mainboard further includes I/O interfaces, the signal for being connected and being sequentially connected in series with fpga chip respectively
Parallel circuit, signal amplification circuit and signal conditioning circuit；I/O interfaces are connected with signal sub-circuit；The letter of signal sub-circuit
The signal input part of number output terminal and signal amplification circuit connects；The signal output part and signal conditioning circuit of signal amplification circuit
Signal input part connection；The signal output part of signal conditioning circuit is connected with the signal input part of multi-channel A/D conversion circuits.
Signal sub-circuit is to improve instrument resolving power into row interpolation to periodic measuring signal using the means of circuit
A kind of method；Signal amplification circuit is used for the circuit that faint signal is amplified, for increasing electrical signal amplitude or power；Letter
Number modulate circuit is used to the analog signal to be transformed to be used for data acquisition, control process, performs and calculates display and read or other mesh
Digital signal.
Second mainboard include the second HSSI High-Speed Serial Interface, output interface, the second dma controller, the second FIFO memory and
The processor of model Atom E3826；Output interface, the second dma controller and the second HSSI High-Speed Serial Interface respectively with processor
Connection；The signal output part of second HSSI High-Speed Serial Interface and the signal input part of processor connect；The number of second FIFO memory
Connected according to the output terminal of input terminal and processor；The input of the data output end of second FIFO memory and the second dma controller
End connection；The output terminal of second dma controller and the input terminal of output interface connect.In the present embodiment, the second mainboard further includes
The second clock circuit and the second data storage being connected respectively with processor.
In the present embodiment, output interface meets the HiSLIP (high-speed of IVI (commutative virtual instrument) alliance formulation
LAN instrument protocol, high speed Ethernet instrument agreement) agreement, substantially improve the transmission speed of equipment；Second
Mainboard uses first batch of embedded controller of increasing income, the MBT-2210 mainboards of ADI Engineering productions using Intel,
MBT-2210 mainboards use the Atom E3826 processors of Intel, and " high-speed engine is realized on the basis of Linux system kernel
Driver”。
The signal output part of first HSSI High-Speed Serial Interface passes through high-speed serial bus and the signal of the second HSSI High-Speed Serial Interface
Input terminal connects.In the present embodiment, the first HSSI High-Speed Serial Interface and the second HSSI High-Speed Serial Interface be PCI-E interface and/or
USB3.0 interfaces, thus carry out power-assisted collector improving performance.
In the present embodiment, the first dma controller and the second dma controller are more than 1；Each first dma controller
There is unique corresponding one group of first FIFO memory；Each second dma controller has unique corresponding one group of the 2nd FIFO storages
Device；Thus solve the problems, such as the data collision of Multi-Channel Parallel Acquisition well, simplify user's operation, abandon traditional caching shape
Formula；Direct high speed data transfer is realized using FIFO memory and dma controller so that equipment performance, which has, greatly to be carried
It is high；FIFO memory plays the role of the buffer between dma controller and peripheral hardware or memory；FIFO memory plays DMA
Control is unique corresponding so that when cannot complete data transfer when resource is nervous, FIFO memory can provide the temporary of data flow
Area is deposited, so as to improve overall performance.
As shown in Fig. 2, the method for work of the LXI data collectors of above-mentioned high-speed transfer, comprises the following steps：
1) multichannel original data stream is gathered, multichannel original data stream is converted into more ways of digital signal by analog signal
According to stream, be ranked up by fpga chip and by multiplex data stream, then for every circuit-switched data stream interpolation data label after, will be per road
Data flow and its corresponding data label are stored in the first FIFO memory respectively；
2) the first dma controller read step 1) in data block in the first FIFO memory of deposit, and by the number of reading
Processor is transmitted to according to block；
3) data block obtained in step 2) is stored in the second FIFO memory by processor, is then controlled by the 2nd DMA
Device becomes per circuit-switched data stream and its corresponding data label after being reduced；
4) every circuit-switched data stream by reduction in step 3) is sent to master control PC machine by output interface respectively.
The data that the method for work of this data flow solves buffer type data collector need the ability after completing to gather
The problem of starting transmission, the pattern of data flow is realized to be transmitted in collection, solves the problems, such as time delay；Meanwhile introduce parallel
Control signal pattern, realizes control and data transfer parallel processing, substantially improves the performance of equipment.
The above is only the preferred embodiment of the present invention, and embodiment is used for structure, the function for understanding utility model
And effect, the protection domain being not intended to limit the present invention.Various modifications and changes may be made to the present invention, all at this
Within the spirit and principle of utility model, any modification, equivalent replacement, improvement and so on, should be included in the utility model
Protection domain within.
Claims (7)
- A kind of 1. LXI data collectors of high-speed transfer, it is characterised in that be connected including the first mainboard and with the first mainboard Two mainboards；First mainboard include fpga chip, the first dma controller, the first FIFO memory, multi-channel A/D conversion circuits and First HSSI High-Speed Serial Interface；First dma controller and the first HSSI High-Speed Serial Interface is connected with fpga chip respectively；It is described Multi-channel A/D conversion circuits signal output part and fpga chip signal input part connect；First FIFO memory Data input pin and fpga chip signal output part connect；The data output end and first of first FIFO memory The input terminal connection of dma controller；The output terminal of first dma controller and the input terminal of the first HSSI High-Speed Serial Interface connect Connect；Second mainboard includes the second HSSI High-Speed Serial Interface, output interface, the second dma controller, the second FIFO memory And the processor of model Atom E3826；Output interface, the second dma controller and the second HSSI High-Speed Serial Interface difference It is connected with processor；The signal output part of second HSSI High-Speed Serial Interface and the signal input part of processor connect；It is described The second FIFO memory data input pin and processor output terminal connect；The data of second FIFO memory are defeated Outlet is connected with the input terminal of the second dma controller；The output terminal of second dma controller and the input terminal of output interface Connection；The signal output part of first HSSI High-Speed Serial Interface passes through high-speed serial bus and the letter of the second HSSI High-Speed Serial Interface The connection of number input terminal.
- 2. the LXI data collectors of high-speed transfer according to claim 1, it is characterised in that first mainboard is also Including I/O interfaces, signal sub-circuit, signal amplification circuit and the signal condition for being connected and being sequentially connected in series with fpga chip respectively Circuit；The signal output part of the signal conditioning circuit is connected with the signal input part of multi-channel A/D conversion circuits.
- 3. the LXI data collectors of high-speed transfer according to claim 1, it is characterised in that on first mainboard Further include the first clock circuit and the first data storage being connected respectively with fpga chip；Further included on second mainboard The second clock circuit and the second data storage being connected respectively with processor.
- 4. the LXI data collectors of high-speed transfer according to claim 1, it is characterised in that second mainboard Model MBT-2210.
- 5. the LXI data collectors of high-speed transfer according to claim 1, it is characterised in that described first is gone here and there at a high speed Line interface and the second HSSI High-Speed Serial Interface are PCI-E interface and/or USB3.0 interfaces.
- 6. the LXI data collectors of high-speed transfer according to claim 1, it is characterised in that the fpga chip is EP3C40 chips.
- 7. the LXI data collectors of high-speed transfer according to claim 1, it is characterised in that the first DMA controls Device and the second dma controller are more than 1；Each first dma controller has unique corresponding one group of first FIFO memory； Each second dma controller has unique corresponding one group of second FIFO memory.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201721397473.5U CN207337649U (en) | 2017-10-25 | 2017-10-25 | A kind of LXI data collectors of high-speed transfer |
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| CN201721397473.5U CN207337649U (en) | 2017-10-25 | 2017-10-25 | A kind of LXI data collectors of high-speed transfer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107564265A (en) * | 2017-10-25 | 2018-01-09 | 成都华太测控技术有限公司 | The LXI data acquisition units and its method of work of a kind of high-speed transfer |
| CN109117398A (en) * | 2018-07-18 | 2019-01-01 | 维沃移动通信有限公司 | A kind of sensor control and terminal |
-
2017
- 2017-10-25 CN CN201721397473.5U patent/CN207337649U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107564265A (en) * | 2017-10-25 | 2018-01-09 | 成都华太测控技术有限公司 | The LXI data acquisition units and its method of work of a kind of high-speed transfer |
| CN107564265B (en) * | 2017-10-25 | 2024-03-26 | 成都华太航空科技股份有限公司 | LXI data acquisition unit for high-speed transmission and working method thereof |
| CN109117398A (en) * | 2018-07-18 | 2019-01-01 | 维沃移动通信有限公司 | A kind of sensor control and terminal |
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| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180508 Termination date: 20191025 |