CN207320123U - Memory transistor and semiconductor devices - Google Patents
Memory transistor and semiconductor devices Download PDFInfo
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- CN207320123U CN207320123U CN201721377579.9U CN201721377579U CN207320123U CN 207320123 U CN207320123 U CN 207320123U CN 201721377579 U CN201721377579 U CN 201721377579U CN 207320123 U CN207320123 U CN 207320123U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 48
- 239000000463 material Substances 0.000 claims description 42
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 45
- 230000008569 process Effects 0.000 abstract description 14
- 230000007547 defect Effects 0.000 abstract description 5
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- 238000010586 diagram Methods 0.000 description 21
- 238000002955 isolation Methods 0.000 description 12
- 239000002184 metal Substances 0.000 description 7
- 238000002360 preparation method Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
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- 230000008021 deposition Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 208000002925 dental caries Diseases 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
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- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910000951 Aluminide Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- 229910052757 nitrogen Inorganic materials 0.000 description 1
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- 239000002210 silicon-based material Substances 0.000 description 1
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Abstract
The utility model provides a kind of memory transistor and semiconductor devices.By the second dielectric layer be formed in first groove on grid layer and the first dielectric layer surface on, and there is cavity in second dielectric layer.Therefore the memory transistor in the utility model can be effectively improved mechanical stress, and reduce the defects of thermal process introduces grid；And by the introducing of cavity, parasitic capacitance can be reduced, so as to improve the performance of memory transistor.
Description
Technical field
Technical field of semiconductors is the utility model is related to, more particularly to a kind of memory transistor and semiconductor devices.
Background technology
Integrated circuit integrates tens of devices from single chip and develops into integrated millions of devices.Traditional collection
Into circuit performance and complexity considerably beyond the initial imagination.In order to realize in complexity and current densities (one
Determine the quantity of device that can be accommodated on chip area) in terms of raising, the characteristic size of device, also referred to as " physical dimension
(geometry) ", as the integrated circuit of every generation has more become smaller.Raising integrated circuit density can not only improve integrated
The complexity and performance of circuit, and consumption can be also reduced for consumers.Device smaller is challenging, because
There is the limit in every one of technique of IC manufacturing, that is to say, that if certain technique will be less than characteristic size
Under the conditions of carry out, it is necessary to replace the technique or device arrangements；Further, since the device design requirement being getting faster, traditional
There are technique limitation for technique and material.
DRAM (Dynamic Random Access Memory), i.e. dynamic random access memory are most commonly seen to be
System memory；The DRAM memory is a kind of semiconductor devices, its performance has been achieved with very big development, but still makes further progress
Demand.In the prior art, it is a kind of common structure to bury grating DRAM, and still, the grid of flush type is subject to upper dielectric
The influence of layer, is restricted its performance.
Utility model content
The purpose of this utility model is to provide the performance that a kind of memory transistor improves memory transistor.
In order to solve the above technical problems, the utility model provides a kind of memory transistor, including：
Substrate, the substrate have the first surface and second surface being oppositely arranged；The substrate also has first groove,
The opening of the first groove is formed on the first surface；
First dielectric layer, is formed in the flute wall surfaces of the first groove；
Grid layer, is formed on first dielectric layer in the first groove, and the top surface of the grid layer
Less than the first surface；And
Second dielectric layer, is filled in the first groove and on the top surface of the grid layer, and described the
Second medium layer covers the grid layer and connects first dielectric layer, also, formed with cavity in the second dielectric layer.
Optionally, for the memory transistor, the cavity occupy second dielectric layer space be more than etc.
In 5%.
Optionally, for the memory transistor, the cavity has a maximum height and a maximum width, it is described most
The first surface is oriented parallel to where big width, direction is described perpendicular to the first surface where the maximum height
Maximum height value is more than the maximum width value.
Optionally, silica is included for the memory transistor, the material of first dielectric layer.
Optionally, silicon oxide layer, silicon nitride layer are included for the memory transistor, the material of the second dielectric layer
With one kind in silicon oxynitride layer or its combination.
Optionally, for the memory transistor, the substrate also has source area and a drain region, the source area and
Drain region is respectively in the both sides of the first groove, and the bottom of the source area and drain region is in the substrate relative to described
The depth location of first surface compared with the top surface less than the grid layer in the substrate relative to the first surface
Depth location.
Optionally, for the memory transistor, the quantity of the first groove is multiple, adjacent first ditches
The source area or the drain region between groove share.
Optionally, for the memory transistor, the substrate also has second groove, and the second groove surrounds institute
Source area and drain region arrangement are stated, is full of spacer material layer in the second groove.
The utility model also provides a kind of semiconductor devices, including：
Substrate, the substrate have the first surface and second surface being oppositely arranged；The substrate also has first groove,
The opening of the first groove is formed on the first surface, and the bottom of the first groove is opposite to deviate from first table
Face；
First material layer, is formed in the flute wall surfaces of the first groove；
Second material layer, is formed in the first material layer in the first groove, the second material layer has
Less than the first top surface of the first surface；And
3rd material layer, is formed in the first groove, and covers the second material layer and the first material layer,
3rd material layer has the second top surface, also, formed with cavity in the 3rd material layer, positioned at the described first top
Between surface and second top surface.
In memory transistor provided by the utility model, the second dielectric layer is formed in first groove on grid layer and the
On one dielectric layer surface, and there is cavity in second dielectric layer.Therefore the memory transistor in the utility model can effectively change
Kind mechanical stress, and reduce the defects of thermal process introduces second dielectric layer；And by the introducing of cavity, parasitism can be reduced
Capacitance, so as to improve the performance of memory transistor.
Brief description of the drawings
Fig. 1 is a kind of structure diagram of memory transistor；
Fig. 2 is the flow diagram of the forming method of the memory transistor of one embodiment of the utility model；
Fig. 3 is the schematic diagram that substrate is provided in the forming method of the memory transistor of one embodiment of the utility model；
Fig. 4 be one embodiment of the utility model memory transistor forming method in formed in the substrate first groove and
The schematic diagram of second groove；
Fig. 5 is the signal that the first dielectric layer is formed in the forming method of the memory transistor of one embodiment of the utility model
Figure；
Fig. 6 is the schematic diagram that grid layer is formed in the forming method of the memory transistor of one embodiment of the utility model；
Fig. 7-Fig. 8 is to form showing for second dielectric layer in the forming method of the memory transistor of one embodiment of the utility model
It is intended to；
Fig. 9 is the schematic diagram of the cavity formed in the forming method of the memory transistor of one embodiment of the utility model；
Figure 10 is the schematic diagram of the cavity formed in the forming method of the memory transistor of another embodiment of the utility model；
Figure 11 is the schematic diagram of the cavity formed in the forming method of the memory transistor of another embodiment of the utility model；
Figure 12 is to form source area and drain region in the forming method of the memory transistor of one embodiment of the utility model
Schematic diagram；
Wherein, reference numeral is as follows：
1,10- substrate；
2,14- grid layers；
3- gate dielectric layers；
4,12- isolation structure layers；
S- source areas；
D- drain regions；
11- grooves；
101- first surfaces；
102- second surfaces；
13- first medium layers；
15- second dielectric layer；
16,161,162,163- cavitys；
17- second dielectric layer.
Embodiment
The memory transistor and semiconductor devices of the utility model are described in more detail below in conjunction with schematic diagram,
Which show the preferred embodiment of the utility model, it should be appreciated that those skilled in the art can change described here reality
With advantageous effects that are new, and still realizing the utility model.Therefore, description below is appreciated that for art technology
Personnel's is widely known, and is not intended as the limitation to the utility model.
The utility model is more specifically described by way of example referring to the drawings in the following passage.According to following explanation and power
The advantages of sharp claim, the utility model and feature will become apparent from.It should be noted that attached drawing using very simplified form and
Non-accurate ratio is used, only to purpose that is convenient, lucidly aiding in illustrating the utility model embodiment.
In the following description, it should be appreciated that when layer (or film), region, pattern or structure be referred to as substrate, layer (or
Film), region, pad and/or pattern " on " when, it can be on another layer or substrate, and/or can also exist and insert
Enter layer.In addition, it is to be appreciated that when layer be referred to as another layer " under " when, it can under another layer, and/or
There can also be one or more insert layers.Furthermore it is possible to carried out based on attached drawing on the reference in each layer "up" and "down".
Fig. 1 is a kind of structure diagram of memory transistor.As shown in Figure 1, the memory transistor includes substrate 1, institute
State formed with isolation structure layer 4 in substrate 1, the isolation structure layer 4 is, for example, to be formed by grooving and fill process.Described
It is, for example, buried gate structure formed with gate structure between isolation structure layer 4, including grid layer 2 and gate dielectric layer 3,
Wherein gate dielectric layer 3 covers grid layer 2, is, for example, source area S and drain region in gate structure both sides then formed with active area
D is respectively in the both sides of gate structure, and active area can carry out ion implanting acquisition according to being actually needed.
Found after inventor's research, since the grid layer 2 of buried gate structure is covered by gate dielectric layer 3, and grid
Dielectric layer 3 is uniformly densely film layer, and it is higher that this results in effective dielectric constant, and then parasitic capacitance becomes larger.It is in addition, such
The defects of gate dielectric layer 3 can bring higher mechanical stress (such as the process such as CMP introduces), and thermal process can also cause
(such as producing molecule in gate dielectric layer 3, electric leakage etc. may be caused).
For this reason, the utility model provides a kind of memory transistor, to improve drawbacks described above.Specifically, with reference to shown in figure 2
The utility model embodiment one in memory transistor forming method flow diagram.The forming method includes：
Step S11 a, there is provided substrate, the substrate have the first surface and second surface being oppositely arranged；
Step S12, forms first groove in the substrate, the opening of the first groove is formed in the first surface
On；
Step S13, forms the first dielectric layer in the flute wall surfaces of the first groove；
Step S14, forms grid layer on first dielectric layer in the first groove, the top table of the grid layer
Face is less than the first surface；And
Step S15, for the second dielectric layer of filling in the first groove, the second dielectric layer is located at the grid layer
On the top surface, the second dielectric layer covers the grid layer and connects first dielectric layer, wherein, described second
Cavity is also formed with dielectric layer.
Fig. 3 to Figure 11 is the structural representation of each step of one embodiment of forming method of the utility model memory transistor
Figure.
First, with reference to figure 3, Fig. 3 is to provide substrate in the forming method of the memory transistor of one embodiment of the utility model
Schematic diagram.
For step S11, there is provided a substrate 10, the substrate 10 have 101 and second table of first surface being oppositely arranged
Face 102.Specifically, the constituent material of the substrate 10 can use undoped monocrystalline silicon, doped with impurity monocrystalline silicon, absolutely
Silicon (SOI) etc. on edge body.As an example, in one embodiment, the substrate 10 selects single crystal silicon material to form.In the lining
This can also not be limited formed with structure known to buried regions (not shown) etc., the utility model in bottom 10.
Then, please refer to Fig.4, Fig. 4 be one embodiment of the utility model memory transistor forming method in substrate
The middle schematic diagram for forming first groove and second groove.
For step S12, first groove 111 is formed in the substrate 10, the opening of the first groove 111 is formed in
On the first surface 101.In one embodiment, the method for chemical wet etching can be used to be formed.In one embodiment, exist
Etching is formed before multiple first grooves 111, can also form multiple second grooves 112, the opening court of the second groove 112
To the first surface 101, the bottom of the second groove 112 deviates from the first surface 101.111 He of first groove
Second groove 112 can be consistent with specification, and in order to improve isolation effect, the depth of the second groove 112 is more than first ditch
The depth of groove 111, and the second groove 112 is to around the first groove 111, source area S and drain region D.It refer to
Fig. 5, full of spacer material layer in the second groove 112, forms isolation structure layer 12.In one embodiment, can be with
It is that etching forms multiple grooves, periphery (such as a row, a row) is used as second groove 112, remaining groove is then the first ditch
Groove 111.The first groove 111 will act as the preparation of follow-up buried gate structure, and the second groove 112 will act as subsequently
The preparation of isolation structure layer.
Then, please continue to refer to Fig. 5, Fig. 5 is shape in the forming method of the memory transistor of one embodiment of the utility model
Into the schematic diagram of the first dielectric layer.
For step S13, flute wall surfaces of first dielectric layer 13 in the first groove 11 are formed.In one embodiment
In, first dielectric layer 13 can be formed using chemical vapor deposition method, its material for example can be silica, its thickness
Can be 1nm-200nm.According to actual product demand, first dielectric layer 13 can be other thickness.
In one embodiment, such as in the second groove isolation structure layer 12, therefore the first dielectric have been formd
The formation of layer 13 will not have an impact second groove.First dielectric layer 13 is for example as grid oxic horizon.
The material of the isolation structure layer 12 can be at least one of silica, silicon nitride and silicon oxynitride.
After the first dielectric layer 13 and/or isolation structure layer 12 are formed, a planarization process can be carried out, for example with
Chemical mechanical planarization process so that the upper surface of first dielectric layer 13 and/or isolation structure layer 12 and first surface 101 are neat
It is flat.
It is understood that first dielectric layer 13 and the isolation structure layer 12 can be suitable with arbitrarily preparing
Sequence.
Afterwards, Fig. 6 is refer to, Fig. 6 is to form grid in the forming method of the memory transistor of one embodiment of the utility model
The schematic diagram of pole layer.
For step S14, grid layer 14 is formed on first dielectric layer 13 in the first groove 11, the grid
The top surface of pole layer 14 is less than the first surface.The grid layer 14 is, for example, metal material, it is of course also possible to select other materials
Matter, such as polysilicon etc., metal gates due to help to obtain preferable heat endurance and suitable work function and can conduct
Preferred solution.Further, the metal material is not limited only to metal simple-substance, can also be bianry alloy, the conduction of metal
Type metal oxide, metal silicide, metal nitride, metal silicide, metal nitrogen aluminide etc..
Afterwards, it refer to the forming method for the memory transistor that Fig. 7-Fig. 8, Fig. 7-Fig. 8 are one embodiment of the utility model
The middle schematic diagram for forming second dielectric layer.
For step S15, the second dielectric layer 15 of filling is in the first groove, and the second dielectric layer 15 is positioned at described
On the top surface of grid layer 14, the second dielectric layer 15 covers the grid layer 14 and connects first dielectric layer
13, wherein, it is also formed with cavity 16 in second dielectric layer 15.
Second dielectric layer 15 can be formed using chemical vapor deposition method, for example, the second dielectric layer 15 can
Think one kind in silicon oxide layer, silicon nitride layer and silicon oxynitride layer or its combination.
Second dielectric layer 15 can be formed in the first groove and on the first surface, deposited by height
The processing procedure of rate can in advance seal in the first groove first half and form required cavity 16.The utility model does not limit herein
Deposition can be adjusted flexibly on the basis of the utility model provides in specific deposition rate score, those skilled in the art, so that
Cavity 16 needed for obtaining.
After deposition is complete, flatening process can be used, removes the second dielectric layer 15 on first surface, is retained
The second dielectric layer 17 in first groove, the cavity 16 can be located in the second dielectric layer 17 retained, such as Fig. 8 institutes
Show.
In one embodiment, the space that the cavity 16 occupies second dielectric layer 17 is more than or equal to 5%.
In one embodiment, the cavity 16 has an a maximum height b and maximum width a, the maximum width a institutes
The first surface is being oriented parallel to, direction is perpendicular to the first surface where the maximum height b.Can be it is described most
Big height b is more than the maximum width a, so as to reduce preparation difficulty.
, then can be with it can be seen from the above that form cavity 16 in second dielectric layer 17 in the utility model on grid layer 14
Mechanical stress is effectively improved, and reduces the defects of thermal process introduces second dielectric layer 17 (although it is understood that above
The thermal process such as annealing is not referred to, but in memory transistor preparation process, there are the presence of thermal process, then cavity 16
The influence of thermal process can be reduced)；And by the introducing of cavity, parasitic capacitance can be reduced, so as to improve memory crystal
The performance of pipe.
The shape of cavity 16 shown in Fig. 8 is ellipse, but the utility model hollow cavity 16 can also be other shapes.
Fig. 9-Figure 11 is turned next to, schematically to describe the cavity in the utility model.Fig. 9 is one embodiment of the utility model
The schematic diagram of the cavity formed in the forming method of memory transistor；Figure 10 is the memory crystal of another embodiment of the utility model
The schematic diagram of the cavity formed in the forming method of pipe；Figure 11 is the formation of the memory transistor of another embodiment of the utility model
The schematic diagram of the cavity formed in method.
As shown in figure 9, in one embodiment, the cavity 161 can have multiple width portions and multiple narrow portions not
Regular shape, it can be up and down (direction of i.e. vertical first surface, is upper close to first surface, under being away from first surface)
The strip cavity of distribution.
As shown in Figure 10, in another embodiment, it is in drops that the cavity 162, which can be, it can be under upper width
Narrow structure or up-narrow and down-wide structure.
As shown in figure 11, In yet another embodiment, the cavity 163 can be multiple independent parts, such as can be with
It is arrangement up and down or left and right (direction of i.e. parallel first surface) arrangement or all has up and down described
Independent part, so that collectively as the cavity 163.
The structure and distribution situation of several optional cavitys are schematically listed above, it is to be understood that the sky
Chamber is not limited to species listed in the utility model, according to actual process demand, can flexibly set the structure of cavity and divide
Cloth.
Afterwards, please refer to Fig.1 and formed in the forming method for the memory transistor that 2, Figure 12 is one embodiment of the utility model
Source area and the schematic diagram of drain region.
The formation of source area and drain region can carry out after above-mentioned steps S15, you can as step S16, form source
For polar region S and drain region D in the substrate 10, the source area S and drain region D are located at the both sides of the first groove respectively,
And the bottom of the source area S and drain region D is relatively low relative to the depth location of the first surface in the substrate 10
In the grid layer 14 the top surface in the substrate 10 relative to the depth location of the first surface.
It is understood that source area S and drain region D is formed after can using ion implanting, the species of ion implanting, agent
Amount and energy can be set according to actual demand.
The quantity of the first groove is multiple, and source area S or drain region D between adjacent first trenches are shared, and is such as schemed
12, which show source area S, shares.
So far, the utility model obtains a kind of memory transistor, please continue to refer to Fig. 3-Figure 12, it is known that in the utility model
Memory transistor include：
Substrate 10, the substrate 10 have the first surface 101 and second surface 102 being oppositely arranged；The substrate 10 is also
With first groove 111, the opening of the first groove 111 is formed on the first surface 101；
First dielectric layer 13, is formed in the flute wall surfaces of the first groove 111；
Grid layer 14, is formed on first dielectric layer 13 in the first groove 111, and the grid layer 14
Top surface be less than the first surface 101；And
Second dielectric layer 17, is filled in the first groove 111, and positioned at the top surface of the grid layer 14
On, second dielectric layer 17 covers the grid layer 14 and connects first dielectric layer 13, also, in the second medium
Formed with cavity 16 in layer 17.
In one embodiment, the space that the cavity 16 occupies second dielectric layer 17 is more than or equal to 5%.
In one embodiment, the cavity 16 has an a maximum height b and maximum width a, the maximum width a institutes
The first surface 101 is being oriented parallel to, direction is perpendicular to the first surface 101 where the maximum height b.
In one embodiment, the maximum height is more than the maximum width.
In one embodiment, the material of first dielectric layer 13 includes silicon oxide layer.
In one embodiment, the material of second dielectric layer 17 includes silicon oxide layer, silicon nitride layer and silicon oxynitride
One kind or its combination in layer.
Further, the memory transistor further includes source area S and drain region D, and the source area S and drain region D divide
It is listed in 111 both sides of first groove, the bottom of the source area S and drain region D is in the substrate relative to described first
The depth location on surface compared with the top surface less than the grid layer in the substrate relative to the depth of the first surface
Spend position.
In one embodiment, the quantity of the first groove 111 is multiple, the source electrode between adjacent first trenches 111
Area S or drain region D are shared.
In one embodiment, further include second groove 112, the second groove 112 around the first groove 111,
Source area S and drain region D arranges, and is full of spacer material layer 12 in the second groove 112.
Further, the utility model also provides a kind of semiconductor devices, including：
Substrate, the substrate have the first surface and second surface being oppositely arranged；The substrate also has first groove,
The opening of the first groove is formed on the first surface, and the bottom of the first groove is opposite to deviate from first table
Face；
First material layer, is formed in the flute wall surfaces of the first groove；
Second material layer, is formed in the first material layer in the first groove, the second material layer has
Less than the first top surface of the first surface；And
3rd material layer, is formed in the first groove, and covers the second material layer and the first material layer,
3rd material layer has the second top surface, also, formed with cavity in the 3rd material layer, positioned at the described first top
Between surface and second top surface.
In conclusion in memory transistor provided by the utility model, the second dielectric layer is formed at grid in first groove
Pole layer has cavity above and on the first dielectric layer surface in second dielectric layer.Therefore the memory transistor in the utility model
Mechanical stress can be effectively improved, and reduces the defects of thermal process introduces second dielectric layer；And pass through the introducing of cavity, energy
Parasitic capacitance is enough reduced, so as to improve the performance of memory transistor.
Foregoing description is only the description to the utility model preferred embodiment, not to any limit of the scope of the utility model
Calmly, any change, the modification that the those of ordinary skill in the utility model field does according to the disclosure above content, belonging to right will
Seek the protection domain of book.
Claims (9)
- A kind of 1. memory transistor, it is characterised in that including：Substrate, the substrate have the first surface and second surface being oppositely arranged；The substrate also has first groove, described The opening of first groove is formed on the first surface；First dielectric layer, is formed in the flute wall surfaces of the first groove；Grid layer, is formed on first dielectric layer in the first groove, and the top surface of the grid layer is less than The first surface；AndSecond dielectric layer, is filled in the first groove and on the top surface of the grid layer, and described second is situated between Matter layer covers the grid layer and connects first dielectric layer, also, formed with cavity in the second dielectric layer.
- 2. memory transistor as claimed in claim 1, it is characterised in that the cavity occupies the space of second dielectric layer For more than or equal to 5%.
- 3. memory transistor as claimed in claim 1, it is characterised in that the cavity has a maximum height and a maximum width Degree, the maximum width place are oriented parallel to the first surface, and direction is perpendicular to described first where the maximum height Surface, the maximum height value are more than the maximum width value.
- 4. memory transistor as claimed in claim 1, it is characterised in that the material of first dielectric layer includes silica.
- 5. memory transistor as claimed in claim 1, it is characterised in that the material of the second dielectric layer includes silica Layer, silicon nitride layer and one kind in silicon oxynitride layer or its combination.
- 6. memory transistor as claimed in claim 1, it is characterised in that the substrate also has source area and drain region, institute State source area and drain region is respectively in the both sides of the first groove, the bottom of the source area and drain region is in the substrate Relative to the first surface depth location compared with the top surface less than the grid layer in the substrate relative to institute State the depth location of first surface.
- 7. memory transistor as claimed in claim 6, it is characterised in that the quantity of the first groove is adjacent to be multiple The source area or the drain region between the first groove share.
- 8. memory transistor as claimed in claim 6, it is characterised in that the substrate also has a second groove, and described second Groove is arranged around the source area and the drain region, is full of spacer material layer in the second groove.
- A kind of 9. semiconductor devices, it is characterised in that including：Substrate, the substrate have the first surface and second surface being oppositely arranged；The substrate also has first groove, described The opening of first groove is formed on the first surface, and the bottom of the first groove is opposite to deviate from the first surface；First material layer, is formed in the flute wall surfaces of the first groove；Second material layer, is formed in the first material layer in the first groove, and the second material layer, which has, to be less than First top surface of the first surface；And3rd material layer, is formed in the first groove, and covers the second material layer and the first material layer, described 3rd material layer has the second top surface, also, formed with cavity in the 3rd material layer, positioned at first top surface Between second top surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721377579.9U CN207320123U (en) | 2017-10-24 | 2017-10-24 | Memory transistor and semiconductor devices |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721377579.9U CN207320123U (en) | 2017-10-24 | 2017-10-24 | Memory transistor and semiconductor devices |
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| CN207320123U true CN207320123U (en) | 2018-05-04 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019080850A1 (en) * | 2017-10-24 | 2019-05-02 | Changxin Memory Technologies, Inc. | Memory transistor, fabrication method thereof and semiconductor device |
| CN113206055A (en) * | 2020-02-03 | 2021-08-03 | 联华电子股份有限公司 | Semiconductor structure with air gap |
-
2017
- 2017-10-24 CN CN201721377579.9U patent/CN207320123U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019080850A1 (en) * | 2017-10-24 | 2019-05-02 | Changxin Memory Technologies, Inc. | Memory transistor, fabrication method thereof and semiconductor device |
| US11329049B2 (en) | 2017-10-24 | 2022-05-10 | Changxin Memory Technologies, Inc. | Memory transistor with cavity structure |
| CN113206055A (en) * | 2020-02-03 | 2021-08-03 | 联华电子股份有限公司 | Semiconductor structure with air gap |
| CN113206055B (en) * | 2020-02-03 | 2023-08-01 | 联华电子股份有限公司 | Semiconductor structure with air gap |
| US11848253B2 (en) | 2020-02-03 | 2023-12-19 | United Microelectronics Corp. | Semiconductor structure with an air gap |
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