CN207320099U - The encapsulating structure of semiconductor chip - Google Patents
The encapsulating structure of semiconductor chip Download PDFInfo
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- CN207320099U CN207320099U CN201720931811.2U CN201720931811U CN207320099U CN 207320099 U CN207320099 U CN 207320099U CN 201720931811 U CN201720931811 U CN 201720931811U CN 207320099 U CN207320099 U CN 207320099U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model provides a kind of encapsulating structure of semiconductor chip, including：Chip structure to be packaged；Re-wiring layer, is formed on chip structure to be packaged, it has the first face being electrically connected with the chip structure to be packaged and second face opposite with first face, and described second shows out metal wiring layer；Metal coupling, is directly made on the metal wiring layer；And polymeric layer, the polymeric layer surrounds the metal coupling, and exposes the part for having the metal coupling on the polymeric layer.The utility model need not make ubm layer on re-wiring layer; one layer of polymeric layer only need to be made to protect metal coupling; the bond strength between ubm layer and re-wiring layer can be increased; and it can be protected, prevent the influence to metal coupling and re-wiring layer such as oxidation and steam；The utility model technique and structure are simpler, can effectively reduce the cost of packaging technology and structure.
Description
Technical field
A kind of semiconductor package is the utility model is related to, more particularly to a kind of encapsulating structure of semiconductor chip.
Background technology
As the integrated circuit that the function of integrated circuit is increasingly stronger, performance and integrated level are higher and higher and new goes out
Existing, encapsulation technology plays an increasingly important role in IC products, shared in the value of whole electronic system
Ratio it is increasing.Meanwhile as integrated circuit feature size reaches nanoscale, transistor to more high density, higher when
Clock frequency develops, and encapsulation also develops to more highdensity direction.
Since fan-out wafer level encapsulates (fowlp) technology due to having the advantages that miniaturization, low cost and high integration, with
And the energy efficiency with better performance and higher, fan-out wafer level encapsulation (fowlp) technology as high request movement/
The important method for packing of the electronic equipments such as wireless network, is one of encapsulation technology most with prospects at present.
A kind of encapsulating structure of existing semiconductor chip is as shown in Figure 1, it includes semiconductor chip 202, encapsulating material
201, re-wiring layer 203, ubm layer 204 (UBM) and the metal being made on the ubm layer (UBM)
Convex block 205, the ubm layer 204 (UBM) can effectively strengthen the metal coupling 205 and the re-wiring layer
Contact strength, in order to avoid the generation for the defects of metal coupling 205 drops.However, the manufacture craft due to ubm layer
It is more complicated, packaging technology and the cost of encapsulating structure can be greatly improved.
Therefore it provides a kind of technique and simple in structure, can effectively reduce the envelope of the semiconductor chip of packaging technology cost
Assembling structure and method for packing are necessary.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of envelope of semiconductor chip
The problem of assembling structure and method for packing, packaging technology and structure are more complicated in the prior art for solution, and cost is higher.
In order to achieve the above objects and other related objects, the utility model provides a kind of encapsulating structure of semiconductor chip,
Including：Chip structure to be packaged；Re-wiring layer, is formed on the chip structure to be packaged, the re-wiring layer has
The first face and second face opposite with first face being electrically connected with the chip structure to be packaged, described second shows
Go out the metal wiring layer having included in the re-wiring layer；Metal coupling, is directly made on the metal wiring layer；With
And polymeric layer, the second face of the re-wiring layer is formed at, the polymeric layer surrounds the metal coupling, and described poly-
Exposing on compound layer has the part of the metal coupling.
Preferably, the chip structure to be packaged includes semiconductor chip and is coated on the encapsulation of the semiconductor chip
There is the electric one side of deriving structure to be in same plane with the lower surface of the encapsulating material for material, the semiconductor chip.
Preferably, the re-wiring layer includes alternately stacked patterned dielectric layer and patterned metal line
Layer, wherein, the top layer of the re-wiring layer is patterned dielectric layer, and exposing in the patterned dielectric layer has metal line
Layer.
Further, the material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorus silicon glass
One or both of glass, fluorine-containing glass combination of the above, the material of the metal wiring layer are included in copper, aluminium, nickel, gold, silver, titanium
One or more kinds of combinations.
Preferably, the metal coupling includes copper post, the nickel layer positioned at the copper post upper surface and positioned at the nickel layer
On solder bump.
Further, the metal barrier includes nickel layer, and the material of the solder bump includes one in lead, tin and silver
Kind or the alloy for including any one above-mentioned solder metal.
Preferably, the encapsulating material includes one kind in polyimides, silica gel and epoxy resin.
Preferably, the polymeric layer is epoxy resin layer.
Preferably, the encapsulating structure of the semiconductor chip is applied to fan-out-type wafer-level packaging FOWLP, wafer stage chip
Encapsulate WLCSP, wafer-level packaging WLP or three dimensional integrated circuits 3DIC.
The utility model also provides a kind of method for packing of semiconductor chip, including：1) chip structure to be packaged is provided；
2) in forming re-wiring layer on the chip structure to be packaged, the re-wiring layer has and the chip knot to be packaged
The first face and second face opposite with first face that structure is electrically connected, described second shows out described in again
Metal wiring layer in wiring layer；3) on the metal wiring layer directly make metal coupling；4) in the re-wiring layer
The second face form polymeric layer, the polymeric layer surrounds the metal coupling, and expose on the polymeric layer have it is described
The part of metal coupling.
Preferably, the chip structure to be packaged includes semiconductor chip and is coated on the encapsulation of the semiconductor chip
There is the electric one side of deriving structure to be in same plane with the lower surface of the encapsulating material for material, the semiconductor chip.
Preferably, step 1) provides the chip structure to be packaged and includes：A support substrate 1-1) is provided, in the substrate
Surface forms separating layer；Semiconductor chip 1-2) is provided, the semiconductor chip is adhered in the separating layer, wherein, institute
Stating semiconductor chip has the one of electric deriving structure facing to the separating layer；1-3) using encapsulating material to the conductor chip
It is packaged；The encapsulating material and the support substrate 1-4) are separated based on the separating layer so that the semiconductor chip
One side and the lower surface of the encapsulating material with electric deriving structure are in same plane.
Preferably, the support substrate includes glass substrate, metal substrate, Semiconductor substrate, polymer substrate and ceramics
One kind in substrate；The separating layer includes one kind in adhesive tape and polymeric layer, and the polymeric layer uses spin coating work first
Skill is coated on the support substrate surface, then makes its curing molding using ultra-violet curing or heat curing process.
Preferably, using encapsulating material encapsulate the semiconductor chip method include compression forming, Transfer molding,
One kind in fluid-tight shaping, vacuum lamination and spin coating, the encapsulating material are included in polyimides, silica gel and epoxy resin
It is a kind of.
Preferably, step 2) makes the re-wiring layer as alternately following steps：Using chemical vapor deposition work
Skill or physical gas-phase deposition form dielectric layer in the plane of the semiconductor chip and encapsulating material, and to the dielectric layer
Perform etching to form patterned dielectric layer；Using chemical vapor deposition method, evaporation process, sputtering technology, electroplating technology or
Chemical plating process in the patterned media layer surface formed metal layer, and the metal layer is performed etching to be formed it is patterned
Metal wiring layer.
Preferably, the material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass,
One or both of fluorine-containing glass combination of the above, the material of the metal wiring layer are included in copper, aluminium, nickel, gold, silver, titanium
One or more combination.
Preferably, in step 3), the top layer of the re-wiring layer is patterned dielectric layer, the patterned medium
Layer expose patterned metal wiring layer, on the patterned metal wiring layer directly making metal coupling.
Preferably, the preparation method of the metal coupling includes step：A) using galvanoplastic in the re-wiring layer table
Face forms copper post；B) using galvanoplastic metal barrier is formed in the copper post surface；C) hindered using galvanoplastic in the metal
Barrier surface forms solder metal, and forms solder bump in the metal barrier layer surface using high temperature reflow processes.
Further, the metal barrier includes nickel layer, and the material of the solder bump includes one in lead, tin and silver
Kind or the alloy for including any one above-mentioned solder metal.
Preferably, the method for packing of the semiconductor chip is applied to fan-out-type wafer-level packaging FOWLP, wafer stage chip
Encapsulate WLCSP, wafer-level packaging WLP or three dimensional integrated circuits 3DIC.
As described above, the encapsulating structure and method for packing of the semiconductor chip of the utility model, have the advantages that：
1) the utility model need not make ubm layer (UBM) on re-wiring layer, form metal coupling
Afterwards, make one layer of polymeric layer to protect the metal coupling, which surrounds the metal coupling, on the one hand
Its bond strength between re-wiring layer can be increased, prevent it from rocking or dropping, on the other hand it can be protected,
Prevent the influence to the re-wiring layer of metal coupling and lower section such as oxidation and steam；
2) the utility model need not make ubm layer (UBM), and technique and structure more simply can be reduced effectively
The cost of packaging technology and encapsulating structure；
3) the utility model can be applied to such as fan-out-type wafer-level packaging FOWLP, wafer stage chip encapsulation WLCSP, crystalline substance
Circle level encapsulation WLP or three dimensional integrated circuits 3DIC etc. need to make in the encapsulating structure of re-wiring layer, are led in semiconductor packages
Domain is with a wide range of applications.
Brief description of the drawings
Fig. 1 is shown as the structure diagram of fan-out package structure of the prior art.
Fig. 2-Fig. 8 is shown as the structural representation that each step of method for packing of the semiconductor chip of the utility model is presented
Figure, wherein, Fig. 8 is shown as the structure diagram of the encapsulating structure of the semiconductor chip of the utility model.
Component label instructions
101 support substrates
102 separating layers
103 semiconductor chips
104 encapsulating materials
30 re-wiring layers
105 first medium layers
106 metal wiring layers
107 second dielectric layer
108 metal couplings
109 polymeric layers
Embodiment
Illustrate the embodiment of the utility model below by way of specific instantiation, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints with answering
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Refer to Fig. 2~Fig. 8.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, when only display is with related component in the utility model rather than according to actual implementation in illustrating then
Component count, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation
Become, and its assembly layout kenel may also be increasingly complex.
As shown in Fig. 2~Fig. 8, the present embodiment provides a kind of method for packing of semiconductor chip 103, including：
As shown in Fig. 2~Fig. 5, step 1) is carried out first, there is provided a chip structure to be packaged.
As an example, the chip structure to be packaged includes semiconductor chip 103 and is coated on the semiconductor chip
103 encapsulating material 104, the semiconductor chip 103 have the one side and the following table of the encapsulating material 104 of electric deriving structure
Face is in same plane.
Specifically, step 1) provides the chip structure to be packaged and includes：
As shown in Fig. 2, carrying out step 1-1), there is provided a support substrate 101, separating layer 102 is formed in the substrate surface；
As an example, the support substrate 101 include glass substrate, metal substrate, Semiconductor substrate, polymer substrate and
One kind in ceramic substrate.In the present embodiment, it is glass substrate that the support substrate 101, which is selected, the glass substrate cost
It is relatively low, separating layer 102 easily is formed on its surface, and the difficulty of follow-up stripping technology can be reduced.
As an example, the separating layer 102 includes one kind in adhesive tape and polymeric layer, the polymeric layer uses first
Spin coating proceeding is coated on 101 surface of support substrate, then makes its curing molding using ultra-violet curing or heat curing process.
In the present embodiment, it is heat-curable glue that the separating layer 102, which is selected, and being formed at the support by spin coating proceeding serves as a contrast
After on bottom 101, its curing molding is made by heat curing process.Heat-curable glue performance is stablized, and surface is more smooth, is conducive to follow-up
Re-wiring layer 30 making, also, in follow-up stripping technology, the difficulty of stripping is relatively low, can have been obtained after stripping
Re-wiring layer 30 whole and of good performance.
As shown in figure 3, carrying out step 1-2), there is provided semiconductor chip 103, institute is adhered to by the semiconductor chip 103
State in separating layer 102, wherein, the semiconductor chip 103 has the one of electric deriving structure facing to the separating layer 102.
As an example, the semiconductor chip 103 can be one or more, can according to need the function realized and into
The arbitrary combination of row, and electrical interconnection is realized by follow-up re-wiring layer 30.
As shown in figure 4, carrying out step 1-3), the conductor chip is packaged using encapsulating material 104.
As an example, the method for the semiconductor chip 103 is encapsulated using encapsulating material 104 includes compression forming, transmission
One kind in molded, fluid-tight shaping, vacuum lamination and spin coating, the encapsulating material 104 include polyimides, silica gel and
One kind in epoxy resin.
As shown in figure 5, carrying out step 1-4), the encapsulating material 104 and the support are separated based on the separating layer 102
Substrate 101 so that the semiconductor chip 103 have the electric one side of deriving structure with the lower surface of the encapsulating material 104
In same plane.
For example, when the selection of separating layer 102 is adhesive tape, the method removed can be used to separate the encapsulating material 104
With the support substrate 101, this technique is relatively simple, can effectively reduce cost.
As shown in fig. 6, step 2) is then carried out, it is described in formation re-wiring layer 30 on the chip structure to be packaged
Re-wiring layer 30 has the first face for being electrically connected with the chip structure to be packaged and opposite with first face the
Two faces, described second shows out the metal wiring layer 106 included in the re-wiring layer 30；
As an example, step 2) makes the re-wiring layer 30 as alternately following steps：Using chemical vapor deposition
Product technique or physical gas-phase deposition form dielectric layer in the plane of the semiconductor chip 103 and encapsulating material 104, and right
The dielectric layer performs etching to form patterned dielectric layer；Using chemical vapor deposition method, evaporation process, sputtering technology,
Electroplating technology or chemical plating process form metal layer in the patterned media layer surface, and perform etching shape to the metal layer
Into patterned metal wiring layer 106.The material of the dielectric layer include epoxy resin, silica gel, PI, PBO, BCB, silica,
One or both of phosphorosilicate glass, fluorine-containing glass combination of the above, the material of the metal wiring layer 106 include copper, aluminium, nickel,
One or both of gold, silver, titanium combination of the above.
Specifically, step 2), which makes the re-wiring layer 30, includes step：
Step 2-1), using chemical vapor deposition method or physical gas-phase deposition in the 102 surface shape of separating layer
Perform etching to form patterned first medium layer 105 into first medium layer 105, and to the dielectric layer.
As an example, the material of the first medium layer 105 include epoxy resin, silica gel, PI, PBO, BCB, silica,
One or both of phosphorosilicate glass, fluorine-containing glass combination of the above.In the present embodiment, the first medium layer 105, which is selected, is
Silica.
Step 2-2), using chemical vapor deposition method, evaporation process, sputtering technology, electroplating technology or chemical plating process
In patterned 105 forming metal layer on surface of first medium layer, and the metal layer is performed etching to be formed it is patterned
Metal wiring layer 106, the metal wiring layer 106 is with passing through the patterned first medium layer 105 and the semiconductor core
The electric deriving structure of piece 103 is connected；
As an example, the material of the metal wiring layer 106 include copper, aluminium, nickel, gold, silver, one or both of titanium with
Upper combination.In the present embodiment, the material selection of the metal wiring layer 106 is copper.
Step 2-3), using chemical vapor deposition method or physical gas-phase deposition in 106 table of metal wiring layer
Face forms second dielectric layer 107, and the dielectric layer is performed etching to form patterned second dielectric layer 107, the figure
The second dielectric layer 107 of change is exposed in the region of metal coupling 108 to be prepared the metal wiring layer 106.
As an example, the material of the second dielectric layer 107 include epoxy resin, silica gel, PI, PBO, BCB, silica,
One or both of phosphorosilicate glass, fluorine-containing glass combination of the above.In the present embodiment, the second dielectric layer 107, which is selected, is
Silica.
It should be noted that the re-wiring layer 30 can include the multiple dielectric layers stacked gradually and multiple metals
Wiring layer 106, according to line demand, each layer metal line is realized by each dielectric layer being patterned or being made through hole
Interconnection between layer 106, to realize the line demand of difference in functionality.
As shown in fig. 7, then carry out step 3), on the metal wiring layer 106 directly making metal coupling 108.
As an example, the top layer of the re-wiring layer 30 is patterned dielectric layer, the patterned dielectric layer dew
Go out patterned metal wiring layer 106, on the patterned metal wiring layer 106 directly make metal coupling 108.
As an example, the preparation method of the metal coupling 108 includes step：A) using galvanoplastic in the rewiring
106 surface of metal wiring layer that the top of layer 30 is exposed forms copper post；B) using galvanoplastic metal resistance is formed in the copper post surface
Barrier；C) solder metal is formed in the metal barrier layer surface using galvanoplastic, and using high temperature reflow processes in the gold
Belong to barrier layer surface and form solder bump.Further, the metal barrier includes nickel layer, the material bag of the solder bump
Include one kind in lead, tin and silver or include the alloy of any one above-mentioned solder metal.
And for example, the metal coupling 108 is tin ball, is directly made in the hardware cloth that the top of re-wiring layer 30 is exposed
106 surface of line layer.
As shown in figure 8, finally carrying out step 4), polymeric layer 109, institute are formed in the second face of the re-wiring layer 30
State polymeric layer 109 and surround the metal coupling 108, and expose the portion for having the metal coupling 108 on the polymeric layer 109
Point.
As an example, made using one kind in compression forming, Transfer molding, fluid-tight shaping, vacuum lamination and spin coating
Make the polymeric layer 109, the material of the polymeric layer 109 includes one kind in polyimides, silica gel and epoxy resin.
In the present embodiment, the polymeric layer 109 is epoxy resin layer.
The utility model need not make ubm layer (UBM) on re-wiring layer 30, form metal coupling
After 108, make one layer of polymeric 109 pairs of metal coupling 108 of layer and protect, which surrounds the gold
Belong to convex block 108, on the one hand can increase its bond strength between re-wiring layer 30, prevent it from rocking or dropping, the opposing party
Face can protect it, prevent the influence to the re-wiring layer 30 of metal coupling 108 and lower section such as oxidation and steam；This
Utility model need not make ubm layer (UBM), and technique and structure more simply can effectively reduce packaging technology and envelope
The cost of assembling structure.
As an example, the method for packing of the semiconductor chip 103 is applied to make being fanned out to for re-wiring layer 30
Type wafer-level packaging FOWLP, wafer stage chip encapsulation WLCSP, wafer-level packaging WLP or three dimensional integrated circuits 3DIC, are applicable in model
Enclose extensively, there is very good application prospect in this conductor encapsulation field.
As shown in figure 8, the present embodiment also provides a kind of encapsulating structure of semiconductor chip 103, including：Chip knot to be packaged
Structure；Re-wiring layer 30, is formed on the chip structure to be packaged, and the re-wiring layer 30 has and the core to be packaged
The first face and second face opposite with first face that chip architecture is electrically connected, described second shows out included in described
Metal wiring layer 106 in re-wiring layer 30；Metal coupling 108, is directly made on the metal wiring layer 106；And
Polymeric layer 109, is formed at the second face of the re-wiring layer 30, and the polymeric layer 109 surrounds the metal coupling
108, and expose the part for having the metal coupling 108 on the polymeric layer 109.
As an example, the chip structure to be packaged includes semiconductor chip 103 and is coated on the semiconductor chip
103 encapsulating material 104, the semiconductor chip 103 have the one side and the following table of the encapsulating material 104 of electric deriving structure
Face is in same plane.
As an example, the re-wiring layer 30 includes alternately stacked patterned dielectric layer and patterned metal
Wiring layer 106, wherein, the top layer of the re-wiring layer 30 is patterned dielectric layer, is exposed in the patterned dielectric layer
There is metal wiring layer 106.Further, the material of the dielectric layer include epoxy resin, silica gel, PI, PBO, BCB, silica,
One or both of phosphorosilicate glass, fluorine-containing glass combination of the above, the material of the metal wiring layer 106 include copper, aluminium, nickel,
One or both of gold, silver, titanium combination of the above.
As an example, the metal coupling 108 includes copper post, the nickel layer positioned at the copper post upper surface and positioned at institute
State the solder bump on nickel layer.Further, the metal barrier includes nickel layer, the material of the solder bump include lead,
One kind in tin and silver or the alloy for including any one above-mentioned solder metal.
As an example, the encapsulating material 104 includes one kind in polyimides, silica gel and epoxy resin.
As an example, the polymeric layer 109 is epoxy resin layer.
As an example, the encapsulating structure of the semiconductor chip 103 is applied to fan-out-type wafer-level packaging FOWLP, wafer
Level chip package WLCSP, wafer-level packaging WLP or three dimensional integrated circuits 3DIC.
As described above, the encapsulating structure and method for packing of the semiconductor chip 103 of the utility model, have below beneficial to effect
Fruit：
1) the utility model need not make ubm layer (UBM) on re-wiring layer 30, and being formed, metal is convex
After block 108, make one layer of polymeric 109 pairs of metal coupling 108 of layer and protect, the polymeric layer 109 is around described
Metal coupling 108, on the one hand can increase its bond strength between re-wiring layer 30, prevent it from rocking or dropping, another
Aspect can protect it, prevent the influence to the re-wiring layer 30 of metal coupling 108 and lower section such as oxidation and steam；
2) the utility model need not make ubm layer (UBM), and technique and structure more simply can be reduced effectively
The cost of packaging technology and encapsulating structure；
3) the utility model can be applied to such as fan-out-type wafer-level packaging FOWLP, wafer stage chip encapsulation WLCSP, crystalline substance
Circle level encapsulation WLP or three dimensional integrated circuits 3DIC etc. need to make in the encapsulating structure of re-wiring layer 30, in semiconductor packages
Field is with a wide range of applications.
So the utility model effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above embodiments are only illustrative of the principle and efficacy of the utility model, new not for this practicality is limited
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
God and all equivalent modifications completed under technological thought or change, should be covered by the claim of the utility model.
Claims (8)
- A kind of 1. encapsulating structure of semiconductor chip, it is characterised in that including：Chip structure to be packaged；Re-wiring layer, is formed on the chip structure to be packaged, and the re-wiring layer has and the chip to be packaged The first face and second face opposite with first face that structure is electrically connected, described second shows out included in described heavy Metal wiring layer in new route layer；Metal coupling, is directly made on the metal wiring layer；AndPolymeric layer, is formed at the second face of the re-wiring layer, and the polymeric layer surrounds the metal coupling, and described Exposing on polymeric layer has the part of the metal coupling.
- 2. the encapsulating structure of semiconductor chip according to claim 1, it is characterised in that：The chip structure bag to be packaged Include semiconductor chip and be coated on the encapsulating material of the semiconductor chip, the semiconductor chip has electric deriving structure Simultaneously the lower surface with the encapsulating material is in same plane.
- 3. the encapsulating structure of semiconductor chip according to claim 1, it is characterised in that：The re-wiring layer includes handing over Patterned dielectric layer and patterned metal wiring layer for stacking, wherein, the top layer of the re-wiring layer is figure The dielectric layer of change, exposing in the patterned dielectric layer has metal wiring layer.
- 4. the encapsulating structure of semiconductor chip according to claim 1, it is characterised in that：The metal coupling includes copper Column, the metal barrier positioned at the copper post upper surface and the solder bump on the metal barrier.
- 5. the encapsulating structure of semiconductor chip according to claim 4, it is characterised in that：The metal barrier includes nickel Layer, the material of the solder bump include one kind in lead, tin and silver or include the alloy of any one above-mentioned solder metal.
- 6. the encapsulating structure of semiconductor chip according to claim 1, it is characterised in that：The material bag of the polymeric layer Include one kind in polyimides, silica gel and epoxy resin.
- 7. the encapsulating structure of semiconductor chip according to claim 1, it is characterised in that：The polymeric layer is asphalt mixtures modified by epoxy resin Lipid layer.
- 8. the encapsulating structure of semiconductor chip according to claim 1, it is characterised in that：The encapsulation of the semiconductor chip Structure is applied to fan-out-type wafer-level packaging FOWLP, wafer stage chip encapsulation WLCSP, wafer-level packaging WLP or three-dimensionally integrated electricity Road 3DIC.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201720931811.2U CN207320099U (en) | 2017-07-28 | 2017-07-28 | The encapsulating structure of semiconductor chip |
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| CN201720931811.2U CN207320099U (en) | 2017-07-28 | 2017-07-28 | The encapsulating structure of semiconductor chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107452702A (en) * | 2017-07-28 | 2017-12-08 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure and method for packing of semiconductor chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107452702A (en) * | 2017-07-28 | 2017-12-08 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure and method for packing of semiconductor chip |
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