CN207234816U - A kind of VPX power boards of SRIO and Ethernet - Google Patents
A kind of VPX power boards of SRIO and Ethernet Download PDFInfo
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- CN207234816U CN207234816U CN201721054459.5U CN201721054459U CN207234816U CN 207234816 U CN207234816 U CN 207234816U CN 201721054459 U CN201721054459 U CN 201721054459U CN 207234816 U CN207234816 U CN 207234816U
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Abstract
The utility model discloses a kind of SRIO and the VPX power boards of Ethernet, including outgoing interface, 10,000,000,000 network interface groups, SRIO exchange chips one and SRIO exchange chips two after management processor, ten thousand mbit ethernet PHY chips, Ethernet switch, VPX, the management processor is connected with Ethernet switch communication, the Ethernet switch is connected with ten thousand mbit ethernets PHY chip communication, and the SRIO exchange chips one, the SRIO exchange chips two and the Ethernet switch are connected with outgoing interface after the VPX.The utility model is under limited structure size, utilize the function of exchange for being integrated with two planes of SRIO and Ethernet, the data exchange of more than the 100Gbps of SRIO and Ethernet is realized by optimal hardware structure, and exchange capacity meets the application demand of most of data exchanges in present industry;The utility model has the advantages that simple in structure, performance is stable and service life is longer.
Description
Technical field
It the utility model is related to power board technical field, more particularly to the VPX power boards of a kind of SRIO and Ethernet.
Background technology
Embedded exchange system is on the increase recently as the demand of the computer system of VPX frameworks, for high-performance
SRIO and the demand of Ethernet exchanging plate also increase therewith, it is desirable to systems exchange bandwidth reaches more than 100 Gigabits per seconds.It is right
It is badly in need of high-performance SRIO and Ethernet exchanging plate as system in military project and industrial control field, especially radar data processing system
Core function of exchange, the data volume that various types of board interacts between each other in case system is increasing, and bandwidth will
Ask higher and higher, and there are stability and reliability in these fields very strict requirements, how to pass through optimal system
Framework meets the exchange requirement of big data, so that these technologies can be applied to these fields, becomes the friendship of computer nowadays system
Change the emphasis of application study.
The content of the invention
The purpose of this utility model is that the VPX for providing a kind of SRIO and Ethernet to solve the above-mentioned problems is exchanged
Plate.
The utility model is achieved through the following technical solutions above-mentioned purpose:
The utility model include management processor, ten thousand mbit ethernet PHY chips, Ethernet switch, outgoing interface after VPX,
10000000000 network interface groups, SRIO exchange chips one and SRIO exchange chips two, the management processor are led to the Ethernet switch
News connection, the communication of the Ethernet switch and the Ethernet PHY chip connect, the SRIO exchange chips one, described
SRIO exchange chips two and the Ethernet switch are connected with outgoing interface after the VPX.
The utility model is preferable, after outgoing interface after VPX including going out after P0 interfaces, VPX to go out P1 interfaces, VPX after the VPX
Go out after P2 interfaces, VPX after P3 interfaces, VPX after P4 interfaces, VPX after going out P5 interfaces and VPX and go out P6 interfaces, the SRIO is handed over
Chip one is changed to go out P6 interface communications with going out after P4 interfaces, the VPX to go out after the VPX respectively after P5 interfaces and the VPX and be connected,
The SRIO exchange chips two go out P6 after P3 interfaces and the VPX and connect with going out after P2 interfaces, the VPX to go out after the VPX respectively
Mouth communication connection, the Ethernet switch are connected with going out P1 interface communications after the VPX.
The utility model is preferable, and the 10000000000 network interface group includes the 10000000000th network interface, the 20000000000th network interface, the 30000000000th
Network interface and the 40000000000th network interface, the ten thousand mbit ethernets PHY chip respectively with the 10000000000th network interface, the 20000000000th net
Mouth, the 30000000000th network interface and the 40000000000th network interface communication connection.
The utility model is preferable, and the management processor communication is connected with memory, serial line interface and USB interface.
The beneficial effects of the utility model are:
The utility model provides the VPX power boards of a kind of SRIO and Ethernet, under limited structure size, using integrated
The functions of exchange of two planes of SRIO and Ethernet, the 100Gbps of SRIO and Ethernet is realized by optimal hardware structure
Data exchange above, and exchange capacity meets the application demand of most of data exchanges in present industry;This reality
Have the advantages that simple in structure, performance is stable and service life is longer with new.
Brief description of the drawings
Fig. 1 is the structure diagram of the VPX power boards of SRIO and Ethernet described in the utility model;
Fig. 2 is the electrical block diagram of the VPX power boards of SRIO and Ethernet described in the utility model.
Embodiment
The utility model is described in further detail below in conjunction with the accompanying drawings:
As shown in Figure 1:The utility model includes management processor, ten thousand mbit ethernet PHY chips, Ethernet switch, VPX
Outgoing interface, 10,000,000,000 network interface groups, SRIO exchange chips one and SRIO exchange chips two afterwards, the management processor and the Ethernet
Interchanger communication connection, the Ethernet switch are connected with Ethernet PHY chip communication, the SRIO exchange chips
First, the SRIO exchange chips two and the Ethernet switch are connected with outgoing interface after the VPX, go out to connect after the VPX
Mouth goes out P0 interfaces after including VPX, and P1 interfaces are gone out after VPX, P2 interfaces are gone out after VPX, P3 interfaces are gone out after VPX, P4 interfaces are gone out after VPX,
Go out after VPX after P5 interfaces and VPX and go out P6 interfaces, the SRIO exchange chips one are respectively with going out P4 interfaces, described after the VPX
Go out P5 interfaces after VPX and connected with P6 interface communications are gone out after the VPX, the SRIO exchange chips two after the VPX respectively with going out
Go out P3 interfaces after P2 interfaces, the VPX and connected with P6 interface communications are gone out after the VPX, the Ethernet switch and the VPX
After go out P1 interface communications connection, the 10000000000 network interface group include the 10000000000th network interface, the 20000000000th network interface, the 30000000000th network interface and
40000000000th network interface, the ten thousand mbit ethernets PHY chip respectively with the 10000000000th network interface, the 20000000000th network interface, institute
The 30000000000th network interface and the 40000000000th network interface communication connection are stated, the management processor communication is connected with memory, serial interface
Mouth and USB interface.
As shown in Fig. 2, welding two panels SRIO exchange chips on board, each exchange chip can draw 12 SRIO and connect
Mouthful, wherein 2 ports are used between exchange chip cascade, it is left the 10000000000 of VPX connectors gone out after 10 ports are all guided to
On network interface.SRIO exchange chips periphery also needs to auxiliary circuit to realize that the port of exchange chip configures, and comprising port speed, connects
Mouth bus bit wide and configuration.Memory is used to store the information such as the routing table of SRIO exchange chips, SRIO when board powers on
Configuration content in the automatic load store chip of exchange chip.Tri- pins of SPD0, SPD1 and SPD2 of exchange chip pass through upper
Pull-up resistor or the operating rate of pull down resistor configuration SRIO ports.J17 is a double contact pin in Fig. 2, can connect burning and set
The configuration of standby programming SRIO chips.This 8 pins of QCFG0 ~ QCFG7 are used for configuring port number and the end of exchange chip
Mouth width degree.This 10 pins of ID0 ~ ID9 are used for configuring the address of the I2C slave devices of exchange chip.Drawn by the above configuration
The configuration of foot, SRIO exchange chips can work normally, and can realize flexible configuration and the management of exchange chip.
In conclusion the utility model provides a kind of VPX power boards of SRIO and Ethernet, in limited structure size
(160mm x 233.35mm)Under, using the function of exchange for being integrated with two planes of SRIO and Ethernet, pass through optimal hardware
Framework realizes the data exchange of more than the 100Gbps of SRIO and Ethernet, and exchange capacity is met in present industry
The application demand of most of data exchanges;The utility model has the advantages that simple in structure, performance is stable and service life is longer.
Those skilled in the art do not depart from the essence and spirit of the utility model, can have various deformation scheme to realize this reality
With new, the above is only the preferred feasible embodiment of the utility model, not thereby limits to the power of the utility model
Sharp scope, all equivalent structure changes made with the utility model specification and accompanying drawing content, is both contained in the utility model
Interest field within.
Claims (4)
1. the VPX power boards of a kind of SRIO and Ethernet, it is characterised in that including management processor, ten thousand mbit ethernet PHY cores
Outgoing interface, 10,000,000,000 network interface groups, SRIO exchange chips one and SRIO exchange chips two, the pipe after piece, Ethernet switch, VPX
Manage processor to connect with Ethernet switch communication, the Ethernet switch connects with Ethernet PHY chip communication
Connect, the SRIO exchange chips one, the SRIO exchange chips two and the Ethernet switch with outgoing interface after the VPX
Connection.
2. the VPX power boards of SRIO according to claim 1 and Ethernet, it is characterised in that:Outgoing interface bag after the VPX
Go out P0 interfaces after including VPX, P1 interfaces are gone out after VPX, P2 interfaces are gone out after VPX, P3 interfaces are gone out after VPX, go out P4 interfaces after VPX, after VPX
Go out P6 interfaces after going out P5 interfaces and VPX, the SRIO exchange chips one after going out P4 interfaces, the VPX after the VPX respectively with going out
P5 interfaces are connected with P6 interface communications are gone out after the VPX, the SRIO exchange chips two respectively with go out after the VPX P2 interfaces,
Go out P3 interfaces after the VPX and connected with P6 interface communications are gone out after the VPX, the Ethernet switch after the VPX with going out P1
Interface communication connects.
3. the VPX power boards of SRIO according to claim 1 and Ethernet, it is characterised in that:The 10000000000 network interface group bag
Include the 10000000000th network interface, the 20000000000th network interface, the 30000000000th network interface and the 40000000000th network interface, the ten thousand mbit ethernets PHY chip
Lead to respectively with the 10000000000th network interface, the 20000000000th network interface, the 30000000000th network interface and the 40000000000th network interface
News connection.
4. the VPX power boards of SRIO according to claim 1 and Ethernet, it is characterised in that:The management processor is led to
News are connected with memory, serial line interface and USB interface.
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CN201721054459.5U CN207234816U (en) | 2018-02-08 | 2018-02-08 | A kind of VPX power boards of SRIO and Ethernet |
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CN201721054459.5U CN207234816U (en) | 2018-02-08 | 2018-02-08 | A kind of VPX power boards of SRIO and Ethernet |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109240960A (en) * | 2018-10-26 | 2019-01-18 | 天津光电通信技术有限公司 | A kind of power board circuit and its implementation based on VPX framework |
CN109547365A (en) * | 2018-10-29 | 2019-03-29 | 中国航空无线电电子研究所 | A kind of unmanned Combat Command System data exchange system based on SRIO |
CN112039805A (en) * | 2020-08-27 | 2020-12-04 | 成都坤恒顺维科技股份有限公司 | Low-delay jitter high-speed signal switching system |
CN115022238A (en) * | 2022-06-08 | 2022-09-06 | 华东计算技术研究所(中国电子科技集团公司第三十二研究所) | Route processing system of multi-path Ethernet on satellite and SRIO interface |
-
2018
- 2018-02-08 CN CN201721054459.5U patent/CN207234816U/en active Active
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109240960A (en) * | 2018-10-26 | 2019-01-18 | 天津光电通信技术有限公司 | A kind of power board circuit and its implementation based on VPX framework |
CN109240960B (en) * | 2018-10-26 | 2023-11-24 | 天津光电通信技术有限公司 | Exchange board circuit based on VPX architecture and implementation method thereof |
CN109547365A (en) * | 2018-10-29 | 2019-03-29 | 中国航空无线电电子研究所 | A kind of unmanned Combat Command System data exchange system based on SRIO |
CN109547365B (en) * | 2018-10-29 | 2021-04-30 | 中国航空无线电电子研究所 | SRIO-based data exchange system of unmanned finger control system |
CN112039805A (en) * | 2020-08-27 | 2020-12-04 | 成都坤恒顺维科技股份有限公司 | Low-delay jitter high-speed signal switching system |
CN115022238A (en) * | 2022-06-08 | 2022-09-06 | 华东计算技术研究所(中国电子科技集团公司第三十二研究所) | Route processing system of multi-path Ethernet on satellite and SRIO interface |
CN115022238B (en) * | 2022-06-08 | 2023-10-27 | 华东计算技术研究所(中国电子科技集团公司第三十二研究所) | Route processing system of on-board multipath Ethernet and SRIO interface |
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