CN207148827U - A kind of device that RS232 and RS485 interface standard group equipment is supported based on SoC - Google Patents

Abstract

The utility model supports the device of RS232 and RS485 interface standard group equipment based on SoC, including：The processor module of PS units inside SoC, and the UART controller that PS units carry；PL units inside SoC；It is connected inside SoC between PS and PL by AXI EBIs；EMIO data-interfaces inside SoC between PS and PL, PS_UART_TX, PS_UART_RX, PS_UART_RTSN signals are defined on EMIO data-interfaces；AXI protocol parsing module and UART bus control modules in PL unit indoor designs；UART bus control modules are connected by electrical level transferring chip with 2 RS485 bus apparatus and 1 RS232 bus apparatus.The utility model simplifies the UART controller peripheral circuit outside SoC on circuit board, reduces the PCB layer number of circuit board, reduces production cost.

Description

A kind of device that RS232 and RS485 interface standard group equipment is supported based on SoC

Technical field

The invention belongs to communication technical field, more particularly to a kind of SoC that is based on to support RS232 and RS485 interface standard groups The device of equipment.

Background technology

Programmable SoC (AP SoC) is integrated with the hard of field programmable gate array (PL, Programmable Logic) entirely The software programmable of part programmability and arm processor (PS, Processing System), can not only be realized hardware-accelerated Controlled with software, and can highly integrated DSP, CPU, ASSP on a single chip, realize the PS+PL frameworks of function innovation type, and Possess huge OS, middleware, protocol stack, accelerator and IP ecological environments and multi-level software and hardware safety.Inside SoC PS and Communication mode has AXI (Advanced extensible Interface) and EMIO (Extendable between PL Multiplexed I/O) two kinds of communication modes.

AXI (Advanced extensible Interface) is a kind of bus protocol, and the agreement is that ARM companies propose AMBA (Advanced Microcontroller Bus Architecture) 3.0 agreements in most important part, be a kind of Towards high-performance, high bandwidth, low latency bus on chip.Its address/control and data phase are separation, support not lining up Data transfer, while in burst transfer, it is only necessary to first address, while the read-write data channel that separates and support Outstanding transmission accesses and out of order access, and is more prone to carry out timing closure.AXI is a new high property in AMBA Can agreement.AXI technologies enrich existing AMBA standard contents, meet very-high performance and the design of complicated on-chip system (SoC) Demand.AXI in complete programmable SoC mainly by read/write address bus (RW_ADDR), read data bus (RD_DATA), write number According to bus (WR_DATA), handshake composition (Handshake).

UART (Universal Asynchronous Receiver/Transmitter) is that a kind of Universal Serial is total Line, for asynchronous communication.The bus two-way communication, it is possible to achieve full duplex transmission and reception.In embedded design, UART is used Communicate with auxiliary equipment in main frame, such as the communication between automobile audio and external AP, communicated with PC including with monitoring debugger And other devices, as EEPROM communicates.

RS-232C is that EIA (EIA) and CCITT (CCITT) lead to be serial Believe a kind of standard that equipment is formulated.The standard provides：For RS-232C using negative logic regulation logic level, -3V--15V is logic Level"1" ,+3V -+15V are level "0".This signal level and the LVTTL/LVCMOS level used in usual parallel interface Difference, can be by MAX232 chips by LVTTL/LVCMOS and RS-232C conversion.

Electronic Industries Association (EIA) works out in nineteen eighty-three and issues RS-485 standards, and is repaiied through Telecommunications Industries Association (TIA) TIA/EIA-485-A is named as after ordering, habitually referred to as RS-485 standards.RS-485 standards be for make up RS-232 communication away from From the short, shortcoming such as speed is low and it is caused.RS-485 standards specify only the electrical characteristics of balance transmitters and receivers, without Provide connector, transmission cable and application layer communication protocol.RS-485 standards and RS-232 are different, and data-signal uses difference Transmission means (Differential Driver Mode), also referred to as balance transmission, it uses a pair of twisted-pair feeders, will a wherein line A is defined as, another line is defined as B.Under normal circumstances, positive level between transmitter A, B is sent in+2~+6V, is one and is patrolled The state of collecting；Negative level is another logic state in -2~-6V.Separately there is a signal ground C.It is general to go back in RS-485 devices There is " enabled " control signal." enabled " signal is used to control the cut-out and connection for sending transmitter and transmission line, when " making Can " end when working, sends transmitter and be in high-impedance state, be referred to as " tri-state ", it is be different from logical one and " 0 " the Three kinds of states.For receiver transmitter, the regulation relative with sending transmitter is also made, Transmitting and Receiving End will by balancing twisted-pair line A-A is corresponding with B-B to be connected.When there is the level more than+200mV between receiving terminal A-B, export as positive logic level；Less than- During 200mV, export as negative logic level.On the receiving balance line of receiver transmitter, level range generally 200mV to 6V it Between.

MDAS (Multiservice Distributed Access System Solution) is a kind of multi-service distribution System, Duo Jia operators, multi-standard, multicarrier, and integrated wlan system can be supported, a step, which solves voice and data service, to be needed Ask, compared with traditional analog compartment system, be provided simultaneously with mixed networking, delay compensation, automatic carrier track, up bottom make an uproar it is low Feature.

MDAS is made up of access unit (MAU), expanding element (MEU) and far-end unit (MRU).Digital system in MDAS System subdivision have cdma system, GSM/DCS/WCDMA double-standards system, GSM/DCS/TD-SDMA double-standard systems, provide 2G, While 3G mobile communication services, wlan system is integrated, meets the high-rate wireless data transfer demands of user.

MDAS system group network ability, 1 MAU can band 4 MEU, 1 MEU can 8 MRU of band, 1 MAU can be with 4*8*8 =256 MRU.Connected before MAU, MEU and MRU by optical module with optical fiber.

The content of the invention

The problem of existing for prior art, at based on SoC as system control and algorithm The problem of managing UART controller deficiency in the circuit single plate of chip.The present invention utilizes the UART controller that PS is carried in SoC Solving system with the PL modules inside SoC needs to control the demand of 2 RS485 interface equipments and 1 RS232 interface equipment.

In order to realize foregoing invention purpose, the technical solution adopted by the present invention is：One kind based on SoC support RS232 and The device of RS485 interface standard group equipment, it is characterised in that it includes：

The processor module of PS units inside SoC, and the UART controller that PS units carry；

PL units inside SoC；

It is connected inside SoC between PS units and PL units by AXI EBIs；

EMIO data-interfaces inside SoC between PS units and PL units, PS_UART_TX is defined on EMIO data-interfaces, PS_UART_RX, PS_UART_RTSN signal；

Two modules are newly devised inside PL units, one is AXI protocol parsing module, and one is UART bus marcos Module；

The UART bus control modules are connected by LVCOMS/RS485 electrical level transferring chips with RS485 interface equipments；

The UART bus control modules are connected by LVCOMS/RS232 electrical level transferring chips with RS232 interface equipment.

The above-mentioned device that RS232 and RS485 interface standard group equipment is supported based on SoC, it is further characterized by：

The data bit width of the read/write address bus (RW_ADDR) of AXI buses is 32bit；Read data bus (RD_DATA) Data bit width is that 32bit, the data bit width of write data bus (WR_DATA) are 32bit.

A control register UART_SEL is defined to UART bus control modules in AXI protocol parsing module, this Register address is 0x00000090, and data bit width is 3bit (UART_SEL [2:0]), UART_SEL controls UART bus marcos The channel selecting of module.

The AXI protocol parsing module：

The handshake (Handshake) for waiting PS to be sended over by AXI buses；

Whether the data for judging address bus are 0x00000090；

If the data of address bus are 0x00000090, continue according to handshake judge be currently write operation or Read operation；

If the data of write operation and RW_ADDR address bus are 0x00000090, WR_DATA low 3bit data It is assigned to UART_SEL；

If the data of read operation and RW_ADDR address bus are 0x00000090, UART_SEL is assigned to RD_ DATA low 3bit, high 29bit data are entered as 0.

The UART_SEL signal decidings PS that the UART bus control modules pass through AXI bus control modules according to PS units UART buses between unit and PL units are connected to one in 2 RS485 bus apparatus and 1 RS232 bus apparatus.

The control software of PS units according to system work requirements, determine current PS units UART controller and 3 outsides One in equipment is communicated；

PS units control the concrete numerical value of UART_SEL registers by AXI buses and AXI protocol parsing module；

UART bus control modules according to the numerical value of UART_SEL control signals, the data/address bus of UART controller with it is right The external device data bus connection answered；

Needed between UART controller and external equipment by LVCOMS/RS232 and LVCOMS/RS485 level conversion cores Piece carries out level conversion.

The UART bus control units module：When the UART controller of PS units needs operation is outside to set as master controller When standby, UART_SEL control signals determine that one in PS UART controller and outside 3 external equipments is communicated.

Beneficial effect：The present invention's supports that the device of RS232 and RS485 interface standard group equipment is excellent with 3 based on SoC Point, 1：The logical resource that the present invention utilizes the PL modules inside PS is carried in SoC a UART controller and SoC unnecessary solves System needs to control the demand of 2 RS485 interface equipments and 1 RS232 interface equipment.If without the present invention, in circuit Just at least need 3 UART control chips to meet system design considerations, using the present invention can save hardware purchase into This.

2：Because whole designs of the present invention are completed inside SoC, the UART controller outside SoC on circuit board is simplified Peripheral circuit, it is possible to reduce the PCB layer number of circuit board, further reduce production cost.

3：Because the peripheral circuits of SoC on circuit boards further simplify, it is possible to the debug time of circuit board is reduced, Lift efficiency of research and development.

Brief description of the drawings

Fig. 1 is the device block diagram that the present invention supports RS232 and RS485 interface standard group equipment based on SoC.

Fig. 2 is the workflow diagram of the AXI protocol parsing module of the embodiment of the present invention.

Embodiment

For the ease of the understanding of those skilled in the art, the present invention is made further with reference to embodiment and accompanying drawing It is bright.

PS inside SoC supports two independent universal asynchronous receiving-transmitting controller (UART, Universal Asynchronous Receiver/Transmitter), the two UART controllers support the mode of operation of full-duplex communication, And the software programmable of serial communication speed is supported to control.UART controller mainly provides following functions：Will be by being transmitted inside PS The parallel data to come over is converted to the serial data stream of output, the serial data come from external reception is converted into byte, for PS The device of internal parallel data uses；Parity check bit is added in the serial data stream of output, and to the number from external reception Even-odd check is carried out according to stream；Start and stop mark is added in output stream, and start and stop mark is deleted in data flow from receiving.

Main following 3 signals for using PS UART controllers inside SoC of the invention：

1：PS_UART_TX is the data-signal transmission interface of UART controller；

2：PS_UART_RX is the data signal reception interface of UART controller；

3：PS_UART_RTSN is the control signal output interface in RS485 bus data streams direction.

There is the serial bus of UART controller inside PS supports UART interface standard group equipment outside two kind modes and SoC Connection：

1：The serial bus of UART controller is connected by SoC MIO interfaces with the serial bus interface of external equipment；

2：The EMIO interfaces that the serial bus of UART controller first passes through PS and PL are connected to PL internal programmable logics, so FPGA common I/O port is connected to by the FPGA inside PL again afterwards, finally in FPGA common I/O port and external equipment Serial ports controlling bus interface connection.

Controlled at one using may be programmed SoC entirely as system in the circuit single plate with algorithm process, because a PS UART Controller need it is independent leave equipment for and start as debugging and system use, so only a UART controller is to SoC Ancillary equipment use.

Such as need 2 RS485 interfaces and 1 RS232 interface is set in the MRU circuit single plates design of MADS systems It is standby.Now with the hardware platform based on SoC can not meet this device requirement, therefore the present invention is carried using PS inside SoC UART controller and PL modules realize a kind of device for supporting RS232 and RS485 interface standard group equipment.

Embodiment

The present embodiment realizes a kind of support using the UART controllers carried of PS inside complete programmable SoC and PL modules The device of RS232 and RS485 interface standard group equipment.

The present embodiment is mainly realized using following 5 modules：

1：The processor module of PS units inside SoC, and the UART controller that PS units carry；

2：PL units inside SoC；

3：AXI EBIs inside SoC between PS and PL；

4：EMIO data-interfaces inside SoC between PS and PL, PS_UART_TX, PS_UART_ are defined on EMIO interfaces RX, PS_UART_RTSN signal；

5：Two modules are newly devised inside PL, one is AXI protocol parsing module, and one is UART bus marco moulds Block.

The device block diagram of the present embodiment is as shown in Figure 1.

The data bit width of the read/write address bus (RW_ADDR) of AXI buses is 32bit；Read data bus (RD_DATA) Data bit width is that 32bit, the data bit width of write data bus (WR_DATA) are 32bit.

A control register UART_SEL is defined to UART bus control modules in AXI parsing modules, this deposit Device address is 0x00000090, and data bit width is 3bit (UART_SEL [2:0]), UART_SEL controls the passage choosing of UART buses Select.The implementation of AXI protocol parsing module is as follows：

1：The handshake (Handshake) for waiting PS to be sended over by AXI buses；

2：Whether the data for judging address bus are 0x00000090；

3：If the data of address bus are 0x00000090, continue according to handshake judge be currently write operation also It is read operation；

4：If the data of write operation and RW_ADDR address bus are 0x00000090, WR_DATA low 3bit numbers According to being assigned to UART_SEL；

5：If the data of read operation and RW_ADDR address bus are 0x00000090, UART_SEL is assigned to RD_ DATA low 3bit, high 29bit data are entered as 0.

The workflow of AXI protocol parsing module is as shown in Figure 2.

Between UART_SEL signal decidings PS and PL that UART bus control modules pass through AXI bus marcos according to PS UART buses are connected to one in 2 RS485 bus apparatus and 1 RS232 equipment.

The present apparatus and method whole system working implementations are as follows：

1：PS control software is according to system work requirements, in the UART controller and 3 external equipments that determine current PS One communicated；

2：PS controls the concrete numerical value of UART_SEL registers by AXI buses and AXI protocol parsing module；

3：UART bus control modules according to the numerical value of UART_SEL control signals, the data/address bus of UART controller with Corresponding external device data bus connection；

4：Needed between UART controller and external equipment by LVCOMS/RS232 and LVCOMS/RS485 level conversions Chip carries out level conversion.

The workflow implementation of UART bus control unit modules is as follows：

1：When PS UART controller needs to operate external equipment as master controller, UART_SEL control signals determine One in PS UART controller and outside 3 external equipments is communicated.

2：4 groups of serial bus are defined in UART bus control modules,

First group of bus：PS_UART_TX_0, PS_UART_TX_0, PS_UART_RTSN_0,

The electrical level transferring chip communication that this group of bus is connected with RS485 interface equipments 0；

Second group of bus：PS_UART_TX_1, PS_UART_TX_1, PS_UART_RTSN_1,

The electrical level transferring chip communication that this group of bus is connected with RS485 interface equipments 1；

3rd group of bus：PS_UART_TX_2, PS_UART_TX_2,

The electrical level transferring chip communication that this group of bus is connected with RS323 interface equipments；

4th group of bus：PS_UART_TX, PS_UART_TX, PS_UART_RTSN, this group of bus be UART controller and UART data communication bus between UART bus control modules.

3：The bus signals design implementation of UART bus control units is as follows：

Here is the design method of the control signal of the data flow direction of UART controller control RS485 half-duplex operations：

PS_UART_RTSN and UART_SEL [0] the two signal numerical value take or are assigned to PS_UART_RTSN_0；

PS_UART_RTSN and UART_SEL [1] the two signal numerical value take or are assigned to PS_UART_RTSN_1.

Here is the design method that UART controller is output to external device data signal：

PS_UART_TX and UART_SEL [0] the two signal numerical value take or are assigned to PS_UART_TX_0；

PS_UART_TX and UART_SEL [1] the two signal numerical value take or are assigned to PS_UART_TX_1；

PS_UART_TX and UART_SEL [2] the two signal numerical value take or are assigned to PS_UART_TX_2.

Here is the design method that external equipment is output to UART controller data-signal, and designs three intermediate variable letters Number：RX_0, RX_1, RX_2；

PS_UART_RX_0 and UART_SEL [0] the two signal numerical value take or are assigned to RX_0；

PS_UART_RX_1 and UART_SEL [1] the two signal numerical value take or are assigned to RX_1；

PS_UART_RX_2 and UART_SEL [2] the two signal numerical value take or are assigned to RX_2；

These three signal numerical value of RX_0, RX_1 and RX_2 take and are assigned to PS_UART_RX.

The technological thought of embodiment above only to illustrate the invention, it is impossible to protection scope of the present invention is limited with this, it is all It is any change for being done on the basis of technical scheme according to technological thought proposed by the present invention, each falls within present invention protection model Within enclosing.The technology that the present invention is not directed to can be realized by existing technology.

Claims (9)

1. a kind of device that RS232 and RS485 interface standard group equipment is supported based on SoC, it is characterised in that it includes：

The processor module of PS units inside SoC, and the UART controller that PS units carry；

PL units inside SoC；

It is connected inside SoC between PS units and PL units by AXI EBIs；

EMIO data-interfaces inside SoC between PS units and PL units, PS_UART_TX, PS_ are defined on EMIO data-interfaces UART_RX, PS_UART_RTSN signal；

Two modules are newly devised inside PL units, one is AXI protocol parsing module, and one is UART bus marco moulds Block；

The UART bus control modules are connected by LVCOMS/RS485 electrical level transferring chips with RS485 interface equipments；

The UART bus control modules are connected by LVCOMS/RS232 electrical level transferring chips with RS232 interface equipment.

2. the device according to claim 1 that RS232 and RS485 interface standard group equipment is supported based on SoC, its feature are existed In：

The read/write address bus of AXI buses（RW_ADDR）Data bit width be 32bit；The data of read data bus (RD_DATA) Bit wide is that 32bit, the data bit width of write data bus (WR_DATA) are 32bit.

3. the device according to claim 1 that RS232 and RS485 interface standard group equipment is supported based on SoC, its feature are existed In：

A control register UART_SEL is defined to UART bus control modules in AXI protocol parsing module, this deposit Device address is 0x00000090, and data bit width is 3bit (UART_SEL [2:0]), UART_SEL controls UART bus control modules Channel selecting.

4. the device according to claim 1 that RS232 and RS485 interface standard group equipment is supported based on SoC, its feature are existed In the AXI protocol parsing module：

The handshake for waiting PS to be sended over by AXI buses（Handshake）；

Whether the data for judging address bus are 0x00000090；

If the data of address bus are 0x00000090, continue to judge to be currently write operation according to handshake or read behaviour Make；

If the data of write operation and RW_ADDR address bus are 0x00000090, WR_DATA low 3bit data assignment To UART_SEL；

If the data of read operation and RW_ADDR address bus are 0x00000090, UART_SEL is assigned to RD_DATA's Low 3bit, high 29bit data are entered as 0.

5. the device according to claim 1 that RS232 and RS485 interface standard group equipment is supported based on SoC, its feature are existed In：

The UART_SEL signal deciding PS units that the UART bus control modules pass through AXI bus control modules according to PS units UART buses between PL units are connected to one in 2 RS485 bus apparatus and 1 RS232 bus apparatus.

6. the device according to claim 5 that RS232 and RS485 interface standard group equipment is supported based on SoC, its feature are existed In：

The control software of PS units determines the UART controller and 3 external equipments of current PS units according to system work requirements In one communicated；

PS units control the concrete numerical value of UART_SEL registers by AXI buses and AXI protocol parsing module；

UART bus control modules according to the numerical value of UART_SEL control signals, the data/address bus of UART controller with it is corresponding External device data bus connects；

Need to enter by LVCOMS/RS232 and LVCOMS/RS485 electrical level transferring chips between UART controller and external equipment Line level is changed.

7. the device according to claim 5 that RS232 and RS485 interface standard group equipment is supported based on SoC, its feature are existed In the UART bus control units module：

When the UART controller of PS units needs to operate external equipment as master controller, UART_SEL control signals determine PS UART controller and outside 3 external equipments in one communicated.

8. the device according to claim 7 that RS232 and RS485 interface standard group equipment is supported based on SoC, its feature are existed In the UART bus control modules define 4 groups of serial bus：

First group of bus：PS_UART_TX_0, PS_UART_TX_0, PS_UART_RTSN_0,

The electrical level transferring chip communication that this group of bus is connected with RS485 interface equipments 0；

Second group of bus：PS_UART_TX_1, PS_UART_TX_1, PS_UART_RTSN_1,

The electrical level transferring chip communication that this group of bus is connected with RS485 interface equipments 1；

3rd group of bus：PS_UART_TX_2, PS_UART_TX_2,

The electrical level transferring chip communication that this group of bus is connected with RS323 interface equipments；

4th group of bus：PS_UART_TX, PS_UART_TX, PS_UART_RTSN, this group of bus be UART controller and UART data communication bus between UART bus control modules.

9. the device according to claim 8 that RS232 and RS485 interface standard group equipment is supported based on SoC, its feature are existed In：

The control signal of the data flow direction of UART controller control RS485 half-duplex operations：

PS_UART_RTSN and UART_SEL [0] the two signal numerical value take or are assigned to PS_UART_RTSN_0；

PS_UART_RTSN and UART_SEL [1] the two signal numerical value take or are assigned to PS_UART_RTSN_1；

UART controller is output to external device data signal：

PS_UART_TX and UART_SEL [0] the two signal numerical value take or are assigned to PS_UART_TX _ 0；

PS_UART_TX and UART_SEL [1] the two signal numerical value take or are assigned to PS_UART_TX _ 1；

PS_UART_TX and UART_SEL [2] the two signal numerical value take or are assigned to PS_UART_TX _ 2；

External equipment is output to UART controller data-signal：

PS_UART_RX_0 and UART_SEL [0] the two signal numerical value take or are assigned to intermediate variable signal RX_0；

PS_UART_RX_1 and UART_SEL [1] the two signal numerical value take or are assigned to intermediate variable signal RX_1；

PS_UART_RX_2 and UART_SEL [2] the two signal numerical value take or are assigned to intermediate variable signal RX_2；

These three intermediate variable signal numerical value of RX_0, RX_1 and RX_2 take and are assigned to PS_UART_RX.