CN207133762U - A kind of electrification reset circuit of no quiescent dissipation - Google Patents
A kind of electrification reset circuit of no quiescent dissipation Download PDFInfo
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- CN207133762U CN207133762U CN201720925464.2U CN201720925464U CN207133762U CN 207133762 U CN207133762 U CN 207133762U CN 201720925464 U CN201720925464 U CN 201720925464U CN 207133762 U CN207133762 U CN 207133762U
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Abstract
It the utility model is related to a kind of electrification reset circuit of no quiescent dissipation, including voltage detecting circuit, hysteresis comparator circuit and the voltage shaping circuit being sequentially connected electrically；Voltage detecting circuit includes transistor MN1, transistor MN2, transistor MP1 and transistor MP2；Transistor MN1, transistor MP1, transistor MN2 and transistor MP2 are sequentially connected in series, and the drain electrode of the latter transistor is connected with the source electrode of previous transistor；Transistor MN1 drain electrode and transistor MP1 source electrode are connected with hysteresis comparator circuit respectively；The output signal of voltage detecting circuit is converted into square wave by hysteresis comparator circuit；Voltage shaping circuit is used to eliminate the small sample perturbations in square wave, and its output end is the output end of electrification reset circuit.The utility model eliminates quiescent dissipation while replying bit function by cable in realization, can be widely applied to the low-power consumption such as handheld device field by selecting P-channel type metal-oxide-semiconductor to solve the problems, such as quiescent dissipation be present.
Description
Technical field
The utility model belongs to semiconductor integrated circuit technical field, and in particular to a kind of electrification reset of no quiescent dissipation
Circuit.
Background technology
Upper voltage from scratch, at RESET can first in high level for a period of time, then because the point is connect by resistance
The level of ground then RESET points can gradually change into low level so that monolithic processor resetting mouth level from 1 to 0, reach to
The function of monolithic processor resetting.Such a reset mode is exactly so-called electrification reset.
Electrification reset circuit (POR, power-on reset) is widely used in various IC chips, is carried for system
For the power-on reset signal of safety；Circuit is forbidden to work during voltage as defined in can not reaching in chip power, when chip power reaches
An indication signal is provided after to defined voltage, prompts chip to start normal work.But under prior art,
Electrification reset circuit also has the quiescent current of a μ A rank after chip normal work, correct with assurance function.Existing skill
Art for example in the system of Internet of Things, handheld device etc., can increase the quiescent dissipation of system, drop in the application of some extremely low power dissipations
The service efficiency of low energy.
Under prior art, electrification reset circuit is required for consuming quiescent current after chip normal work, to ensure
Function is correct.By taking existing patent document as an example, a kind of entitled " power-on-reset circuit with low power consumption " (application publication number
CN106033960A the technical scheme as shown in Figure 1 of patent notes), after circuit normal work, due to exhaust pipe MD1 and
MD2 is N-channel depletion type MOS tube, and the A point voltages in Fig. 1 are close to supply voltage, therefore N-channel depletion type MOS tube can not
Complete switch off, have a quiescent current and produce.
The shortcomings that prior art be exactly electrification reset circuit normal operating conditions due to N-channel depletion type MOS tube not
It can complete switch off, a quiescent current can be produced, be not suitable for the application of extremely low power dissipation, such as Internet of Things, handheld device etc..
In addition, being required for por circuit in almost all of chip system, the circuit in chip is returned into initial shape
State.Digital circuit in chip is especially needed to reset circuit, the shift register in whole circuit, D in digital circuit
Trigger and counter all return to original state or clearing, and in analog circuit, reset signal is also required to sometimes by circuit
Original state is returned to, normal operating conditions is rapidly introduced into ensure circuit.In order to meet these requirements, traditional POR
Circuit can take larger space, and this is not intended to see in an integrated system.
Utility model content
In view of this, the purpose of this utility model is overcome the deficiencies in the prior art, there is provided one kind is nearly free from quiet
The electrification reset circuit of state electric current.
To realize object above, the utility model adopts the following technical scheme that：
A kind of electrification reset circuit of no quiescent dissipation, including the voltage detecting circuit, sluggish more electric being sequentially connected electrically
Road and voltage shaping circuit；
The voltage detecting circuit includes transistor MN1, transistor MN2, transistor MP1 and transistor MP2；The crystal
Pipe MN1, the transistor MP1, the transistor MN2 and the transistor MP2 are sequentially connected in series, the drain electrode of the latter transistor with
The source electrode connection of previous transistor；
The drain and gate of the transistor MN1 is connected with power end；The grid of the transistor MP1 and the crystal
Pipe MN2 grid connection；The source ground of the transistor MP2, grid are connected with power end；
The drain electrode of the transistor MN1 and the source electrode of the transistor MP1 are connected with the hysteresis comparator circuit respectively；Institute
State hysteresis comparator circuit and the output signal of the voltage detecting circuit is converted into square wave；The voltage shaping circuit is used to disappear
Except the small sample perturbations in square wave, its output end is the output end of the electrification reset circuit.
The grounded-grid of the transistor MN2.
The voltage detecting circuit controls reset level by adjusting transistor MP1 and transistor MN1 gate source voltage.
The transistor MN2 is the metal-oxide-semiconductor of N-channel depletion type MOS tube or negative threshold voltage；The transistor MP2 is P
Channel depletion type metal-oxide-semiconductor.
Further, the transistor MN2 and transistor MP2 forms the biasing of the voltage detecting circuit；
Further, in power up, supply voltage VDD has conducting electric current when relatively low in the transistor MP2；Upper electricity
After the completion of, supply voltage VDD can complete switch off the transistor MP2, to realize without quiescent dissipation.
The hysteresis comparator circuit includes transistor MN3, transistor MN4, transistor MP3 and transistor MP4；
Further, the grid of the transistor MN3 and the drain electrode to drain with the transistor MN1 are connected；
The drain electrode of the transistor MP3 is connected with the source electrode of the transistor MN3, the source of source electrode and the transistor MP1
Pole connects；
The drain electrode of the transistor MP4 is connected with the drain electrode of the transistor MN3, the source of grid and the transistor MP3
Pole is connected, and source electrode is connected with the grid of the transistor MP3；
The drain electrode of the transistor MN4 is connected with the source electrode of the transistor MP4, the source of grid and the transistor MP3
Pole connects；
The drain electrode of the transistor MP4 and the drain electrode of the transistor MN4 and source electrode are electric with the voltage shaping respectively
Road connects.
The hysteresis comparator circuit adjusts electricity by adjusting the transistor MP3 and the transistor MN3 breadth length ratio
The hysteresis voltage on road.
The voltage shaping circuit includes transistor MN5 and transistor MP5；
The drain electrode of the transistor MP5 is connected with the drain electrode of the transistor MP4, the leakage of grid and the transistor MN4
Pole connects；
The drain electrode of the transistor MN5 is connected with the source electrode of the transistor MP5, the grid of grid and the transistor MP5
Pole is connected, and source electrode is connected with the source electrode of the transistor MN4；
The drain electrode of the transistor MN5 is the output end of the electrification reset circuit.
The source ground of the transistor MN5.
The transistor MN5 is N-channel type metal-oxide-semiconductor, and the transistor MP5 is P-channel type metal-oxide-semiconductor.
The utility model uses above technical scheme, asking for quiescent dissipation be present by selecting P-channel type metal-oxide-semiconductor to solve
Topic, in normal operation, quiescent current can be ignored and (is less than 0.1nA) electrification reset circuit of the present utility model,
It is considered that quiescent dissipation is not present in engineer applied.The utility model can realize traditional electrification reset function, again may be used
Without quiescent dissipation, the low-power consumption such as Internet of Things, handheld device field can be widely used in.
Electrification reset function, the sky taken in integrated circuits can be achieved only with a small amount of metal-oxide-semiconductor in the utility model
Between very little, therefore can reduce chip cost, reduce chip volume.
Brief description of the drawings
, below will be to embodiment in order to illustrate more clearly of the utility model embodiment or technical scheme of the prior art
Or the required accompanying drawing used is briefly described in description of the prior art, it should be apparent that, drawings in the following description are only
It is some embodiments of the utility model, for those of ordinary skill in the art, is not paying the premise of creative work
Under, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the electrification reset circuit that prior art provides；
Fig. 2 is the structural representation of electrification reset circuit provided by the utility model；
Fig. 3 is the physical circuit figure of electrification reset circuit provided by the utility model.
In figure：1- voltage detecting circuits；2- hysteresis comparator circuits；3- voltage shaping circuits.
Embodiment
, below will be to technology of the present utility model to make the purpose of this utility model, technical scheme and advantage clearer
Scheme is described in detail.Obviously, described embodiment is only the utility model part of the embodiment, rather than all
Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not before creative work is made
Resulting all other embodiment is put, belongs to the scope that the utility model is protected.
As shown in Fig. 2 the utility model provides a kind of electrification reset circuit of no quiescent dissipation, including be sequentially connected electrically
Voltage detecting circuit 1, hysteresis comparator circuit 2 and voltage shaping circuit 3.
Input power vdd voltage is exported to hysteresis comparator circuit 2 and voltage shaping circuit 3 after overvoltage detection circuit 1
Afterwards, final output is signal POR.
For this patent is described in further detail, carries out expansion and be described as follows：
As shown in figure 3, the voltage detecting circuit 1 includes transistor MN1, transistor MN2, transistor MP1 and transistor
MP2；The transistor MN1, the transistor MP1, the transistor MN2 and the transistor MP2 are sequentially connected in series, and the latter is brilliant
The drain electrode of body pipe is connected with the source electrode of previous transistor；I.e.：
The drain electrode of the transistor MP1 is connected with transistor MN1 source electrode；The drain electrode of the transistor MN2 and transistor
MP1 source electrode connection；The drain electrode of the transistor MP2 is connected with transistor MN2 source electrode.
The drain and gate of the transistor MN1 is connected with power end VDD；The grid of the transistor MP1 with it is described
Transistor MN2 grid connection；The source ground of the transistor MP2, grid are connected with power end VDD；
The drain electrode of the transistor MN1 and the source electrode of the transistor MP1 are connected with the hysteresis comparator circuit 2 respectively；
The output signal of the voltage detecting circuit 1 is converted into square wave by the hysteresis comparator circuit 2；The voltage shaping circuit 3
For eliminating the small sample perturbations in square wave, its output end is the output end of the electrification reset circuit.
The grounded-grid of the transistor MN2.
The voltage detecting circuit 1 controls reset level by adjusting transistor MP1 and transistor MN1 gate source voltage.
The transistor MN2 is the metal-oxide-semiconductor of N-channel depletion type MOS tube or negative threshold voltage；The transistor MP2 is P
Channel depletion type metal-oxide-semiconductor.
It should be noted that the transistor MN2 and transistor MP2 forms the biasing of the voltage detecting circuit 1.
Further, in power up, supply voltage VDD has conducting electric current when relatively low in the transistor MP2；Upper electricity
After the completion of, supply voltage VDD can complete switch off the transistor MP2, to realize without quiescent dissipation.
The utility model is by using the crystalline substance by depletion type or negative threshold voltage creatively in voltage detecting circuit 1
The body pipe MN2 and transistor MP2 of P-channel depletion type forms the biasing of voltage detecting circuit 1, can make to use the utility model
Electrification reset circuit in normal operation, quiescent current is less than 0.1nA, in engineer applied it is considered that in the absence of quiet
State power consumption.
The hysteresis comparator circuit 2 includes transistor MN3, transistor MN4, transistor MP3 and transistor MP4；
Further, the grid of the transistor MN3 and the drain electrode to drain with the transistor MN1 are connected；
The drain electrode of the transistor MP3 is connected with the source electrode of the transistor MN3, the source of source electrode and the transistor MP1
Pole connects；
The drain electrode of the transistor MP4 is connected with the drain electrode of the transistor MN3, the source of grid and the transistor MP3
Pole is connected, and source electrode is connected with the grid of the transistor MP3；
The drain electrode of the transistor MN4 is connected with the source electrode of the transistor MP4, the source of grid and the transistor MP3
Pole connects；
The drain electrode of the transistor MP4 and the drain electrode of the transistor MN4 and source electrode are electric with the voltage shaping respectively
Road 3 connects.
The hysteresis comparator circuit 2 adjusts electricity by adjusting the transistor MP3 and the transistor MN3 breadth length ratio
The hysteresis voltage on road.
The voltage shaping circuit 3 includes transistor MN5 and transistor MP5；
The drain electrode of the transistor MP5 is connected with the drain electrode of the transistor MP4, the leakage of grid and the transistor MN4
Pole connects；
The drain electrode of the transistor MN5 is connected with the source electrode of the transistor MP5, the grid of grid and the transistor MP5
Pole is connected, and source electrode is connected with the source electrode of the transistor MN4；
The drain electrode of the transistor MN5 is the output end of the electrification reset circuit.
The source ground of the transistor MN5.
The transistor MN5 is N-channel type metal-oxide-semiconductor, and the transistor MP5 is P-channel type metal-oxide-semiconductor.
It is made up of transistor MN3, transistor MN4, transistor MN5, transistor MP3, transistor MP4 and transistor MP5
Hysteresis comparator circuit 2 and voltage shaping circuit 3 are ensure that after electrification reset in the form of digital circuit without quiescent dissipation.
It is described above, only specific embodiment of the present utility model, but the scope of protection of the utility model is not limited to
In this, any one skilled in the art can readily occur in change in the technical scope that the utility model discloses
Or replace, it should all cover within the scope of protection of the utility model.Therefore, the scope of protection of the utility model should be with the power
The protection domain that profit requires is defined.
Claims (9)
- A kind of 1. electrification reset circuit of no quiescent dissipation, it is characterised in that：Including be sequentially connected electrically voltage detecting circuit, late Stagnant comparison circuit and voltage shaping circuit；The voltage detecting circuit includes transistor MN1, transistor MN2, transistor MP1 and transistor MP2；The transistor MN1, the transistor MP1, the transistor MN2 and the transistor MP2 are sequentially connected in series, and the drain electrode of the latter transistor is with before The source electrode connection of one transistor；The drain and gate of the transistor MN1 is connected with power end；The grid of the transistor MP1 and the transistor MN2 grid connection；The source ground of the transistor MP2, grid are connected with power end；The drain electrode of the transistor MN1 and the source electrode of the transistor MP1 are connected with the hysteresis comparator circuit respectively；It is described slow The output signal of the voltage detecting circuit is converted into square wave by stagnant comparison circuit；The voltage shaping circuit is used to eliminate square Small sample perturbations in shape ripple, its output end are the output end of the electrification reset circuit.
- A kind of 2. electrification reset circuit of no quiescent dissipation according to claim 1, it is characterised in that：The transistor MN2 grounded-grid.
- A kind of 3. electrification reset circuit of no quiescent dissipation according to claim 1, it is characterised in that：The voltage detecting Circuit controls reset level by adjusting transistor MP1 and transistor MN1 gate source voltage.
- A kind of 4. electrification reset circuit of no quiescent dissipation according to claim 1, it is characterised in that：The transistor MN2 is the metal-oxide-semiconductor of N-channel depletion type MOS tube or negative threshold voltage；The transistor MP2 is P-channel depletion type MOS tube.
- A kind of 5. electrification reset circuit of no quiescent dissipation according to any one of Claims 1-4, it is characterised in that：Institute Stating hysteresis comparator circuit includes transistor MN3, transistor MN4, transistor MP3 and transistor MP4；The grid of the transistor MN3 and the drain electrode to drain with the transistor MN1 are connected；The drain electrode of the transistor MP3 is connected with the source electrode of the transistor MN3, and the source electrode of source electrode and the transistor MP1 connects Connect；The drain electrode of the transistor MP4 is connected with the drain electrode of the transistor MN3, and the source electrode of grid and the transistor MP3 connects Connect, source electrode is connected with the grid of the transistor MP3；The drain electrode of the transistor MN4 is connected with the source electrode of the transistor MP4, and the source electrode of grid and the transistor MP3 connects Connect；The drain electrode of the transistor MP4 and the drain electrode of the transistor MN4 and source electrode connect with the voltage shaping circuit respectively Connect.
- A kind of 6. electrification reset circuit of no quiescent dissipation according to claim 5, it is characterised in that：The sluggishness is relatively Circuit adjusts the hysteresis voltage of circuit by adjusting the transistor MP3 and the transistor MN3 breadth length ratio.
- A kind of 7. electrification reset circuit of no quiescent dissipation according to claim 5, it is characterised in that：The voltage shaping Circuit includes transistor MN5 and transistor MP5；The drain electrode of the transistor MP5 is connected with the drain electrode of the transistor MP4, and the drain electrode of grid and the transistor MN4 connects Connect；The drain electrode of the transistor MN5 is connected with the source electrode of the transistor MP5, and the grid of grid and the transistor MP5 connects Connect, source electrode is connected with the source electrode of the transistor MN4；The drain electrode of the transistor MN5 is the output end of the electrification reset circuit.
- A kind of 8. electrification reset circuit of no quiescent dissipation according to claim 7, it is characterised in that：The transistor MN5 source ground.
- A kind of 9. electrification reset circuit of no quiescent dissipation according to claim 7, it is characterised in that：The transistor MN5 is N-channel type metal-oxide-semiconductor, and the transistor MP5 is P-channel type metal-oxide-semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720925464.2U CN207133762U (en) | 2017-07-27 | 2017-07-27 | A kind of electrification reset circuit of no quiescent dissipation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720925464.2U CN207133762U (en) | 2017-07-27 | 2017-07-27 | A kind of electrification reset circuit of no quiescent dissipation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207133762U true CN207133762U (en) | 2018-03-23 |
Family
ID=61639561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720925464.2U Withdrawn - After Issue CN207133762U (en) | 2017-07-27 | 2017-07-27 | A kind of electrification reset circuit of no quiescent dissipation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207133762U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107294516A (en) * | 2017-07-27 | 2017-10-24 | 上海毅栈半导体科技有限公司 | A kind of electrification reset circuit without quiescent dissipation |
| CN112117993A (en) * | 2020-09-18 | 2020-12-22 | 上海艾为电子技术股份有限公司 | Shaping circuit and oscillation circuit |
-
2017
- 2017-07-27 CN CN201720925464.2U patent/CN207133762U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107294516A (en) * | 2017-07-27 | 2017-10-24 | 上海毅栈半导体科技有限公司 | A kind of electrification reset circuit without quiescent dissipation |
| CN107294516B (en) * | 2017-07-27 | 2023-08-11 | 上海毅栈半导体科技有限公司 | Power-on reset circuit without static power consumption |
| CN112117993A (en) * | 2020-09-18 | 2020-12-22 | 上海艾为电子技术股份有限公司 | Shaping circuit and oscillation circuit |
| CN112117993B (en) * | 2020-09-18 | 2024-03-01 | 上海艾为电子技术股份有限公司 | Shaping circuit and oscillating circuit |
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Legal Events
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20180323 Effective date of abandoning: 20230811 |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20180323 Effective date of abandoning: 20230811 |