CN206977576U - Interface protection circuit for video receiving unit - Google Patents
Interface protection circuit for video receiving unit Download PDFInfo
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- CN206977576U CN206977576U CN201720963638.4U CN201720963638U CN206977576U CN 206977576 U CN206977576 U CN 206977576U CN 201720963638 U CN201720963638 U CN 201720963638U CN 206977576 U CN206977576 U CN 206977576U
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Abstract
The utility model discloses a kind of interface protection circuit for video receiving unit, belong to interfacing field.For in video transmitting element interface protection circuit, N to be connected to one end of pull-up resistor with external power source, N is connected one by one with the N of video transmitting element to output pin and the N of ESD circuit to input respectively to the other end of pull-up resistor；N is connected one by one to one end of pull down resistor and the N of video interface to input pin, and N is grounded to the other end of pull down resistor；N corresponds to pull-up resistor and N to pull down resistor, and for N to being in series with electric capacity between one end of the other end of each pair pull-up resistor in pull-up resistor and a pair of corresponding pull down resistors, the electric capacity is used for filtering low electric current and DC current.The utility model can fall the abnormal current on the signal wire between video transmitting element and video interface by N number of capacitive filter, avoid these abnormal currents from damaging video transmitting element.
Description
Technical Field
The utility model relates to an interface technical field especially relates to an interface protection circuit for video transceiver unit.
Background
With the rapid development of interface technology, various video interfaces are widely applied to audio and video products, such as HDMI (High definition multimedia interface), DVI (digital visual interface), and the like. In the use process of the video interface, static electricity, abnormal power failure, voltage difference between the grounding end of the video sending device and the grounding end of the video receiving device and the like all generate current to be coupled to a signal wire of the video interface. In order to protect the video transceiver unit connected to the video interface from being damaged by these currents, an interface protection circuit is often provided to protect the video transceiver unit.
At present, as shown in fig. 1, the interface protection circuit generally includes a plurality of resistors and an ESD (Electro-static discharge) circuit, one end of each of the plurality of resistors is connected to a plurality of pins of the video transceiver unit one by one, and the other end of each of the plurality of resistors is connected to a plurality of pins of the video interface and a plurality of input ends of the ESD circuit one by one. When abnormal current occurs on a signal wire between the video receiving and transmitting unit and the video interface, the ESD circuit can bypass the abnormal current, and meanwhile, the resistors can also play a role in limiting current, so that the video receiving and transmitting unit can be prevented from being damaged by the abnormal current.
However, the interface protection circuit is a DC (direct current) coupling circuit, in this case, since the ESD circuit can bypass the abnormal current only when the abnormal current is large, when the abnormal current is small, such as when the abnormal current is a low frequency current generated due to signal noise, a direct current generated due to a voltage difference between a ground terminal of the video transmitting apparatus and a ground terminal of the video receiving apparatus, and the like, the ESD circuit cannot bypass the small abnormal current, and thus the small abnormal current continues to exist on a signal line between the video transmitting/receiving unit and the video interface, thereby damaging the video transmitting/receiving unit.
SUMMERY OF THE UTILITY MODEL
In order to solve the problem that the video receiving and dispatching unit is damaged by abnormal current in the related art, the utility model provides an interface protection circuit for video sending unit and an interface protection circuit for video receiving unit. The technical scheme is as follows:
in one aspect, an interface protection circuit for a video transmitting unit is provided, the interface protection circuit comprising: the ESD protection circuit comprises N pairs of pull-up resistors, N pairs of pull-down resistors, N capacitors and an ESD circuit, wherein N is a positive integer;
one end of each of the N pairs of pull-up resistors is connected with an external power supply, the other end of each of the N pairs of pull-up resistors is respectively connected with N pairs of output pins of the video sending unit and N pairs of input ends of the ESD circuit one by one, and the video sending unit sends video signals through a video interface;
one ends of the N pairs of pull-down resistors are connected with the N pairs of input pins of the video interface one by one, and the other ends of the N pairs of pull-down resistors are grounded;
the N pairs of pull-up resistors correspond to the N pairs of pull-down resistors one by one, capacitors are connected in series between the other end of each pair of pull-up resistors in the N pairs of pull-up resistors and one end of the corresponding pair of pull-down resistors, and the capacitors are used for filtering low-frequency current and direct current.
Optionally, the interface guard circuit comprises a switch;
one end of the switch is connected with the other ends of the N pairs of pull-down resistors respectively, and the other end of the switch is grounded.
Optionally, the switch comprises a PMOS (Positive channel Metal Oxide Semiconductor) transistor;
the source electrode of the PMOS tube is respectively connected with the other ends of the N pairs of pull-down resistors, the grid electrode of the PMOS tube is connected with the control unit, and the drain electrode of the PMOS tube is grounded.
Optionally, the switch comprises an NMOS (Negative channel-Metal-Oxide-Semiconductor) transistor;
the drain electrode of the NMOS tube is respectively connected with the other ends of the N pairs of pull-down resistors, the grid electrode of the NMOS tube is connected with the control unit, and the source electrode of the NMOS tube is grounded.
Optionally, the video interface is HDMI or DVI.
Optionally, the N pairs of output pins of the video transmission unit are used to output TMDS (Transition minimized differential Signaling).
In another aspect, an interface protection circuit for a video receiving unit is provided, where the interface protection circuit includes: the ESD protection circuit comprises N pairs of pull-up resistors, N pairs of pull-down resistors, N capacitors and an ESD circuit, wherein N is a positive integer;
one ends of the N pairs of pull-up resistors are connected with an external power supply, the other ends of the N pairs of pull-up resistors are connected with N pairs of output pins of a video interface one by one, and the video receiving unit receives video signals through the video interface;
one ends of the N pairs of pull-down resistors are respectively connected with N pairs of input pins of the video receiving unit and N pairs of input ends of the ESD circuit one by one, and the other ends of the N pairs of pull-down resistors are grounded;
the N pairs of pull-up resistors correspond to the N pairs of pull-down resistors one by one, capacitors are connected in series between the other end of each pair of pull-up resistors in the N pairs of pull-up resistors and one end of the corresponding pair of pull-down resistors, and the capacitors are used for filtering low-frequency current and direct current.
Optionally, the interface guard circuit comprises a switch;
one end of the switch is connected with the other ends of the N pairs of pull-down resistors respectively, and the other end of the switch is grounded.
Optionally, the switch comprises a PMOS transistor;
the source electrode of the PMOS tube is respectively connected with the other ends of the N pairs of pull-down resistors, the grid electrode of the PMOS tube is connected with the control unit, and the drain electrode of the PMOS tube is grounded.
Optionally, the switch comprises an NMOS transistor;
the drain electrode of the NMOS tube is respectively connected with the other ends of the N pairs of pull-down resistors, the grid electrode of the NMOS tube is connected with the control unit, and the source electrode of the NMOS tube is grounded.
Optionally, the video interface is HDMI or DVI.
Optionally, the N pairs of input pins of the video receiving unit are used for inputting a TMDS.
The utility model provides a technical scheme's beneficial effect is: the interface protection circuit for the video transmitting unit is an AC (alternating current) coupling circuit and comprises N pairs of pull-up resistors, N pairs of pull-down resistors, N capacitors and an ESD circuit. In this case, since a video signal is generally transmitted on a signal line between the video transmitting unit and the video interface, and the video signal is generally an alternating current of a high frequency, both a low-frequency current and a direct current appearing on the signal line are generally abnormal currents. And because N electric capacity sets up between video sending unit and video interface, and N electric capacity C can filter low frequency current and direct current, consequently, when low frequency current or direct current appear on this signal line, N electric capacity can filter these low frequency current or direct current to the realization is to the filtering of the abnormal current on this signal line, and then can effectively avoid these abnormal current to cause the damage to video sending unit.
Drawings
Fig. 1 is a schematic structural diagram of an interface protection circuit provided in the prior art;
fig. 2 is a schematic structural diagram of a first interface protection circuit for a video sending unit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a second interface protection circuit for a video sending unit according to an embodiment of the present invention;
fig. 4A is a schematic structural diagram of a third interface protection circuit for a video transmitting unit according to an embodiment of the present invention;
fig. 4B is a schematic structural diagram of a fourth interface protection circuit for a video sending unit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a first interface protection circuit for a video receiving unit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a second interface protection circuit for a video receiving unit according to an embodiment of the present invention;
fig. 7A is a schematic structural diagram of a third interface protection circuit for a video receiving unit according to an embodiment of the present invention;
fig. 7B is a schematic structural diagram of a fourth interface protection circuit for a video receiving unit according to an embodiment of the present invention.
Reference numerals:
1: a video transmitting unit; 1 a: an output pin of the video sending unit;
2: a video receiving unit; 2 a: an input pin of the video receiving unit;
3: an ESD circuit; 3 a: an input of an ESD circuit;
4: a video interface; 4 a: an input pin of the video interface; 4 b: an output pin of the video interface;
5: a switch; 5 a: one end of a switch; 5 b: the other end of the switch; q1: a PMOS tube; s 1: a source electrode of the PMOS tube; g 1: a grid electrode of the PMOS tube; d 1: a drain electrode of the PMOS tube; q2: an NMOS tube; s 2: a source electrode of the NMOS tube; g 2: a grid electrode of the NMOS tube; d 2: a drain electrode of the NMOS tube;
r1: a pull-up resistor; r2: a pull-down resistor; c: a capacitor; 6: a control unit.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
Fig. 2 is an interface protection circuit for a video sending unit according to an embodiment of the present invention. Referring to fig. 2, the interface guard circuit includes: n pairs of pull-up resistors R1, N pairs of pull-down resistors R2, N capacitors C and an ESD circuit 3, wherein N is a positive integer;
one end of each of the N pairs of pull-up resistors R1 is connected to an external power supply, the other end of each of the N pairs of pull-up resistors R1 is connected to the N pairs of output pins 1a of the video transmitting unit 1 and the N pairs of input terminals 3a of the ESD circuit 3, one to one, and the video transmitting unit 1 transmits a video signal through the video interface 4;
one ends of the N pairs of pull-down resistors R2 are connected to the N pairs of input pins 4a of the video interface 4 one by one, and the other ends of the N pairs of pull-down resistors R2 are all grounded;
the N pairs of pull-up resistors R1 are in one-to-one correspondence with the N pairs of pull-down resistors R2, a capacitor C is connected in series between the other end of each pair of pull-up resistors R1 in the N pairs of pull-up resistors R1 and one end of the corresponding pair of pull-down resistors R2, and the capacitor C is used for filtering low-frequency current and direct current.
It should be noted that the external power source is used to provide a preset voltage, and the preset voltage may be preset, for example, the preset voltage may be 3.3 volts.
In addition, the video interface 4 may be an interface for transmitting a video signal, for example, the video interface 4 may be HDMI, DVI, or the like. The N pairs of output pins 1a of the video transmitting unit 1 are used to output a video signal, which may be TMDS or the like.
The embodiment of the utility model provides an interface protection circuit is AC coupling circuit, under this condition, because the video signal that transmits on the signal line between video transmission unit 1 and video interface 4, and video signal is the alternating current of high frequency generally, so low frequency current and direct current that appear on this signal line are abnormal current generally, if the low frequency current that produces because of signal noise, the direct current that produces because of the voltage difference between the earthing terminal of video transmission equipment and the earthing terminal of video receiving equipment etc. are abnormal current. Because N electric capacity C is used for filtering low frequency current and direct current, consequently, when low frequency current or direct current appear on this signal line, N electric capacity C can filter these low frequency current or direct current to the realization is to the filtering of the abnormal current on this signal line, and then can effectively avoid these abnormal current to cause the damage to video transmitting unit 1.
It should be noted that, for each of the N pairs of output pins 1a of the video transmitting unit 1, the video transmitting unit 1 generally outputs a video signal on the pair of output pins only when detecting that the pair of output pins is pulled up to a preset voltage. Since the N capacitors C filter the dc current, the video transmitting unit 1 cannot detect the pull-up voltage provided by the video receiving unit in the video receiving apparatus. Therefore, in order to guarantee that the N of video transmitting unit 1 can normally output video signal to output pin 1a, the embodiment of the utility model provides an increased N between video transmitting unit 1 and a N electric capacity C to pull up resistance R1, will make the N of video transmitting unit 1 all pull up to preset voltage to output pin 1a, N provides a suitable common mode voltage scope for video transmitting unit 1 to pull up resistance R1 this moment to can guarantee the normal output of video transmitting unit 1 to video signal.
In addition, because the video receiving unit can only receive the video signal in the appointed voltage range generally, consequently, in order to guarantee that the video receiving unit can normally receive video signal, the embodiment of the utility model provides an N has increased N to pull-down resistance R2 between N electric capacity C and video interface 4 to the video signal with N electric capacity C output pulls down in the appointed voltage range, thereby makes the video signal of video interface 4 transmission be located the appointed voltage range, and N provides a suitable common mode voltage range for the video receiving unit to pull-down resistance R2 this moment, thereby can guarantee that the video signal of video interface 4 transmission can be normally received by the video receiving unit.
Furthermore, the ESD circuit 3 is disposed between the video sending unit 1 and the N capacitors C, so that when an excessive abnormal current (such as a surge current) occurs at the video interface 4, the excessive abnormal current is filtered by the N capacitors C, and then the filtered abnormal current is bypassed by the ESD circuit 3, thereby effectively preventing the video sending unit 1 from being damaged by the excessive abnormal current, and also effectively preventing the ESD circuit 3 from being damaged by the excessive abnormal current.
Referring to fig. 3, the interface protection circuit includes a switch 5;
one end 5a of the switch 5 is connected to the other ends of the N pairs of pull-down resistors R2, and the other end 5b of the switch 5 is grounded.
The switch 5 may be turned on when the video interface 4 is connected to the video receiving unit, so that the N pairs of pull-down resistors R2 may work normally to implement the pull-down function thereof; the switch 5 may be turned off when the video interface 4 is not connected to the video receiving unit, so that the N pairs of pull-down resistors R2 do not operate, thereby saving resources.
Referring to fig. 4A, the switch 5 includes a PMOS transistor Q1;
the source s1 of the PMOS transistor Q1 is connected to the other end of the N pair of pull-down resistors R2, the gate g1 of the PMOS transistor Q1 is connected to the control unit 6, and the drain d1 of the PMOS transistor Q1 is grounded.
When the control unit 6 detects that the video interface 4 is connected to the video receiving unit, the control unit 6 may output a low level to the gate g1 of the PMOS transistor Q1 to turn on the PMOS transistor Q1, and at this time, the N pairs of pull-down resistors R2 may work normally to implement the pull-down function thereof.
When the control unit 6 detects that the video interface 4 is not connected to the video receiving unit, the control unit 6 may output a high level to the gate g1 of the PMOS transistor Q1 to turn off the PMOS transistor Q1, and at this time, the N pair of pull-down resistors R2 does not work, so that resources may be saved.
Referring to fig. 4B, the switch 5 includes an NMOS transistor Q2;
the drain d2 of the NMOS transistor Q2 is connected to the other end of the N pair of pull-down resistors R2, the gate g2 of the NMOS transistor Q2 is connected to the control unit 6, and the source s2 of the NMOS transistor Q2 is grounded.
When the control unit 6 detects that the video interface 4 is connected to the video receiving unit, the control unit 6 may output a high level to the gate g2 of the NMOS transistor Q2 to turn on the NMOS transistor Q2, and at this time, the N pairs of pull-down resistors R2 may work normally to implement the pull-down function thereof.
When the control unit 6 detects that the video interface 4 is not connected to the video receiving unit, the control unit 6 may output a low level to the gate g2 of the NMOS transistor Q2 to turn off the NMOS transistor Q2, and at this time, the N pair of pull-down resistors R2 does not work, so that resources may be saved.
The embodiment of the utility model provides an in, an interface protection circuit for video sending unit is AC coupling circuit, and this interface protection circuit includes that N is to pull-up resistance, N to pull-down resistance, a N electric capacity and ESD circuit. In this case, since a video signal is transmitted on the signal line between the video transmitting unit and the video interface, and the video signal is generally an alternating current of a high frequency, both a low-frequency current and a direct current appearing on the signal line are generally abnormal currents. And because N electric capacity sets up between video sending unit and video interface, and N electric capacity C can filter low frequency current and direct current, consequently, when low frequency current or direct current appear on this signal line, N electric capacity can filter these low frequency current or direct current to the realization is to the filtering of the abnormal current on this signal line, and then can effectively avoid these abnormal current to cause the damage to video sending unit.
Fig. 5 is an interface protection circuit for a video receiving unit according to an embodiment of the present invention. Referring to fig. 5, the interface guard circuit includes: n pairs of pull-up resistors R1, N pairs of pull-down resistors R2, N capacitors C and an ESD circuit 3, wherein N is a positive integer;
one end of each of the N pairs of pull-up resistors R1 is connected to an external power supply, the other end of each of the N pairs of pull-up resistors R1 is connected to the N pairs of output pins 4b of the video interface 4 one by one, and the video receiving unit 2 receives a video signal through the video interface 4;
one ends of the N pairs of pull-down resistors R2 are respectively connected to the N pairs of input pins 2a of the video receiving unit 2 and the N pairs of input terminals 3a of the ESD circuit 3 one by one, and the other ends of the N pairs of pull-down resistors R2 are all grounded;
the N pairs of pull-up resistors R1 are in one-to-one correspondence with the N pairs of pull-down resistors R2, a capacitor C is connected in series between the other end of each pair of pull-up resistors R1 in the N pairs of pull-up resistors R1 and one end of the corresponding pair of pull-down resistors R2, and the capacitor C is used for filtering low-frequency current and direct current.
It should be noted that the external power source is used to provide a preset voltage, and the preset voltage may be preset, for example, the preset voltage may be 3.3 volts.
In addition, the video interface 4 may be an interface for transmitting a video signal, for example, the video interface 4 may be HDMI, DVI, or the like. The N pairs of input pins 2a of the video receiving unit 2 are used to input a video signal, which may be TMDS or the like.
The embodiment of the utility model provides an interface protection circuit is AC coupling circuit, under this condition, because the video signal that transmits on the signal line between video interface 4 and the video receiving unit 2, and video signal is the alternating current of high frequency generally, so low frequency current and direct current that appear on this signal line are abnormal current generally, if the low frequency current that produces because of signal noise, the direct current that produces because of the voltage difference between the earthing terminal of video sending equipment and video receiving equipment etc. are abnormal current. Because N electric capacity C is used for filtering low frequency current and direct current, consequently, when low frequency current or direct current appear on this signal line, N electric capacity C can filter these low frequency current or direct current to the realization is to the filtration of the abnormal current on this signal line, and then can effectively avoid these abnormal current to cause the damage to video receiving element 2.
It should be noted that, for each pair of output pins in the N pairs of output pins 4b of the video interface 4, the video sending unit in the video sending apparatus generally outputs the video signal on the pair of output pins only when detecting that the pair of output pins is pulled up to the preset voltage. Since the N capacitors C filter the dc current, the video transmitter unit cannot detect the pull-up voltage provided by the video receiver unit 2. Therefore, in order to guarantee that video interface 4's N can normally output video signal to output pin 4b, the embodiment of the utility model provides an increased N between video interface 4 and N electric capacity C to pull up resistance R1, will make video interface 4's N all pull up to preset voltage to output pin 4b, N provides a suitable common mode voltage scope for the video transmitting unit to pull up resistance R1 this moment to can guarantee that the video transmitting unit can normally output video signal on video interface 4.
In addition, because video receiving element 2 can only receive the video signal in the appointed voltage range generally, consequently, in order to guarantee that video receiving element 2 can normally receive video signal, the embodiment of the utility model provides an N to pull-down resistance R2 has been increased between N electric capacity C and video receiving element 2 to the video signal with N electric capacity C input is pulled down in the appointed voltage range, thereby makes the video signal of N electric capacity C input be located the appointed voltage range, and N provides a suitable common mode voltage range for video receiving element 2 to pull-down resistance R2 this moment, thereby can guarantee video receiving element 2 to the normal receipt of video signal.
Furthermore, the ESD circuit 3 is disposed between the N capacitors C and the video receiving unit 2, when an excessive abnormal current (such as a surge current) occurs at the video interface 4, the excessive abnormal current is filtered by the N capacitors C, and then the filtered abnormal current is bypassed by the ESD circuit 3, so that the ESD circuit 3 can be effectively prevented from being damaged by the excessive abnormal current while the video receiving unit 2 is effectively prevented from being damaged by the excessive abnormal current.
Referring to fig. 6, the interface protection circuit includes a switch 5;
one end 5a of the switch 5 is connected to the other ends of the N pairs of pull-down resistors R2, and the other end 5b of the switch 5 is grounded.
The switch 5 can be turned on when the video interface 4 is connected to the video sending unit, so that the N pairs of pull-down resistors R2 can work normally to realize the pull-down function; the switch 5 may be turned off when the video interface 4 is not connected to the video transmitting unit, so that the N pairs of pull-down resistors R2 do not operate, thereby saving resources.
Referring to fig. 7A, the switch 5 includes a PMOS transistor Q1;
the source s1 of the PMOS transistor Q1 is connected to the other end of the N pair of pull-down resistors R2, the gate g1 of the PMOS transistor Q1 is connected to the control unit 6, and the drain d1 of the PMOS transistor Q1 is grounded.
When the control unit 6 detects that the video interface 4 is connected to the video transmitting unit, the control unit 6 may output a low level to the gate g1 of the PMOS transistor Q1 to turn on the PMOS transistor Q1, and at this time, the N pairs of pull-down resistors R2 may work normally to implement the pull-down function thereof.
When the control unit 6 detects that the video interface 4 is not connected to the video transmitting unit, the control unit 6 may output a high level to the gate g1 of the PMOS transistor Q1 to turn off the PMOS transistor Q1, and at this time, the N pair of pull-down resistors R2 does not work, so that resources may be saved.
Referring to fig. 7B, the switch 5 includes an NMOS transistor Q2;
the drain d2 of the NMOS transistor Q2 is connected to the other end of the N pair of pull-down resistors R2, the gate g2 of the NMOS transistor Q2 is connected to the control unit 6, and the source s2 of the NMOS transistor Q2 is grounded.
When the control unit 6 detects that the video interface 4 is connected to the video transmitting unit, the control unit 6 may output a high level to the gate g2 of the NMOS transistor Q2 to turn on the NMOS transistor Q2, and at this time, the N pairs of pull-down resistors R2 may work normally to implement the pull-down function thereof.
When the control unit 6 detects that the video interface 4 is not connected to the video transmitting unit, the control unit 6 may output a low level to the gate g2 of the NMOS transistor Q2 to turn off the NMOS transistor Q2, and at this time, the N pair of pull-down resistors R2 does not work, so that resources may be saved.
The embodiment of the utility model provides an in, an interface protection circuit for video receiving unit is AC coupling circuit, and this interface protection circuit includes that N is to pull-up resistance, N to pull-down resistance, a N electric capacity and ESD circuit. In this case, since a video signal is transmitted on the signal line between the video interface and the video receiving unit, and the video signal is generally an alternating current of a high frequency, both a low-frequency current and a direct current appearing on the signal line are generally abnormal currents. And because N electric capacity sets up between video interface and video receiving element, and N electric capacity can filter low frequency current and direct current, consequently, when low frequency current or direct current appear on this signal line, N electric capacity can filter these low frequency current or direct current to the realization is to the filtering of the abnormal current on this signal line, and then can effectively avoid these abnormal current to cause the damage to video receiving element.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the present invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included within the protection scope of the present invention.
Claims (10)
1. An interface guard circuit for a video transmission unit, the interface guard circuit comprising: the ESD protection circuit comprises N pairs of pull-up resistors, N pairs of pull-down resistors, N capacitors and an electrostatic discharge (ESD) circuit, wherein N is a positive integer;
one end of each of the N pairs of pull-up resistors is connected with an external power supply, the other end of each of the N pairs of pull-up resistors is respectively connected with N pairs of output pins of the video sending unit and N pairs of input ends of the ESD circuit one by one, and the video sending unit sends video signals through a video interface;
one ends of the N pairs of pull-down resistors are connected with the N pairs of input pins of the video interface one by one, and the other ends of the N pairs of pull-down resistors are grounded;
the N pairs of pull-up resistors correspond to the N pairs of pull-down resistors one by one, capacitors are connected in series between the other end of each pair of pull-up resistors in the N pairs of pull-up resistors and one end of the corresponding pair of pull-down resistors, and the capacitors are used for filtering low-frequency current and direct current.
2. The interface protection circuit of claim 1, wherein the interface protection circuit comprises a switch;
one end of the switch is connected with the other ends of the N pairs of pull-down resistors respectively, and the other end of the switch is grounded.
3. The interface protection circuit of claim 2, wherein the switch comprises a positive channel metal oxide semiconductor (PMOS) transistor, sources of the PMOS transistors are respectively connected with the other ends of the N pairs of pull-down resistors, a gate of the PMOS transistor is connected with the control unit, and a drain of the PMOS transistor is grounded; or,
the switch comprises a negative channel metal oxide semiconductor (NMOS) tube, the drain electrode of the NMOS tube is respectively connected with the other ends of the N pairs of pull-down resistors, the grid electrode of the NMOS tube is connected with the control unit, and the source electrode of the NMOS tube is grounded.
4. The interface guard circuit of any one of claims 1-3, wherein the video interface is a High Definition Multimedia Interface (HDMI) or a Digital Video Interface (DVI).
5. The interface guarding circuit according to any one of claims 1 to 3, wherein the N pairs of output pins of the video transmitting unit are used to output a Transition Minimized Differential Signaling (TMDS).
6. An interface guard circuit for a video receiving unit, the interface guard circuit comprising: the ESD protection circuit comprises N pairs of pull-up resistors, N pairs of pull-down resistors, N capacitors and an electrostatic discharge (ESD) circuit, wherein N is a positive integer;
one ends of the N pairs of pull-up resistors are connected with an external power supply, the other ends of the N pairs of pull-up resistors are connected with N pairs of output pins of a video interface one by one, and the video receiving unit receives video signals through the video interface;
one ends of the N pairs of pull-down resistors are respectively connected with N pairs of input pins of the video receiving unit and N pairs of input ends of the ESD circuit one by one, and the other ends of the N pairs of pull-down resistors are grounded;
the N pairs of pull-up resistors correspond to the N pairs of pull-down resistors one by one, capacitors are connected in series between the other end of each pair of pull-up resistors in the N pairs of pull-up resistors and one end of the corresponding pair of pull-down resistors, and the capacitors are used for filtering low-frequency current and direct current.
7. The interface guard circuit of claim 6, wherein the interface guard circuit comprises a switch;
one end of the switch is connected with the other ends of the N pairs of pull-down resistors respectively, and the other end of the switch is grounded.
8. The interface protection circuit of claim 7, wherein the switch comprises a positive channel metal oxide semiconductor (PMOS) transistor, sources of the PMOS transistors are respectively connected to the other ends of the N pairs of pull-down resistors, a gate of the PMOS transistor is connected to the control unit, and a drain of the PMOS transistor is grounded; or,
the switch comprises a negative channel metal oxide semiconductor (NMOS) tube, the drain electrode of the NMOS tube is respectively connected with the other ends of the N pairs of pull-down resistors, the grid electrode of the NMOS tube is connected with the control unit, and the source electrode of the NMOS tube is grounded.
9. The interface guard circuit of any one of claims 6-8, wherein the video interface is a High Definition Multimedia Interface (HDMI) or a Digital Video Interface (DVI).
10. The video output interface according to any of claims 6 to 8, wherein the N pairs of input pins of the video receiving unit are used for inputting Transition Minimized Differential Signaling (TMDS).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720963638.4U CN206977576U (en) | 2017-08-03 | 2017-08-03 | Interface protection circuit for video receiving unit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720963638.4U CN206977576U (en) | 2017-08-03 | 2017-08-03 | Interface protection circuit for video receiving unit |
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| Publication Number | Publication Date |
|---|---|
| CN206977576U true CN206977576U (en) | 2018-02-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720963638.4U Active CN206977576U (en) | 2017-08-03 | 2017-08-03 | Interface protection circuit for video receiving unit |
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| Country | Link |
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| CN (1) | CN206977576U (en) |
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