CN206976354U - Suitable for the power semiconductor device structure of deep trench - Google Patents

Abstract

It the utility model is related to a kind of power semiconductor device structure suitable for deep trench, it is characterised in that：On the section of semiconductor devices, the first conduction type drift region surface in terminal protection area is provided with second the second well region of conduction type, several Second Type grooves are provided with second the second well region of conduction type, and the center in Second Type groove is filled with the second class electric conductor and the second class dielectric positioned at the second class electric conductor outer ring, second class electric conductor electrically connects with outer second the second well region of conduction type close to terminal transition region side of place Second Type groove, first kind groove in terminal transition region below the Second Type groove in terminal protection area with being equipped with the well region of the second conduction type the 3rd；The utility model structure can effectively improve the high pressure resistant property of device, and manufacture craft is compatible with existing semiconductor technology, wide adaptation range, saves production cost.

Description

Suitable for the power semiconductor device structure of deep trench

Technical field

It the utility model is related to a kind of power semiconductor, especially a kind of power semiconductor device suitable for deep trench Part, belong to the manufacturing technology field of semiconductor devices.

Background technology

Regulator and requirement more and more higher of the terminal client to DC-DC power source efficiency, power semiconductor is new to be set Meter requires lower conduction impedance, while can not influence non-clamper perception switch（UIS）Ability is increased without switching loss.

DC-DC power source designer is faced with the challenge for improving efficiency and power density, conduction impedance always（Rds-on） And gate charge（Qg）It is two key parameters of power semiconductor, typically always one reduces then another increase, therefore Power MOSFET designs personnel must account for balance therebetween, and the continuous progress of Power MOSFET technologies helps them It is able to alleviate this contradiction.Shield grid power MOSFET belongs to one kind of deep-groove power device, can accomplish to reduce conducting resistance It is anti-, gate charge is not influenceed but.This technology allow Power Management Design personnel efficiency and power density can be brought up to one it is new It is horizontal.

The drift doping concentration of shield grid power MOSFET in deep slot power semiconductor device is higher, has relatively low Resistivity, make its on state resistance（Conduction impedance（Rds-on））It is smaller, but this advantage can become inferior position in some aspects.It is first First, groove exhausts caused transverse electric field from the active area of device to becoming irregular during the transition of termination environment, reduces device Reliability；Secondly as the Electric Field Distribution in terminal protection area is longitudinal so that the breakdown potential in terminal protection area is lower than active area A lot.Therefore, the Terminal Design of deep groove device increases considerably compared to general power device difficulty.

The content of the invention

The purpose of this utility model is to overcome the deficiencies in the prior art, it is proposed that one kind is applied to deep-groove power The semiconductor structure and manufacture method of device, by setting first kind groove, the second class in terminal transition region and terminal protection area Groove and the well region of the second conduction type the 3rd, the terminal peak electric field of deep trench shielding gate power MOSFET device, energy can be reduced The high pressure resistant property of device is effectively improved, and the device making method is compatible with existing semiconductor technology, manufacturing cost is low, adapts to Scope is wide, securely and reliably.

To realize above technical purpose, the technical solution of the utility model is：Suitable for the power semiconductor device of deep trench Part structure, in the top plan view of the semiconductor devices, including active area on semiconductor substrate, terminal transition region with And terminal protection area, the active area are located at the center of semiconductor substrate, terminal transition region is located at the outer ring of active area and ring Around the active area is surrounded, terminal protection area is located at the outer ring of terminal transition zone and around the encirclement terminal transition region；Institute State on the section of semiconductor devices, semiconductor substrate has two corresponding interareas, two interareas include the first interarea and Second interarea corresponding with the first interarea, the first conduction type is included between the first interarea and the second interarea of semiconductor substrate and is floated Area and the first conductivity type substrate are moved, first conductivity type substrate is located at the lower section of the first conduction type drift region and neighbour Connect, first interarea is the upper surface of the first conduction type drift region, and second interarea is the first conductivity type substrate Lower surface, drain metal, the drain metal and the first conductivity type substrate Ohmic contact are set on the second interarea；Described On the section of semiconductor devices, the first conduction type drift region surface of active area is provided with second the first well region of conduction type, institute State and several first kind grooves are provided with second the first well region of conduction type, the first kind groove is from the second conduction type The direction that the second interarea is pointed on the surface of first well region along the first interarea is extended in the first conduction type drift region, and first Center in type groove is filled with first kind electric conductor and the first kind medium positioned at the first kind electric conductor outer ring Body, the top in the first kind groove are provided around the internal channel of first kind electric conductor, in the side wall of the internal channel Provided with insulation gate oxide, and Gate Electrode Conductive polysilicon is filled with internal channel, on the surface of second the first well region of conduction type Provided with the first conduction type source area, the outer wall of the first conduction type source area and first kind groove abuts, active It is provided with source metal above first interarea of the semiconductor substrate in area, the source metal and the first conduction type source area, the Two conduction type the first well region Ohmic contacts, and source metal electrically connects with first kind electric conductor, several yuan in active area Born of the same parents are in parallel in overall by Gate Electrode Conductive polysilicon；On the section of the semiconductor devices, the first of terminal transition region is conductive Type drift region surface is provided with second the second well region of conduction type, and the first kind is provided with the well region of the second conduction type second Groove, the first kind groove point to the side of the second interarea from the surface of second the second well region of conduction type along the first interarea To extending in the first conduction type drift region, and the center in first kind groove is filled with first kind electric conductor and position First kind dielectric in the first kind electric conductor outer ring, the top in the first kind groove are provided around the first kind The internal channel of electric conductor, the side wall of the internal channel are provided with insulation gate oxide, and more filled with Gate Electrode Conductive in internal channel Crystal silicon, source metal, the source metal and second are provided with above the first interarea of the semiconductor substrate in terminal transition region Conduction type the second well region Ohmic contact, and electrically connected with first kind electric conductor, several cellulars in terminal transition region pass through Gate Electrode Conductive polysilicon is in parallel in overall, it is characterised in that：The lower section of first kind groove in terminal transition region is provided with second The well region of conduction type the 3rd, the well region of the second conduction type the 3rd coat the groove of the first kind groove in terminal transition region Bottom；On the section of the semiconductor devices, the first conduction type drift region surface in terminal protection area is provided with the second conductive-type The well region of type second, the well region of the second conduction type second is interior to be provided with several Second Type grooves, the Second Type groove The direction that the second interarea is pointed to from the surface of second the second well region of conduction type along the first interarea extends to the first conduction type In drift region, and the center in Second Type groove is filled with the second class electric conductor and outside the second class electric conductor Second class dielectric of circle, the second class electric conductor are outer close to the second of terminal transition region side with place Second Type groove The well region of conduction type second electrically connects.

Further, the first kind groove and Second Type groove are same technique manufactures layer, the phase in active area Spacing between adjacent first kind groove is identical；The spacing of adjacent first type groove in terminal transition region can with active area Spacing between adjacent first type groove is identical or different；Distance in terminal protection area between adjacent Second Type groove it is identical or The direction that terminal protection area is pointed to along active area gradually increases.

Further, the groove opening width of the first kind groove in terminal transition region can be with first in active area The groove opening width of type groove is identical or different.

Further, the both sides of the first kind electric conductor in the first kind groove in terminal transition region can be not provided with Gate Electrode Conductive polysilicon can set Gate Electrode Conductive polysilicon or both sides all to set Gate Electrode Conductive polysilicon, and terminal in side Gate Electrode Conductive polysilicon in transition region can connect gate metal or floating.

Further, second the second well region of conduction type in terminal transition region can be by second the first trap of conduction type Area substitutes.

Further, for N-type semiconductor device, the first conduction type is that N-type is conductive, and the second conduction type is led for p-type Electricity；For P-type semiconductor device, the first conduction type is P-type conduction, and the second conduction type is that N-type is conductive.

In order to further realize above technical purpose, the utility model also proposes that a kind of power suitable for deep trench is partly led The manufacture method of body device architecture, it is characterized in that, comprise the following steps：

Step 1 provides semiconductor substrate, and the semiconductor substrate includes the first conductivity type substrate and is grown in the The first conduction type drift region in one conductivity type substrate, the upper surface of the first conduction type drift region is the first master Face, the lower surface of first conductivity type substrate is the second interarea；

Step 2 sets hard mask layer on the first interarea of semiconductor substrate, optionally shelters and etch hard mask Layer, form the mask layer window of insertion hard mask layer；

Step 3 is carried out etching groove to the first interarea of semiconductor substrate, had by the masking of mask layer window For source region with forming first kind groove in the first conduction type drift region of terminal transition region, first in terminal protection area is conductive Second Type groove is formed in type drift region；

Step 4 removes the mask layer window on the first interarea, the Selective implantation on the first interarea of semiconductor substrate Second conductive type impurity ion, and trap is pushed away, it is respectively formed second the second trap of conduction type in terminal transition region and terminal protection area Area and the well region of the second conduction type the 3rd；

Step 5 carries out dielectric filling in first kind groove and Second Type groove, in first kind groove Interior formation first kind dielectric and the first kind electric conductor filling hole, forms the second class dielectric and second in Second Type groove Class electric conductor fills hole；

Step 6 fills the filling that electric conductor is carried out in hole and the second class electric conductor filling hole in first kind electric conductor, First kind electric conductor is formed in first kind groove, the second class electric conductor is formed in Second Type groove；

Step 7 performs etching to the first kind dielectric in first kind groove, the top in first kind groove Form internal channel；

Step 8 deposits insulation gate oxide in internal channel, and deposit grid is led in the groove that insulation gate oxide is formed Electric polysilicon；

Step 9 is selectively implanted the second conductive type impurity ion and pushed away on the first interarea of semiconductor substrate Trap, second the first well region of conduction type is formed in active area；

Step 10 is selectively implanted the first conductive type impurity ion on the first interarea of semiconductor substrate, is having The first conduction type source area is formed in second the first well region of conduction type of source region；

Step 11 deposits insulating medium layer on the first interarea of semiconductor substrate, and the insulating medium layer is entered Row contact hole etching；

Step 12 deposited metals in the contact hole on the first interarea of semiconductor substrate, enter to the metal level Row etched features, source metal, gate metal and terminal connection metal are formed on the interarea of semiconductor substrate first；

Step 13 sets drain metal, the drain metal and the first conduction on the second interarea of semiconductor substrate Type substrates Ohmic contact.

Compared with conventional power semiconductors device, the utility model has advantages below：

1）By the second class electric conductor in Second Type groove in terminal protection area with it is close outside the Second Type groove of place The well region of p-type second of terminal transition region side is electrical, makes the second class electric conductor in Second Type groove and adjacent terminals transition Type the second well region equipotential of area side, the potential of the second class electric conductor are formed less than the N-type drift region of the second class groove periphery Certain electrical potential difference, the horizontal depletion degree of enhancing Second Type groove periphery N-type drift region, improves device voltage endurance capability；

2）The well region of Second Type channel bottom implanting p-type the 3rd in terminal protection area so that two neighboring Second Type Depletion layer caused by below channel bottom is connected in the horizontal direction, reduces the curvature of terminal protection area depletion layer, effectively subtracts Delay terminal transition region to concentrate to the electric field during transition of terminal protection area, the breakdown characteristics of device significantly improve；

3）When three well region of p-type is set in terminal transition region, the N-type drift region of first kind channel bottom is not only with the A kind of electric conductor is exhausted, and is also exhausted with the well region of p-type the 3rd so that first kind channel bottom in terminal transition region Electric field intensity is substantially suppressed so that the breakdown characteristics of device significantly improve.

Brief description of the drawings

Fig. 1 is cross section structure diagram of the present utility model.

Fig. 2 is the cross section structure diagram of the utility model semiconductor substrate.

Fig. 3 is that the utility model obtains the cross section structure diagram after first kind groove, Second Type groove.

Fig. 4 is that the utility model obtains the cross section structure diagram after the well region of p-type second, the well region of p-type the 3rd.

Fig. 5 is that the utility model obtains the cross section structure diagram after first kind dielectric, the second class dielectric.

Fig. 6 is that the utility model obtains the cross section structure diagram after first kind electric conductor, the second class electric conductor.

Fig. 7 is that the utility model obtains the cross section structure diagram after internal channel.

Fig. 8 is that the utility model obtains the cross section structure diagram after Gate Electrode Conductive polysilicon.

Fig. 9 is that the utility model obtains the cross section structure diagram after the well region of p-type first.

Figure 10 is that the utility model obtains the cross section structure diagram after N-type source region.

Figure 11 is that the utility model obtains the cross section structure diagram after source metal.

Description of reference numerals：The conductivity type substrates of 1- first, the first conduction types of 2- drift region, 3- first kind groove, 4- first kind dielectric, 5- first kind electric conductor, 6- Gate Electrode Conductives polysilicon, 7- insulation gate oxide, the conduction types of 8- second First well region, the first conduction types of 9- source area, the well region of the second conduction types of 10- the 3rd, 11- source metals, the classes of 12- second Type groove, the second classes of 13- dielectric, the second classes of 14- electric conductor, the second well region of the second conduction types of 15-, 16- drain metals, 17- first kind electric conductor filling hole, the second classes of 18- electric conductor filling hole, 19- internal channels, 100- active areas, 200- terminal transition Area, 300- terminal protections area, the interareas of 001- first, the interareas of 002- second.

Embodiment

With reference to specific drawings and examples, the utility model is described in further detail.

As shown in figure 1, in order to effectively improve the high pressure resistant property of device, cost is reduced, improves accommodation, this practicality It is new to propose a kind of semiconductor structure and manufacture method suitable for deep groove device, with partly leading for N-type deep trench MOSFET Exemplified by shield grid power MOSFET in body device, in the top plan view of the semiconductor devices, including positioned at semiconductor-based Active area 100, terminal transition region 200 and terminal protection area 300 on plate, the active area 100 are located at semiconductor substrate Center, terminal transition region 200 are located at the outer ring of active area 100 and around the encirclement active area 100, terminal protection areas 300 Positioned at the outer ring of terminal transition region 200 and around the encirclement terminal transition region 200；

On the section of the semiconductor devices, semiconductor substrate has two corresponding interareas, and two interareas include First interarea 001 and second interarea 002 corresponding with the first interarea 001, the first interarea 001 and second of semiconductor substrate Include N-type drift region 2 and N-type substrate 1 between interarea 002, the N-type substrate 1 is located at the lower section of N-type drift region 2, and N-type substrate 1 Adjacent N-type drift region 2, first interarea 001 are the upper surface of N-type drift region 2, and second interarea 002 is N-type substrate 1 Lower surface, drain metal 16, the drain metal 16 and the Ohmic contact of N-type substrate 1 are set on the second interarea 002；

On the section of active area 100 of the semiconductor devices, N-type substrate 1 is provided with N-type drift region 2, N-type drift region 2 Surface is provided with the first well region of p-type 8, and first kind groove 3, the first kind are provided with the first well region of p-type 8 of active area 100 Groove 3 is located at the surface of the first well region of p-type 8, and depth is stretched into the N-type drift region 2 of the lower section of the first well region of p-type 8, the first kind Center in type groove 3 is filled with first kind electric conductor 5, and the outer ring of the first kind electric conductor 5 is enclosed with first kind Jie Plastid 4, the top in the first kind groove 3 are provided around the Gate Electrode Conductive polysilicon 6 of first kind electric conductor 5, the grid The outer ring of pole conductive polycrystalline silicon 6 is enclosed with insulation gate oxide 7, and two N-type source regions 9 are provided with the surface of the first well region of p-type 8, The N-type source region 9 is in contact with the outer wall of first kind groove 3, on the first interarea of the semiconductor substrate of active area 100 Side is provided with source metal 11, the source metal 11 and N-type source region 9, the Ohmic contact of the first well region of p-type 8, and is led with the first kind Electric body 5 electrically connects, and is separated between source metal 11 and Gate Electrode Conductive polysilicon 6 by insulating medium layer, some in active area 100 Individual cellular unit is in parallel in overall by Gate Electrode Conductive polysilicon 6；

On the section of terminal transition region 200 of the semiconductor devices, N-type substrate 1 is provided with N-type drift region 2, N-type drift Moving the surface of area 2 and be provided with the second well region of p-type 15, the second well region of p-type 15 in terminal transition region 200 is interior to be provided with first kind groove 3, The first kind groove 3 is located at the surface of the second well region of p-type 15, and depth stretches into the N-type drift of the lower section of the second well region of p-type 15 Move in area 2, the center in first kind groove 3 is filled with first kind electric conductor 5, and the outer ring of the first kind electric conductor 5 First kind dielectric 4 is enclosed with, the top in the first kind groove 3 is provided around the Gate Electrode Conductive of first kind electric conductor 5 Polysilicon 6, the outer ring of Gate Electrode Conductive polysilicon 6 are enclosed with insulation gate oxide 7, the first kind in terminal transition region 200 The lower section of the bottom land of groove 3 is provided with the well region 10 of p-type the 3rd, and the area of the 3rd trap of p-type 10 coats the first kind in terminal transition region 200 The bottom land of type groove 3, source metal 11 is provided with above the first interarea of the semiconductor substrate in terminal transition region 200, it is described Source metal 11 and the Ohmic contact of the second well region of p-type 15, several cellular units in terminal transition region 200 pass through Gate Electrode Conductive Polysilicon 6 is in parallel in overall：

On the section of terminal protection area 300 of the semiconductor devices, N-type substrate 1 is provided with N-type drift region 2, the N The surface of type drift region 2 is provided with the second well region of p-type 15, is provided with some Second Type grooves 12 in terminal protection area 300, and described second Type groove 12 is located in the second well region of p-type 15, and depth is stretched into the N-type drift region 2 of the lower section of the second well region of p-type 15；Second class Center in type groove 12 is filled with the second class electric conductor 14, and the outer ring of the second class electric conductor 1 is enclosed with the second class Dielectric 13, the p-type of the second class electric conductor 14 and the outer side of adjacent terminals transition region 200 of place Second Type groove 12 the Two well regions 15 electrically connect；The well region 10 of p-type the 3rd, the trap of p-type the 3rd are provided with the lower section of the bottom land of Second Type groove 12 Area 10 coats the bottom land of Second Type groove 12；, can be the of the top of Second Type groove 12 in the terminal protection area 300 The both sides of two class electric conductors 14 or side set Gate Electrode Conductive polysilicon 6, can also both sides be all not provided with Gate Electrode Conductive polycrystalline Silicon 6, the Gate Electrode Conductive polysilicon 6 and the second class in P drift area 2, the second well region of p-type 15 and Second Type groove 12 Electric conductor 14 insulate, the floating of Gate Electrode Conductive polysilicon 6；

The first kind groove 3, Second Type groove 12 are same technique manufactures layer, adjacent in active area 100 Spacing between one type groove 3 is identical；The spacing between adjacent first type groove 3 in terminal transition region 200 can with it is active The spacing between adjacent first type groove 3 in area 100 is identical, can also differ；Adjacent second class in terminal protection area 300 Distance between type groove 12 is identical or gradually increases along the direction in the sensing terminal protection of active area 100 area 300, and the first kind is situated between The class dielectric 13 of plastid 4 and second is same technique manufactures layer, first kind groove 3 and institute in the terminal transition region 200 The groove opening width for stating the first kind groove 3 in active area 100 can be consistent, can also be inconsistent, the terminal transition The both sides of the first kind electric conductor 5 in first kind groove 3 in area 200 can all be not provided with Gate Electrode Conductive polysilicon 6, also may be used To set Gate Electrode Conductive polysilicon 6 in side, can also both sides Gate Electrode Conductive polysilicon 6 is all set, if the terminal transition region Gate Electrode Conductive polysilicon 6 is set in 200, then Gate Electrode Conductive polysilicon 6 can connect gate metal or floating, not connect metal.

The second well region of p-type 15 in terminal transition region 200 can be substituted by the first well region of p-type 8, in terminal transition region 200 The second well region of p-type 15 substituted by the first well region of p-type 8 after, N can be set in the first well region of p-type 8 in terminal transition region 200 Type source area 9, source metal 11 and N-type source region 9, the first well region of p-type 8 and first kind electric conductor 5 in terminal transition region 200 Ohmic contact；After the second well region of p-type 15 in terminal transition region 200 is substituted by the first well region of p-type 8, in terminal transition region 200 Can be not provided with N-type source region 9 in the first well region of p-type 8, in terminal transition region 200 source metal 11 and the first well region of p-type 8 with And the Ohmic contact of first kind electric conductor 5.

Example shielding is performed as described above and deletes power semiconductor device structure, can make to obtain as follows：

As shown in Fig. 2 step 1 provides semiconductor substrate, the semiconductor substrate includes N-type substrate 1 and is grown in N-type drift region 2 in N-type substrate 1, the upper surface of the N-type drift region 2 are the first interarea 001, the following table of the N-type substrate 1 Face is the second interarea 002；

Specifically, the material of semiconductor substrate can use conventional silicon, and the thickness of N-type drift region 2 is more than N-type substrate 1 Thickness, the concrete form of semiconductor substrate can also be selected as needed, specially known to those skilled in the art, Here is omitted.

Step 2 sets hard mask layer on the first interarea 001 of semiconductor substrate, optionally shelters and etches and be hard Mask layer, form the mask layer window of insertion hard mask layer；

Hard mask layer is arranged on the first interarea 001 of semiconductor substrate by deposit mode, the material of hard mask layer with And the process of setting hard mask layer is known to those skilled in the art, here is omitted.Can be by hard mask layer The modes such as upper coating photoresist, realize the masking to hard mask layer and etching, mask layer window insertion hard mask layer, so as to make It is exposed to obtain the first corresponding interarea 001 of semiconductor substrate；When it is implemented, mask layer window is included positioned at active area 100 The window of window, the window of terminal transition region 200 and terminal protection area 300.

As described in Figure 3, step 3 is carried out by the masking of mask layer window to the first interarea 001 of semiconductor substrate Etching groove, first kind groove 3 is formed in the N-type drift region 2 of active area 100 and terminal transition region 200, in terminal protection Second Type groove 12 is formed in the N-type drift region 2 in area 300；

After carrying out etching groove to the first interarea 001 of semiconductor substrate using above-mentioned mask layer window, first can be obtained The class groove 12 of class groove 3 and second, the notch of the class groove 12 of first kind groove 3 and second are respectively positioned on the first interarea 001, the A kind of groove 3 extends vertically downward with the second class groove 12 from the first interarea 001 of semiconductor substrate.Between first kind groove 3 Spacing between spacing, the second class groove 12 can be controlled by above-mentioned mask layer window, specially those skilled in the art Known, here is omitted.

As described in Figure 4, step 4 removes the mask layer window on the first interarea 001, in the first master of semiconductor substrate Selective implantation p type impurity ion on face 001, and trap is pushed away, it is respectively formed p-type in terminal transition region 200 and terminal protection area 300 Two well regions 15 and the well region 10 of p-type the 3rd；

Hard mask layer is removed by conventional technical means, after hard mask layer is removed, in the first interarea of semiconductor substrate 001 carries out p type impurity ion implanting, such as injects boron ion, so as to obtain the second well region of p-type 15 and the well region 10 of p-type the 3rd, the The top of two type grooves 12 passes through the second well region of p-type 15, and the well region of p-type second is obtained in the first interarea implanting p-type foreign ion 15th, the process of the well region 10 of p-type the 3rd is known to those skilled in the art, in addition, the second well region of p-type 15, the well region 10 of p-type the 3rd It can also be formed, can specifically be selected as needed, here is omitted by two step injection process.

As described in Figure 5, step 5 carries out dielectric filling in first kind groove 3 and Second Type groove 12, First kind dielectric 4 and first kind electric conductor filling hole 17, the shape in Second Type groove 12 are formed in first kind groove 3 Into the second class dielectric 13 and the second class electric conductor filling hole 18；

First kind dielectric 4, the second class dielectric 13 are silica, can deposit silica again by first thermal oxide Mode obtain, first kind dielectric 4, the second class dielectric 13 thickness by semiconductor devices pressure-resistant specification, N-type drift region 2 doping concentration determines that specially known to those skilled in the art, here is omitted.First kind electric conductor fills hole 17 Positioned at the center of first kind groove 3, first kind electric conductor fills hole 17 and passes through the filling first kind medium in first kind groove 3 Formed after body 4, the second class electric conductor filling hole 18 is located at the center of the second class groove 12, and the second class electric conductor filling hole 18 is logical Cross and formed in the second class groove 12 after the second class dielectric 13 of filling.

As described in Figure 6, step 6 is carried out in the first kind electric conductor filling class electric conductor of hole 18 and second filling hole 17 The filling of electric conductor, first kind electric conductor 5 is formed in first kind groove 3, the second class is formed in Second Type groove 12 Electric conductor 14；

The electric conductor can use conductive polycrystalline silicon, can deposit electric conductor in the first interarea 001 of semiconductor substrate, After electric conductor fills up first kind electric conductor filling hole 17, the second class electric conductor filling hole 18 respectively, using dry etching etc. Mode carve, to obtain the conduction of the second class in the class groove 12 of first kind electric conductor 5 and second in first kind groove 3 Body 14, detailed process are that here is omitted known to those skilled in the art.

As described in Figure 7, step 7 performs etching to the first kind dielectric 4 in first kind groove 3, in the first kind Internal channel 19 is formed at the top in groove；

Using conventional technical means, after being etched to first kind dielectric 4, internal channel 19 is obtained, internal channel 19 is from the first kind The notch of groove 3 extends vertically downward.

As described in Figure 8, step 8 deposit insulation gate oxides 7 in internal channel 19, are formed in insulation gate oxide 7 Deposit Gate Electrode Conductive polysilicon 6 in groove；

In the utility model embodiment, insulated gate oxide layer 7 is first grown in internal channel 19, and in growth insulation gate oxidation Filling Gate Electrode Conductive polysilicon 6, passes through insulation in internal channel 19 after layer 7 between Gate Electrode Conductive polysilicon 6 and first kind electric conductor 5 Gate oxide 6 and first kind dielectric 4 are dielectrically separated from；

As described in Figure 9, step 9 is selectively implanted p type impurity ion on the first interarea 001 of semiconductor substrate And trap is pushed away, form the first well region of p-type 8 in active area；

P type impurity ion can be boron ion, the injection of p type impurity ion be carried out to active area 100, in N-type drift region 2 Top obtain the first well region of p-type 8, the depth of the first well region of p-type 8 can be less than the depth of the second well region of p-type 15, p-type first Well region 8 is located to be spaced by first kind groove 3 in adjacent active area 100.The first well region of p-type 8 is located at the upper of the bottom land of internal channel 19 Side；

As described in Figure 10, step 10 be selectively implanted on the first interarea 001 of semiconductor substrate N-type impurity from Son, N-type source region 9 is formed in the first well region of p-type 8 of active area 100；

N-type impurity ion can be phosphonium ion or arsenic ion, and N-type source region 8 is located in the first well region of p-type 8, obtains N-type The process of source area 9 is that here is omitted known to those skilled in the art.

As described in Figure 11, step 11 deposits insulating medium layer on the first interarea 001 of semiconductor substrate, to described Insulating medium layer carries out contact hole etching；

Insulating medium layer can be silicon dioxide layer, and insulating medium layer is covered on the first interarea 001 of semiconductor substrate, Deposit the process of insulating medium layer and be that those skilled in the art institute is ripe to the process of the contact hole etching of insulating medium layer Know, here is omitted.

As shown in figure 11, deposited metal in contact holes of the step 12 on the first interarea 001 of semiconductor substrate, The metal level is performed etching graphically, on the first interarea of semiconductor substrate 001 formed source metal 11, gate metal with And terminal connection metal；Source metal 11 is in active area 100 and the first well region of p-type 8, the Ohmic contact of N-type source region 9, and source electrode Metal 11 electrically connects with first kind electric conductor 5, and gate metal electrically connects with Gate Electrode Conductive polysilicon 6, the second class electric conductor 14 are connected metal electricity with the second well region of p-type 15 of the outer 1 nearly side of terminal transition region 200 of place Second Type groove 12 by terminal Connection；

Front metal layer is supported on insulating medium layer, after to front metallic layer graphic, respectively obtains source electrode gold Category 11, gate metal and terminal connection metal, source metal 11 are located at active area 100, and source metal 11 passes through active area 100 Contact hole can be with the first well region of p-type 8, N-type source region 9 and the Ohmic contact of first kind electric conductor 5, gate metal and active area Gate Electrode Conductive polysilicon 6 in 100 electrically connects, so as to by the cellular in active area 100 and join together.Terminal connects metal Above terminal protection area 300, metal is connected by terminal the second class electric conductor 14 and the second class groove 12 is outer neighbouring whole The second well region of p-type 15 of the end side of transition region 200 electrically connects, and does not show that gate metal connects metal with terminal in Figure 11, has Body type of attachment is that here is omitted known to those skilled in the art.

As shown in figure 1, step 13 sets drain metal 16, the leakage on the second interarea 002 of semiconductor substrate The Ohmic contact of 16 and first conductivity type substrate of pole metal 1, the drain electrode end of MOSFET element is formed by drain metal 16.

The characteristics of the utility model, is, by the second class electric conductor 14 in Second Type groove 12 in terminal protection area 300 After being electrically connected with outer the second well region of p-type 15 close to the side of terminal transition region 200 of place Second Type groove 12, when draining High voltage on metal 16, when source metal 11 is grounded with gate metal, from bottom to top potential gradually reduces in N-type drift region 2, And the second class electric conductor 14 and the grade electricity of the second well region of p-type 15 of the side of adjacent terminals transition region 200 in Second Type groove 12 Gesture so that the potential of the second class electric conductor 14 N-type drift region 2 peripheral less than the second class groove 12, certain electrical potential difference is formed, Due to Charged Couple effect, the formation of electrical potential difference enhances the degree of exhaustion of the peripheral N-type drift region 2 of Second Type groove 12, institute That states enhancing exhausts exhausting including the bottom section horizontal direction of the second class groove 12；In addition, second in terminal protection area 300 The well region 10 of 12 bottom implanting p-type of type groove the 3rd, when the high voltage in drain metal 16, source metal 11 and gate metal During ground connection, the presence of the well region 10 of p-type the 3rd effectively enhances exhausting for N-type drift region 2 around it, and depleted region is to various aspects Extension, including horizontal direction, with the increase of voltage in drain metal 16, the two neighboring bottom part down institute of Second Type groove 12 Caused depletion layer is gradually connected in the horizontal direction, reduces the curvature of the depletion layer of terminal protection area 300, particularly effectively slows down Terminal transition region 200 is concentrated to electric field during 300 transition of terminal protection area, effectively improves the breakdown characteristics of device；If not yet There is the bottom of Second Type groove 12 in terminal protection area 300 that the well region 10 of p-type the 3rd is set, with voltage in drain metal 16 Increase, device can shift to an earlier date the bottom of Second Type groove 12 breakdown of the adjacent terminal end transition region 200 in terminal protection area 300；

When three well region 10 of p-type is set in terminal transition region 200, the N-type drift region 2 of the bottom of first kind groove 3 is not Light is exhausted with first kind electric conductor 5, is also exhausted with the well region 10 of p-type the 3rd so that the first kind in terminal transition region 200 The electric field intensity of the bottom of type groove 3 is substantially suppressed and disperseed, if the not first kind groove in terminal transition region 200 3 bottoms set the well region 10 of p-type the 3rd, and with the increase of voltage in drain metal 16, device can shift to an earlier date in terminal transition region 200 Close to the bottom breakdown of the first kind groove 3 in terminal protection area 300；If the trap of p-type the 3rd is not present in terminal transition region 200 During area 10, the almost all of N-type drift region 2 in the bottom of first kind groove 3 exhausts with first kind electric conductor 5, so the first kind The bottom peak electric field of groove 3 is high, is easy to breakdown；

Breakdown of the utility model by changing the structure device of terminal transition region 200 and terminal protection area 300 is special Property significantly improve, and simple in construction, good with existing semiconductor common process compatibility, manufacture difficulty is small, be advantageous to yield and The control of manufacturing cost.

Here description and application of the present utility model are illustrative, are not wishing to the scope of the utility model being limited in State in embodiment.The deformation and change of embodiments disclosed herein are possible, for the ordinary skill people of those this areas The replacement of embodiment and equivalent various parts are known for member.It should be appreciated by the person skilled in the art that do not taking off In the case of spirit or essential characteristics of the present utility model, the utility model can in other forms, structure, arrangement, ratio, And realized with other components, material and part., can be to this in the case where not departing from the scope of the utility model and spirit In disclosed embodiment carry out other deformations and change.

The utility model and embodiments thereof are described above, this describe it is no restricted, shown in accompanying drawing Also it is one of embodiment of the present utility model, practical structures are not limited thereto.All in all if this area it is common Technical staff is enlightened by it, in the case where not departing from the utility model and creating objective, without designing and the skill for creativeness The similar frame mode of art scheme and embodiment, all should belong to the scope of protection of the utility model.

Claims (6)

1. it is applied to the power semiconductor device structure of deep trench, in the top plan view of the semiconductor devices, including positioned at Active area on semiconductor substrate（100）, terminal transition region（200）And terminal protection area（300）, the active area（100） Positioned at the center of semiconductor substrate, terminal transition region（200）Positioned at active area（100）Outer ring and around surround it is described active Area（100）, terminal protection area（300）Positioned at terminal transition region（200）Outer ring and around surrounding the terminal transition region （200）；On the section of the semiconductor devices, semiconductor substrate has two corresponding interareas, and two interareas include the One interarea（001）And with the first interarea（001）The second corresponding interarea（002）, the first interarea of semiconductor substrate（001） With the second interarea（002）Between include the first conduction type drift region（2）With the first conductivity type substrate（1）, described first is conductive Type substrates（1）Positioned at the first conduction type drift region（2）Lower section and adjoining, first interarea（001）It is conductive for first Type drift region（2）Upper surface, second interarea（002）For the first conductivity type substrate（1）Lower surface, second master Face（002）Upper setting drain metal（16）, the drain metal（16）With the first conductivity type substrate（1）Ohmic contact；Institute State on the section of semiconductor devices, active area（100）The first conduction type drift region（2）Surface is provided with the second conduction type the One well region（8）, the well region of the second conduction type first（8）It is interior to be provided with several first kind grooves（3）, the first kind Groove（3）From second the first well region of conduction type（8）Surface along the first interarea（001）Point to the second interarea（002）Side To extending to the first conduction type drift region（2）It is interior, and first kind groove（3）Interior center is filled with first kind electric conductor （5）And positioned at the first kind electric conductor（5）The first kind dielectric of outer ring（4）, in the first kind groove（3）Interior Top is provided around first kind electric conductor（5）Internal channel（19）, the internal channel（19）Side wall be provided with insulation gate oxidation Layer（7）, and internal channel（19）It is interior to be filled with Gate Electrode Conductive polysilicon（6）, in second the first well region of conduction type（8）Surface set There is the first conduction type source area（9）, the first conduction type source area（9）With first kind groove（3）Outer wall adjoining, In active area（100）Semiconductor substrate the first interarea（001）Top is provided with source metal（11）, the source metal（11） With the first conduction type source area（9）, second the first well region of conduction type（8）Ohmic contact, and source metal（11）With first Class electric conductor（5）Electrical connection, active area（100）Several interior cellulars pass through Gate Electrode Conductive polysilicon（6）Parallel connection is in overall； On the section of the semiconductor devices, terminal transition region（200）The first conduction type drift region（2）It is conductive that surface is provided with second The well region of type second（15）, the well region of the second conduction type second（15）It is interior to be provided with first kind groove（3）, the first kind Type groove（3）From second the second well region of conduction type（15）Surface along the first interarea（001）Point to the second interarea（002）'s Direction extends to the first conduction type drift region（2）It is interior, and first kind groove（3）Interior center is conductive filled with the first kind Body（5）And positioned at the first kind electric conductor（5）The first kind dielectric of outer ring（4）, in the first kind groove（3）It is interior Top be provided around first kind electric conductor（5）Internal channel（19）, the internal channel（19）Side wall be provided with insulation grid oxygen Change layer（7）, and internal channel（19）It is interior to be filled with Gate Electrode Conductive polysilicon（6）, in terminal transition region（200）Interior semiconductor substrate The first interarea（001）Top is provided with source metal（11）, the source metal（11）With second the second well region of conduction type （15）Ohmic contact, and with first kind electric conductor（5）Electrical connection, terminal transition region（200）Several interior cellulars pass through grid Conductive polycrystalline silicon（6）Parallel connection is in overall, it is characterised in that：The terminal transition region（200）Interior first kind groove（3）Lower section Provided with the well region of the second conduction type the 3rd（10）, the well region of the second conduction type the 3rd（10）Coat terminal transition region（200） Interior first kind groove（3）Bottom land；On the section of the semiconductor devices, terminal protection area（300）It is first conductive Type drift region（2）Surface is provided with second the second well region of conduction type（15）, the well region of the second conduction type second（15）It is interior Provided with several Second Type grooves（12）, the Second Type groove（12）From second the second well region of conduction type（15）Table Face is along the first interarea（001）Point to the second interarea（002）Direction extend to the first conduction type drift region（2）It is interior, and the Two type grooves（12）Interior center is filled with the second class electric conductor（14）And positioned at the second class electric conductor（14）Outside Second class dielectric of circle（13）, the second class electric conductor（14）With place Second Type groove（12）Outer close terminal transition Area（200）Second the second well region of conduction type of side（15）Electrical connection.

2. the power semiconductor device structure according to claim 1 suitable for deep trench, it is characterised in that：Described first Type groove（3）With Second Type groove（12）For same technique manufactures layer, active area（100）Interior adjacent first type groove （3）Between spacing it is identical；Terminal transition region（200）Interior adjacent first type groove（3）Spacing can be with active area（100）It is interior Adjacent first type groove（3）Between spacing it is identical or different；Terminal protection area（300）Interior adjacent Second Type groove（12） Between distance it is identical or along active area（100）Point to terminal protection area（300）Direction gradually increase.

3. the power semiconductor device structure according to claim 1 suitable for deep trench, it is characterised in that：In terminal mistake Cross area（200）Interior first kind groove（3）Groove opening width can be with active area（100）Interior first kind groove（3） Groove opening width it is identical or different.

4. the power semiconductor device structure according to claim 1 suitable for deep trench, it is characterised in that：In terminal mistake Cross area（200）Interior first kind groove（3）Interior first kind electric conductor（5）Both sides can be not provided with Gate Electrode Conductive polysilicon （6）Or Gate Electrode Conductive polysilicon can be set in side（6）Or both sides all set Gate Electrode Conductive polysilicon（6）, and terminal transition Area（200）Interior Gate Electrode Conductive polysilicon（6）Gate metal or floating can be connect.

5. the power semiconductor device structure according to claim 1 suitable for deep trench, it is characterised in that：In terminal mistake Cross area（200）Second interior the second well region of conduction type（15）Can be by second the first well region of conduction type（8）Substitute.

6. the power semiconductor device structure according to claim 1 suitable for deep trench, it is characterised in that：For N-type Semiconductor devices, the first conduction type are that N-type is conductive, and the second conduction type is P-type conduction；For P-type semiconductor device, first Conduction type is P-type conduction, and the second conduction type is that N-type is conductive.