CN206865135U - A kind of bridge-type IGBT trigger protection circuits - Google Patents
A kind of bridge-type IGBT trigger protection circuits Download PDFInfo
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- CN206865135U CN206865135U CN201720469381.7U CN201720469381U CN206865135U CN 206865135 U CN206865135 U CN 206865135U CN 201720469381 U CN201720469381 U CN 201720469381U CN 206865135 U CN206865135 U CN 206865135U
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Abstract
The utility model discloses a kind of bridge-type IGBT trigger protection circuits, G1' and G4' is a pair of trigger signals in circuit, and G2' and G3' are another pair trigger signal, and G1' and G3' are a pair of complementary signals, and G2' and G4' are another pair complementary signal；When trigger pulse locking signal EN and trigger signal are all high level, photoelectric isolated chip cut-off output high level；When G1' is 1 or G3' is high level, when flashover signal and alarm signal are high level, an IGBT trigger signal is exported；When G1' and G3' are all high level, cut-off trigger signal conducting, protect IGBT not short-circuit；Trigger signal is blocked when flashover signal or alarm signal are low level；Thus, when G1' and G4' are all high level or G2' and G3' is all high level, the IGBT trigger signals of a pair of safety, IGBT work are sent out, and the conducting for effectively ending IGBT trigger signals when complementary signal is all high level occurs.The utility model solves the uniqueness of protection and the conducting of IGBT trigger signals of IGBT trigger signals, has ensured that IGBT safely and reliably works.
Description
Technical field
IGBT trigger protection technical fields are the utility model is related to, more particularly to a kind of bridge-type IGBT trigger protection circuits.
Background technology
IGBT be it is a kind of with MOS come the novel power transistor of controlling transistor, have that voltage is high, electric current is big, frequency
High, the features such as conducting resistance is small, it is widely used in the inverter circuit of frequency converter.But the resistance to conveyance capacity due to IGBT with it is resistance to
Overvoltage capabilities are poor, once occur that it will surprisingly damaged.For that purpose it is necessary to related protection is carried out to IGBT.Typically from excessively stream,
Overvoltage, the aspect of overheat three carry out IGBT protection circuit design.The time that IGBT bears overcurrent is only a few microseconds, resistance to inflow-rate of water turbine
It is small therefore primary it is to be noted that overcurrent protection using IGBT.
It is as shown in Figure 1 the IGBT control circuits with overcurrent protection function, the circuit can be used for medium-frequency heating system.Its
In, LM565 is integrated phase lock loop circuit, and its function is to provide the square-wave signal of frequency stabilization, by adjusting potentiometer VR1
Change LM565 output frequency；LM565 output signal is connected to d type flip flop 74HC74 by schmitt inverter 74HC14
Clock end, the output of d type flip flop is added to the input with door 74HC08 after shaping, from output end OUT1, OUT2,
The i.e. available 2 tunnel complementation square-wave signals of OUT3, OUT4.Wherein OUT1, OUT2 are one group, and OUT3, OUT4 are another group and added respectively
To the input of IGBT drive circuit.The circuit ensure that from design two paths of signals be all under any circumstance it is complementary, this
Avoid the generation that IGBT bridges lead directly to phenomenon, it is ensured that the security of IGBT module work.EN signals are IGBT controls in Fig. 1
Enable signal, when EN=1 then has control signal output, and when EN=0 is not exported then, realize and excessively stream guarantor is carried out to IGBT
Shield.But above-mentioned technical proposal can only adjust IGBT turn-on frequency, and conducting dutycycle can not be modulated, thus
Output voltage size can not be adjusted flexibly in PMW modulation；In addition, under electrifying condition, always there is that one group of IGBT is in the conduction state,
If frequency generating circuit or d type flip flop circuit break down, can make d type flip flop Q orAlways there is one to be in grow tall
Level state, thus always there is one group of IGBT to be in long conducting state, this may damage IGBT and energy storage device.
Utility model content
The purpose of this utility model is overcome the deficiencies in the prior art, proposes a kind of bridge-type IGBT trigger protection circuits,
A pair of IGBT Continuity signal is separated, only when simultaneously a pair of Continuity signals malfunction and are enabled (high level) Shi Caihui of conducting
Make IGBT length conductings, thus greatly reduce the possibility of long conducting, improve device security；In addition, the utility model is electric
Road also ensures that two groups of switches will not open at the same time, protects IGBT not short-circuit, protects IGBT normal work.
Technical scheme is used by the utility model solves its technical problem：
A kind of bridge-type IGBT trigger protection circuits, including：
First and door, described first with an input of door and trigger pulse block letter EN be connected, another input and the
One trigger signal is connected；
Second and door, described second with an input of door and trigger pulse block letter EN be connected, another input and the
Two trigger signals are connected；
3rd and door, the described 3rd with an input of door and trigger pulse block letter EN be connected, another input and the
Three trigger signals are connected；
4th and door, the described 4th with an input of door and trigger pulse block letter EN be connected, another input and the
Four trigger signals are connected；
First photoelectric isolated chip, the 3rd pin of first photoelectric isolated chip and described first and the output end of door
Signal is connected；
Second photoelectric isolated chip, the 3rd pin of second photoelectric isolated chip and described second and the output end of door
Signal is connected；
3rd photoelectric isolated chip, the 3rd pin of the 3rd photoelectric isolated chip and the described 3rd and the output end of door
Signal is connected；
4th photoelectric isolated chip, the 3rd pin of the 4th photoelectric isolated chip and the described 4th and the output end of door
Signal is connected；
First XOR gate, an input of first XOR gate and the 6th pin of first photoelectric isolated chip
Output signal G1' is connected, the other end is connected with the output signal G3' of the 6th pin of the 3rd photoelectric isolated chip；
Second XOR gate, an input of second XOR gate and the 6th pin of second photoelectric isolated chip
Output signal G2' is connected, the other end is connected with the output signal G4' of the 6th pin of the 4th photoelectric isolated chip；
5th and door, the described 5th is connected with an input of door with the output end of first XOR gate, another input
End is connected with signal SPARK；
6th and door, the described 6th is connected with an input of door with signal FAULT, another input with the described 5th with
The output end of door is connected；
7th and door, the described 7th with the output of the input and the 6th pin of first photoelectric isolated chip of door
Signal G1' is connected, another input is connected with the described 6th with the output end of door；
8th and door, the described 8th is connected with an input of door with the described 6th with the output end of door, another input
It is connected with the output signal G3' of the 6th pin of the 3rd photoelectric isolated chip；
9th and door, the described 9th is connected with an input of door with the output end of second XOR gate, another input
End is connected with network signal SPARK；
Tenth and door, the described tenth is connected with an input of door with signal FAULT, another input with the described 9th with
The output end of door is connected；
11st and door, the described 11st with the input and the 6th pin of second photoelectric isolated chip of door
Output signal G2' is connected, another input is connected with the described tenth with the output end of door；
12nd and door, the described 12nd is connected with the output end of door with the described tenth with an input of door, is another defeated
Enter end with the output signal G4' of the 6th pin of the 4th photoelectric isolated chip to be connected.
Preferably, first XOR gate includes：
First NAND gate, an input of first NAND gate and the 6th pin of first photoelectric isolated chip
Output signal G1' is connected, another input is connected with the output signal G3' of the 6th pin of the 3rd photoelectric isolated chip；
Second NAND gate, an input of second NAND gate and the 6th pin of first photoelectric isolated chip
Output signal G1' is connected, another input is connected with the output end of first NAND gate；
3rd NAND gate, an input of the 3rd NAND gate are connected with the output end of first NAND gate, are another
Input is connected with the output signal G3' of the 6th pin of the 3rd photoelectric isolated chip；.
4th NAND gate, an input of the 4th NAND gate are connected with the output end of second NAND gate, are another
Input is connected with the output end of the 3rd NAND gate.
Preferably, second XOR gate includes：
5th NAND gate, an input of the 5th NAND gate and the 6th pin of second photoelectric isolated chip
Output signal G2' is connected, another input is connected with the output signal G4' of the 6th pin of the 4th photoelectric isolated chip；
6th NAND gate, an input of the 6th NAND gate and the 6th pin of second photoelectric isolated chip
Output signal G2' is connected, another input is connected with the output end of the 5th NAND gate；
7th NAND gate, an input of the 7th NAND gate are connected with the output end of the 5th NAND gate, are another
Input is connected with the output signal G4' of the 6th pin of the 4th photoelectric isolated chip；.
8th NAND gate, an input of the 8th NAND gate are connected with the output end of the 6th NAND gate, are another
Input is connected with the output end of the 7th NAND gate.
Preferably, the IGBT trigger protections circuit also includes：With first photoelectric isolated chip, the second Phototube Coupling
The connected power supply of 2nd pin of chip, the 3rd photoelectric isolated chip and the 4th photoelectric isolated chip.
Preferably, first photoelectric isolated chip, the second photoelectric isolated chip, the 3rd photoelectric isolated chip and the 4th light
It is electrically isolated the resistance that to be connected to a resistance equal between the 2nd pin of chip and the power supply.
Preferably, described first with door, second with door, the 3rd with door and the 4th with the model 74HC08 of door.
Preferably, first photoelectric isolated chip, the second photoelectric isolated chip, the 3rd photoelectric isolated chip and the 4th light
It is electrically isolated the model 6N136 of chip.
Preferably, the model CD4011 of first XOR gate and the second XOR gate.
Preferably, the described 5th with door, the 6th with door, the 7th with door, the 8th with door, the 9th with door, the tenth with door, the tenth
One with door and the 12nd with the model CD4081 of door.
The beneficial effect that technical scheme provided by the utility model is brought is：
1st, a kind of bridge-type IGBT trigger protection circuits of the utility model, a pair of IGBT Continuity signal be it is separated, only when
A pair of Continuity signals malfunction and just to make IGBT length conductings when conducting enabled (high level) simultaneously, thus greatly reduce length and lead
Logical possibility, improves device security；
2nd, a kind of bridge-type IGBT trigger protection circuits of the utility model, ensure that two groups of switches will not open at the same time, protect
IGBT is not short-circuit, protects IGBT normal work.
The utility model is described in further detail below in conjunction with drawings and Examples, but a kind of bridge of the present utility model
Formulas I GBT trigger protection circuits are not limited to embodiment.
Brief description of the drawings
Fig. 1 is the IGBT control circuits of the prior art with overcurrent protection function；
Fig. 2 is a kind of bridge-type IGBT trigger protection circuits of the present utility model.
Embodiment
Shown in Figure 2, the utility model embodiment provides a kind of bridge-type IGBT trigger protection circuits, including：
First and door U5B, described first is connected with trigger pulse locking signal EN with a door U5B input 4, is another defeated
Enter end 5 with the first trigger signal SCR4 to be connected；
Second and door U5D, described second is connected with trigger pulse locking signal EN with a door U5D input 9, is another defeated
Enter end 10 with the second trigger signal SCR6 to be connected；
3rd and door U5C, the described 3rd is connected with trigger pulse locking signal EN with a door U5C input 12, is another
Input 13 is connected with the 3rd trigger signal SCR1；
4th and door U5A, the described 4th is connected with trigger pulse locking signal EN with a door U5A input 1, is another defeated
Enter end 2 with the 4th trigger signal SCR3 to be connected；
First photoelectric isolated chip N18, the 3rd pin of the first photoelectric isolated chip N18 and described first and door U5B
Output end signal SCR41 be connected；
Second photoelectric isolated chip N20, the 3rd pin of the second photoelectric isolated chip N20 and described second and door U5D
Output end signal SCR61 be connected；
3rd photoelectric isolated chip N19, the 3rd pin of the 3rd photoelectric isolated chip N19 and the described 3rd and door U5C
Output end signal SCR11 be connected；
4th photoelectric isolated chip N21, the 3rd pin of the 4th photoelectric isolated chip N21 and the described 4th and door U5A
Output end signal SCR31 be connected；
First XOR gate U6, an input of the first XOR gate U6 and the 6th of the first photoelectric isolated chip N18
The output signal G1' of pin is connected, the output signal G3' phases of the other end and the 6th pin of the 3rd photoelectric isolated chip N19
Even；
Second XOR gate U7, an input of the second XOR gate U7 and the 6th of the second photoelectric isolated chip N20
The output signal G2' of pin is connected, the output signal G4' phases of the other end and the 6th pin of the 4th photoelectric isolated chip N21
Even；
5th with door U9A, the described 5th be connected with a door U9A input 1 with the output end of the first XOR gate U6,
Another input 2 is connected with flashover signal SPARK；
6th and door U9B, the described 6th is connected with a door U9B input 5 with alarm signal FAULT, another input 6
It is connected with the described 5th with door U9A output end；
7th with door U10B, the described 7th and the of a door U10B input 5 and the first photoelectric isolated chip N18
The output signal G1' of 6 pins is connected, another input 6 is connected with the described 6th with door U9B output end；
8th with door U10A, the described 8th with the output end phase of door U10A an input 1 and the described 6th and door U9B
Even, another input 2 is connected with the output signal G3' of the 6th pin of the 3rd photoelectric isolated chip N19；
9th is connected with the output end of second XOR gate with a door U9C input 8 with door U9C, the described 9th, is another
One input 9 is connected with flashover signal SPARK；
Tenth and door U9D, the described tenth is connected with a door U9D input 12 with alarm signal FAULT, another input
13 are connected with the described 9th with door U9C output end；
11st and door U10D, the described 11st and door U10D an input 12 and second photoelectric isolated chip
The output signal G2' of N20 the 6th pin is connected, another input 13 is connected with the described tenth with door U9D output end；
The output end of 12nd and door U10C, the described 12nd and door U10C an input 8 and the described tenth and door U9D
It is connected, another input 9 is connected with the output signal G4' of the 6th pin of the 4th photoelectric isolated chip N21.
Further, the first XOR gate U6 includes：
First NAND gate U6A, a first NAND gate U6A input 1 and the 6th of first photoelectric isolated chip
The output signal G1' of pin is connected, the output signal of another input 2 and the 6th pin of the 3rd photoelectric isolated chip N19
G3' is connected；
Second NAND gate U6B, a second NAND gate U6B input 5 and the 6th of first photoelectric isolated chip
The output signal G1' of pin is connected, another input 6 is connected with the output end of the first NAND gate U6A；
3rd NAND gate U6C, the 3rd NAND gate U6C input 8 and the first NAND gate U6A output end
It is connected, another input 9 is connected with the output signal G3' of the 6th pin of the 3rd photoelectric isolated chip N19；.
4th NAND gate U6D, the 4th NAND gate U6D input 12 and the output end of second NAND gate
U6B is connected, another input 13 is connected with the output end of the 3rd NAND gate U6C.
Further, the second XOR gate U7 includes：
5th NAND gate U7A, the 5th NAND gate U7A input 1 and the second photoelectric isolated chip N20's
The output signal G2' of 6th pin is connected, the output of another input 2 and the 6th pin of the 4th photoelectric isolated chip N21
Signal G4' is connected；
6th NAND gate U7B, the 6th NAND gate U7B input 5 and the second photoelectric isolated chip N20's
The output signal G2' of 6th pin is connected, another input 6 is connected with the output end of the 5th NAND gate U7A；
7th NAND gate U7C, the 7th NAND gate U7C input 8 and a 5th NAND gate U7A output end
It is connected, another input 9 is connected with the output signal G4' of the 6th pin of the 4th photoelectric isolated chip N21；.
8th NAND gate U7D, the 8th NAND gate U7D input 12 and a 6th NAND gate U7B output
End is connected, another input 13 is connected with the output end of the 7th NAND gate U7C.
Preferably, the IGBT trigger protections circuit also includes：With the first photoelectric isolated chip N18, the second photoelectricity
The connected dc source of isolating chip N20, the 3rd photoelectric isolated chip N19 and the 4th photoelectric isolated chip N21 the 2nd pin
3.3V。
Further, the first photoelectric isolated chip N18, the second photoelectric isolated chip N20, the 3rd photoelectric isolated chip
It is equal that a resistance is connected between N19 and the 4th photoelectric isolated chip N21 the 2nd pin and the 3.3V dc sources
Resistance, wherein resistance R56 are connected between the first photoelectric isolated chip N18 and power supply；Resistance R58 is connected to the second Phototube Coupling
Between chip N20 and power supply；Resistance R57 is connected between the 3rd photoelectric isolated chip N19 and power supply；Resistance R58 is connected to
Between four photoelectric isolated chip N21 and power supply, resistance R56, R57, R58 are identical with R59 resistance.
Further, described first and door U5B, second and door U5D, the 3rd and door U5C and the 4th and door U5A model
74HC08。
Further, the first photoelectric isolated chip N18, the second photoelectric isolated chip N20, the 3rd photoelectric isolated chip
N19 and the 4th photoelectric isolated chip N21 model 6N136.
Further, the first XOR gate U6 and the second XOR gate U7 model CD4011.
Further, the described 5th with door U9A, the 6th and door U9B, the 7th with door U10B, the 8th and door U10A, the 9th and
Door U9C, the tenth and door U9D, the 11st and door U10D and the 12nd and door U10C model CD4081.
In the present embodiment, G1' and G4' are a pair of trigger signals, and G2' and G3' are another pair trigger signal, and G1' and G3' are
A pair of complementary signals, G2' and G4' are another pair complementary signal.
Illustrated as follows by taking the trigger process of G1' and G3' complementary signals as an example.Wherein, EN is trigger pulse block letter
Number (low level effective blockade signal), SCR4 is the first trigger signal with door U5B, when EN and SCR4 signals are all high level
When, first and door U5B output signal SCR41 is high level, and N18 photoelectric isolated chips 6N136 cut-offs, now G1' is high electricity
It is flat.Similarly, SCR1 is the 3rd trigger signal with door U5C, and when EN and SCR1 signals are all high level, the 3rd with door U5C's
Output signal SCR11 is high level, and N19 photoelectric isolated chips 6N136 cut-offs, now G3' is high level.When EN is high level,
One of them is high level for SCR4 signals and SCR1 signals, one when being low level, and one in G1' or G3' is 1, another
It is individual, it is 0 (1 represents high level, and 0 represents low level)；And when EN is low level, G1' and G3' are 0.
G1' and G3' is output to the combination of U6 subcomponents and forms XOR, and logical consequence (U6, Pin11) is finallySo only when G1' is 1 or G3' is 1, just it is as a result 1, is otherwise all 0.Therefore, as G1' and
This group of complementary signal of G3' occurs when being all high level, cut-off trigger signal conducting, protects IGBT not short-circuit.
No matter U6 outputs 1 or 0, when flashover signal SPARK is low level, the 5th and door U9A output is 0,
Block trigger signal；No matter the 5th is 1 or 0 with the output on door U9A, when IGBT alarm signal IGBT FAULT are low level
When, the 6th and door U9B output is 0, blocks trigger signal.
It follows that only G1' or G3' is high level, trigger pulse locking signal EN, flashover signal SPARK and
When IGBT alarm signal IGBT FAULT are equal high level, could exporting the IGBT trigger signals of a safety, (high level has
Effect).
Similarly, as two trigger signal G2' in addition with G4' are also, only G2' or G4' are high level, flashover
When signal SPARK and IGBT alarm signal IGBT FAULT are high level, the IGBT trigger signals of a safety could be exported.
G1' and G4' is all high level or G2' and when G3' is all high level, and circuit sends out the IGBT trigger signals of a pair of safety,
IGBT works.And there is the conducting for effectively ending IGBT trigger signals when complementary signal is all high level.
The present invention solves the uniqueness of protection and the conducting of IGBT trigger signals of IGBT trigger signals from hardware, ensures
IGBT more safely and reliably works.
Preferred embodiment of the present utility model is the foregoing is only, it is all in this practicality not to limit the utility model
Within new spirit and principle, any modification, equivalent substitution and improvements made etc., guarantor of the present utility model should be included in
Within the scope of shield.
Claims (9)
- A kind of 1. bridge-type IGBT trigger protection circuits, it is characterised in that including：First and door, described first with an input of door and trigger pulse block letter EN be connected, another input and first tactile Signal and be connected；Second and door, described second with an input of door and trigger pulse block letter EN be connected, another input and second tactile Signal and be connected；3rd and door, the described 3rd with an input of door and trigger pulse block letter EN be connected, another input and the 3rd tactile Signal and be connected；4th and door, the described 4th with an input of door and trigger pulse block letter EN be connected, another input and the 4th tactile Signal and be connected；First photoelectric isolated chip, the 3rd pin of first photoelectric isolated chip and described first and the output end signal of door It is connected；Second photoelectric isolated chip, the 3rd pin of second photoelectric isolated chip and described second and the output end signal of door It is connected；3rd photoelectric isolated chip, the 3rd pin of the 3rd photoelectric isolated chip and the described 3rd and the output end signal of door It is connected；4th photoelectric isolated chip, the 3rd pin of the 4th photoelectric isolated chip and the described 4th and the output end signal of door It is connected；First XOR gate, the output of an input of first XOR gate and the 6th pin of first photoelectric isolated chip Signal G1' is connected, the other end is connected with the output signal G3' of the 6th pin of the 3rd photoelectric isolated chip；Second XOR gate, the output of an input of second XOR gate and the 6th pin of second photoelectric isolated chip Signal G2' is connected, the other end is connected with the output signal G4' of the 6th pin of the 4th photoelectric isolated chip；5th and door, the described 5th is connected with an input of door with the output end of first XOR gate, another input with Signal SPARK is connected；6th and door, the described 6th is connected with an input of door with signal FAULT, another input and the described 5th and door Output end is connected；7th and door, the described 7th with the output signal of the input and the 6th pin of first photoelectric isolated chip of door G1' is connected, another input is connected with the described 6th with the output end of door；8th and door, the described 8th is connected with an input of door with the described 6th with the output end of door, another input and institute The output signal G3' for stating the 6th pin of the 3rd photoelectric isolated chip is connected；9th and door, the described 9th is connected with an input of door with the output end of second XOR gate, another input with Network signal SPARK is connected；Tenth and door, the described tenth is connected with an input of door with signal FAULT, another input and the described 9th and door Output end is connected；11st and door, the described 11st with the output of the input and the 6th pin of second photoelectric isolated chip of door Signal G2' is connected, another input is connected with the described tenth with the output end of door；12nd and door, the described 12nd is connected with an input of door with the described tenth with the output end of door, another input It is connected with the output signal G4' of the 6th pin of the 4th photoelectric isolated chip.
- 2. bridge-type IGBT trigger protection circuits according to claim 1, it is characterised in that first XOR gate includes：First NAND gate, the output of an input of first NAND gate and the 6th pin of first photoelectric isolated chip Signal G1' is connected, another input is connected with the output signal G3' of the 6th pin of the 3rd photoelectric isolated chip；Second NAND gate, the output of an input of second NAND gate and the 6th pin of first photoelectric isolated chip Signal G1' is connected, another input is connected with the output end of first NAND gate；3rd NAND gate, an input of the 3rd NAND gate is connected with the output end of first NAND gate, another input End is connected with the output signal G3' of the 6th pin of the 3rd photoelectric isolated chip；4th NAND gate, an input of the 4th NAND gate is connected with the output end of second NAND gate, another input End is connected with the output end of the 3rd NAND gate.
- 3. bridge-type IGBT trigger protection circuits according to claim 2, it is characterised in that second XOR gate includes：5th NAND gate, the output of an input of the 5th NAND gate and the 6th pin of second photoelectric isolated chip Signal G2' is connected, another input is connected with the output signal G4' of the 6th pin of the 4th photoelectric isolated chip；6th NAND gate, the output of an input of the 6th NAND gate and the 6th pin of second photoelectric isolated chip Signal G2' is connected, another input is connected with the output end of the 5th NAND gate；7th NAND gate, an input of the 7th NAND gate is connected with the output end of the 5th NAND gate, another input End is connected with the output signal G4' of the 6th pin of the 4th photoelectric isolated chip；8th NAND gate, an input of the 8th NAND gate is connected with the output end of the 6th NAND gate, another input End is connected with the output end of the 7th NAND gate.
- 4. bridge-type IGBT trigger protection circuits according to claim 1, it is characterised in that the IGBT trigger protections circuit Also include：With first photoelectric isolated chip, the second photoelectric isolated chip, the 3rd photoelectric isolated chip and the 4th Phototube Coupling The connected power supply of 2nd pin of chip.
- 5. bridge-type IGBT trigger protection circuits according to claim 4, it is characterised in that the first Phototube Coupling core Between piece, the second photoelectric isolated chip, the 3rd photoelectric isolated chip and the 2nd pin of the 4th photoelectric isolated chip and the power supply It is connected to the equal resistance of a resistance.
- 6. bridge-type IGBT trigger protection circuits according to claim 1, it is characterised in that described first with door, second with Door, the 3rd with door and the 4th with the model 74HC08 of door.
- 7. bridge-type IGBT trigger protection circuits according to claim 1, it is characterised in that the first Phototube Coupling core Piece, the second photoelectric isolated chip, the model 6N136 of the 3rd photoelectric isolated chip and the 4th photoelectric isolated chip.
- 8. bridge-type IGBT trigger protection circuits according to claim 1, it is characterised in that first XOR gate and second The model CD4011 of XOR gate.
- 9. bridge-type IGBT trigger protection circuits according to claim 1, it is characterised in that the described 5th with door, the 6th with Door, the 7th with door, the 8th with door, the 9th with door, the tenth with door, the 11st with door and the 12nd with the model CD4081 of door.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720469381.7U CN206865135U (en) | 2017-04-28 | 2017-04-28 | A kind of bridge-type IGBT trigger protection circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720469381.7U CN206865135U (en) | 2017-04-28 | 2017-04-28 | A kind of bridge-type IGBT trigger protection circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206865135U true CN206865135U (en) | 2018-01-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720469381.7U Active CN206865135U (en) | 2017-04-28 | 2017-04-28 | A kind of bridge-type IGBT trigger protection circuits |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206865135U (en) |
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2017
- 2017-04-28 CN CN201720469381.7U patent/CN206865135U/en active Active
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