CN206864461U - A kind of square flat pin-free packaging structure - Google Patents
A kind of square flat pin-free packaging structure Download PDFInfo
- Publication number
- CN206864461U CN206864461U CN201720659729.9U CN201720659729U CN206864461U CN 206864461 U CN206864461 U CN 206864461U CN 201720659729 U CN201720659729 U CN 201720659729U CN 206864461 U CN206864461 U CN 206864461U
- Authority
- CN
- China
- Prior art keywords
- lead frame
- copper lead
- logic chip
- packaging structure
- square flat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
A kind of square flat pin-free packaging structure is the utility model is related to, includes copper lead frame, at least one logic chip and multiple conducting wires；Encapsulated space is provided with the copper lead frame, fills insulating resin in encapsulated space, the both sides of copper lead frame are provided with multiple metal pads；The logic chip is arranged on copper lead frame, and radiating silver paste is provided between logic chip and copper lead frame, and logic chip and metal pad are electrically connected with by multiple conducting wires；The bottom surface of the copper lead frame is provided with the exposed radiating surface outside encapsulated space；The square flat pin-free packaging structure of the utility model, using bilateral no pin scheme, traditional pin is replaced using metal pad, electrodynamic capacity and routing resistance are very low, good electrical property, solve the problems, such as that chip information processing frequency is high, meanwhile copper lead frame center bottom is exposed, so that chip quickly conducts heat at work, good heat dissipation effect, reliability are high.
Description
Technical field
The utility model belongs to logic semiconductor chip encapsulation technology field, and in particular to a kind of small-size chips, nothing are drawn
The logic chip square flat pin-free packaging structure of pin, rapid heat dissipation.
Background technology
In encapsulating in the prior art, the encapsulation for the small chips of below 2mm*2mm, the general LGA/BGA with substrate class is sealed
Dress mode, or continue to use large scale encapsulating structure and have a lead-frame packages of pin, not special encapsulating structure solve
The problem of poor radiation, larger impedance.
Utility model content
The purpose of the utility model is to provide a kind of quad flat non-pin package knot for overcome the deficiencies in the prior art
Structure.
To reach above-mentioned purpose, the technical solution adopted in the utility model is：A kind of square flat pin-free packaging structure,
Include copper lead frame, logic chip and multiple conducting wires；It is provided with encapsulated space on the copper lead frame, logic chip and more
Root wire is respectively positioned in encapsulated space, and filling insulating resin in encapsulated space, the both sides of copper lead frame are provided with multiple metals
Pad；The logic chip is arranged on copper lead frame, and radiating silver paste is provided between logic chip and copper lead frame, is patrolled
Collect chip and metal pad is electrically connected with by multiple conducting wires；The bottom surface of the copper lead frame is provided with exposed in encapsulated space
Outer radiating surface.
Preferably, the area of the radiating surface is more than logic chip.
Preferably, locked mode hole is provided with the metal pad.
Preferably, the size of the copper lead frame is 3mm*3mm.
Preferably, size≤1.5mm*1.5mm of the logic chip.
Preferably, the gross thickness of the copper lead frame and encapsulated space is 0.75mm.
Due to the utilization of above-mentioned technical proposal, the utility model has following advantages compared with prior art：
A kind of square flat pin-free packaging structure described in the utility model uses bilateral no pin scheme, uses metal pad
Instead of traditional pin, routing resistance is very low in electrodynamic capacity and packaging body, so it can provide the electrical property of brilliance, solves
The problem of chip information processing frequency is high, meanwhile, copper lead frame center bottom is exposed outside encapsulated space, so that chip exists
Heat, good heat dissipation effect, reliability height are quickly conducted during work.
Brief description of the drawings
Technical solutions of the utility model are described further below in conjunction with the accompanying drawings：
Accompanying drawing 1 is the diagrammatic cross-section of square flat pin-free packaging structure described in the utility model；
Accompanying drawing 2 is the top schematic diagram of square flat pin-free packaging structure described in the utility model；
Accompanying drawing 3 is the schematic bottom view of quad flat leaded package described in the utility model；
Accompanying drawing 4 is quad flat leaded package inside chip connecting line construction schematic diagram described in the utility model；
Wherein, 11, wire；12nd, logic chip；13rd, insulating resin；14th, copper lead frame；15th, radiate silver paste；21st, side
To indicateing arm；31st, metal pad；32nd, radiating surface；41st, positioning hole；45th, locked mode hole；46th, the corrosion region of lead frame half.
Embodiment
Below in conjunction with the accompanying drawings and specific embodiment the utility model is described in further detail.
As Figure 1-4, a kind of quad flat leaded package, copper lead frame 14, at least one logic core are included
Piece 12 and multiple conducting wires 11；Encapsulated space, 11 equal position of logic chip 12 and multiple conducting wires are provided with the copper lead frame 14
In encapsulated space, filling insulating resin 13 in encapsulated space, the both sides of copper lead frame 14 are provided with the metal instead of pin
Pad 31, locked mode hole 45 is set, and locked mode hole 45 can effectively pin external resin, further enhance combination on metal pad 31
Power, improve the reliability of product；The logic chip 12 is arranged on copper lead frame 14, logic chip 12 and copper lead frame
Radiating silver paste 15 is provided between 14, radiating silver paste 15 is used for the bonding of copper lead frame 14 and logic chip 12, logic chip
12 and metal pad 31 be electrically connected with by multiple conducting wires 11；The bottom surface of the copper lead frame 14 is provided with exposed empty in encapsulation
Between outer radiating surface 32；Size≤1.5mm*1.5mm of the logic chip 12；The size of the copper lead frame 14 is 3mm*
The gross thickness of 3mm, copper lead frame 14 and encapsulated space is 0.75mm, and copper lead frame 14 is provided with the corrosion region of lead frame half
46；The upper surface of the encapsulated space is provided with direction indicateing arm 21, for indicating overall direction.
During encapsulation, logic chip 12 is ground to the thickness of encapsulation needs first, and cuts into discrete component, is then passed through
The silver paste 15 that radiates connects logic chip 12 and copper lead frame 14, welding lead 11, whole cavity is synthesized by insulating resin 13
Internal each device is protected, unification is cut after injection molding, forms unit, the back side is metal pad 31 and will plated on metal pad 31
Tin, multiple asymmetrical positioning holes 41 are set to be preferably connected with circuit board, on circuit board, it is more accurate in order to install positioning
Really.
It the above is only concrete application example of the present utility model, do not form any limit to the scope of protection of the utility model
System.All technical schemes formed using equivalent transformation or equivalent replacement, all fall within the utility model rights protection scope it
It is interior.
Claims (6)
- A kind of 1. square flat pin-free packaging structure, it is characterised in that：Include copper lead frame（14）, at least one logic core Piece（12）And multiple conducting wires（11）；The copper lead frame（14）On be provided with encapsulated space, logic chip（12）Led with more Line（11）It is respectively positioned in encapsulated space, filling insulating resin in encapsulated space（13）, copper lead frame（14）Both sides be provided with Multiple metal pads（31）；The logic chip（12）It is arranged on copper lead frame（14）On, logic chip（12）With copper lead Framework（14）Between be provided with radiating silver paste（15）, logic chip（12）And metal pad（31）Pass through multiple conducting wires（11）Electrically Connection；The copper lead frame（14）Bottom surface be provided with the exposed radiating surface outside encapsulated space（32）.
- 2. square flat pin-free packaging structure according to claim 1, it is characterised in that：The radiating surface（32）Face Product is more than logic chip（12）.
- 3. square flat pin-free packaging structure according to claim 1, it is characterised in that：The metal pad（31）On It is provided with locked mode hole（45）.
- 4. square flat pin-free packaging structure according to claim 1, it is characterised in that：The copper lead frame（14） Size be 3mm*3mm.
- 5. square flat pin-free packaging structure according to claim 1, it is characterised in that：The logic chip（12）'s Size≤1.5mm*1.5mm.
- 6. square flat pin-free packaging structure according to claim 1, it is characterised in that：The copper lead frame（14） Gross thickness with encapsulated space is 0.75mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720659729.9U CN206864461U (en) | 2017-06-08 | 2017-06-08 | A kind of square flat pin-free packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720659729.9U CN206864461U (en) | 2017-06-08 | 2017-06-08 | A kind of square flat pin-free packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206864461U true CN206864461U (en) | 2018-01-09 |
Family
ID=60830691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720659729.9U Active CN206864461U (en) | 2017-06-08 | 2017-06-08 | A kind of square flat pin-free packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206864461U (en) |
-
2017
- 2017-06-08 CN CN201720659729.9U patent/CN206864461U/en active Active
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