CN206833202U - A kind of eject key switch electromechanics road - Google Patents
A kind of eject key switch electromechanics road Download PDFInfo
- Publication number
- CN206833202U CN206833202U CN201720608601.XU CN201720608601U CN206833202U CN 206833202 U CN206833202 U CN 206833202U CN 201720608601 U CN201720608601 U CN 201720608601U CN 206833202 U CN206833202 U CN 206833202U
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- China
- Prior art keywords
- resistance
- key switch
- mcu
- schottky diode
- pmos
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Abstract
The utility model provides a kind of eject key switch electromechanics road,It includes the MCU being sequentially connected,Key control circuit,USB supplies power detection circuit and power control circuit,The key control circuit includes resistance R1,R5,R7,R8,The eject key switch SW1 and Schottky diode D2 to the encapsulation of pipe common anode formula,The positive pole pin 1 of the Schottky diode D2 is grounded by resistance R8,And it is connected with an I/O mouth of the MCU,The positive pole pin 2 of the Schottky diode D2 is connected by resistance R5 with another I/O mouth of the MCU,Tie point between the resistance R5 and MCU I/O mouths is grounded by resistance R7,Schottky diode D2 positive pole pin 2 also passes sequentially through the eject key switch SW1,Resistance R1 meets high level PS.Eject key switch electromechanics road of the present utility model has cost low and designs the advantages of simple.
Description
Technical field
It the utility model is related to electronic circuit field, more particularly to a kind of eject key switch electromechanics road.
Background technology
Key switch machine is for being all an essential function for all product on the market at present, eject
The switching on and shutting down of button also applied very extensively, its technology is also very ripe in itself, and existing implementation typically will be according to
Rely in single-chip microcomputer or the chip with computing capability does corresponding processing, the conceptual design of this type is complicated, cost is high, right
The dependence of chip is too big.
Utility model content
In order to solve the above mentioned problem of prior art, it is necessary to provide a kind of low cost and with intelligent operating system from bullet
Formula key switch electromechanics road.
The utility model solves the technical scheme that technical problem provides：
A kind of eject key switch electromechanics road, its MCU for including being sequentially connected, key control circuit, USB power supplies detect
Circuit and power control circuit, the key control circuit include resistance R1, R5, R7, R8, eject key switch SW1 and right
The Schottky diode D2 of pipe common anode formula encapsulation, the positive pole pin 1 of the Schottky diode D2 are grounded by resistance R8, and
It is connected with an I/O mouth of the MCU, the positive pole pin 2 of the Schottky diode D2 passes through the resistance R5's and MCU
Another I/O mouth is connected, and the tie point between resistance R5 and the I/O mouths of the MCU is grounded by resistance R7, Schottky
Diode D2 positive pole pin 2 also passes sequentially through the eject key switch SW1, resistance R1 meets high level PS.
In the utility model embodiment, the USB includes isolating diode D1, resistance R4, R9 and electricity for power detection circuit
Hold C4, isolating diode D1 positive pole connects USB feeder ear USB-VBus, isolating diode D1 negative pole and Schottky diode
D2 negative pin 3 is connected, and isolating diode D1 negative pole is also grounded by resistance R9, and resistance R4 one end is with isolating two poles
Pipe D1 negative pole is connected, and the other end is grounded by electric capacity C4.
In the utility model embodiment, the power control circuit include PMOS Q1, NPN triode Q2, resistance R2,
R3 and electric capacity C1, NPN triode Q2 base stage are connected by resistance R4 with Schottky diode D2 negative pin 3, NPN tri-
Pole pipe Q2 grounded emitter, NPN triode Q2 colelctor electrode are connected to high level PS by resistance R2 respectively and pass through resistance
R3 is connected to PMOS Q1 grid, and PMOS Q1 drain electrode meets high level PS, and PMOS Q1 source electrode connects power control terminal
VCC-SYS, PMOS Q1 source electrode are also grounded by electric capacity C1.
Compared with prior art, eject key switch electromechanics road of the present utility model, using a kind of eject button
The mode of switching on and shutting down, it is possible to achieve low design complexities, realize hard start, the soft-off of low cost, and system is stable, can solve
The cost of the switching on and shutting down button of prior art is high and power down is shut down the problem of causing system program to be lost.
Brief description of the drawings
Fig. 1 is the circuit diagram on the eject key switch electromechanics road of the embodiment of the utility model one.
Embodiment
As shown in figure 1, the eject key switch electromechanics road of the embodiment of the utility model one include be sequentially connected MCU,
Key control circuit, USB supply power detection circuit and power control circuit, are specifically described below.
The key control circuit includes resistance R1, R5, R7, R8, eject key switch SW1 and pipe common anode formula is encapsulated
Schottky diode D2, the positive pole pin 1 of the Schottky diode D2 is grounded by resistance R8, and with the MCU's
One I/O mouth is connected, and the positive pole pin 2 of the Schottky diode D2 passes through the resistance R5 and MCU another I/O mouth
It is connected, the tie point between resistance R5 and the I/O mouths of the MCU is grounded by resistance R7, Schottky diode D2's
Positive pole pin 2 also passes sequentially through the eject key switch SW1, resistance R1 meets high level PS.
It should be noted that key switch SW1 is off in acquiescence, and when SW1 is pressed, Schottky diode D2
Pin 2, the forward conduction of pin 3, export the voltage to be remained basically stable with high level PS.Resistance R5 and resistance R7 forms one
Bleeder circuit, export a high level compatible with the I/O mouth level of the MCU.Resistance R8 is maintained at as pull down resistor is
Unite off-mode under, Schottky diode D2 pin 1 is constantly in low level, off-mode not by with the I/ being connected
The influence of O mouths.Schottky diode D2 does the effect of forward conduction herein.
USB includes isolating diode D1, resistance R4, R9 and electric capacity C4 for power detection circuit.Isolating diode D1 positive pole
USB feeder ear USB-VBus are met, isolating diode D1 negative pole is connected with Schottky diode D2 negative pin 3.Isolation
Diode D1 negative pole is grounded by resistance R9.Resistance R4 one end is connected with isolating diode D1 negative pole, and the other end leads to
Cross electric capacity C4 ground connection.
It should be noted that when using USB power supplies, USB power supply exports a high level by isolating diode D1
Schottky diode D2 negative pin 3 is given to, this pin is drawn high.Pull down resistor R9 main functions are ensured and are being not powered on
Schottky diode D2 negative pin 3 is kept into low level under situation.Resistance R4 and electric capacity C4 is respectively intended to partial pressure and storage
Electric charge.
Power control circuit includes PMOS Q1, NPN triode Q2, resistance R2, R3 and electric capacity C1.NPN triode Q2's
Base stage is connected by resistance R4 with Schottky diode D2 negative pin 3, NPN triode Q2 grounded emitter, NPN tri-
Pole pipe Q2 colelctor electrode is connected to high level PS by resistance R2 respectively and PMOS Q1 grid is connected to by resistance R3,
PMOS Q1 drain electrode meets high level PS, and PMOS Q1 source electrode connects power control terminal VCC-SYS, PMOS Q1 source electrode
Also it is grounded by electric capacity C1.
It should be noted that NPN triode Q2 is mainly used to control PMOS pipes Q1 switch, when NPN triode Q2's
When pin base stage has the high level to come, its emitter stage turns on colelctor electrode, and PMOS pipes Q1 the first pin is drawn as low level, by
The on state characteristic of PMOS pipes understands that PMOS pipes Q1 source electrode and drain electrode now turn on, VCC-SYS output high level, system electricity
Establish machine on source by cable.Resistance R2 is to draw high PMOS Q1 grid when NPN triode Q2 is in cut-off state, so as to turn off
PMOS Q1 source electrode and drain electrode, system power failure shutdown.
Whole circuit operation principle general introduction：
Start：When key switch SW1 is pressed, NPN triode Q2 receives a high level, and system electrification is started shooting, this
When MCU receive POWER-DET high level the I/O port where POWER-OFF persistently immediately exported into a high level, now
Button is just unclamped at last, and NPN triode Q2 base stage also has a high level, maintains the normal operation of system always.
Shutdown：After the time that system detectio to key switch SW1 is persistently pressed, which exceedes, to be limitation（System is set）,
The MCU does certain record, and the MCU immediately sends a low level in the I/O port where POWER-OFF after unclamping button,
PMOS pipes Q1 is turned off after NPN triode Q2 base stage receives low level, system power failure shutdown.
Compared with prior art, eject key switch electromechanics road of the present utility model, using a kind of eject button
The mode of switching on and shutting down, it is possible to achieve low design complexities, realize hard start, the soft-off of low cost, and system is stable, can solve
The cost of the switching on and shutting down button of prior art is high and power down is shut down the problem of causing system program to be lost.
Above content is to combine specific preferred embodiment further detailed description of the utility model, it is impossible to
Assert that specific implementation of the present utility model is confined to these explanations.For the ordinary skill of the utility model art
For personnel, without departing from the concept of the premise utility, some simple deduction or replace can also be made, should all be regarded
To belong to the scope of protection of the utility model.
Claims (3)
1. a kind of eject key switch electromechanics road, it is characterised in that including MCU, key control circuit, the USB being sequentially connected
For power detection circuit and power control circuit, the key control circuit includes resistance R1, R5, R7, R8, eject key switch
The SW1 and Schottky diode D2 to the encapsulation of pipe common anode formula, the positive pole pin 1 of the Schottky diode D2 are connect by resistance R8
Ground, and be connected with an I/O mouth of the MCU, the positive pole pin 2 of the Schottky diode D2 passes through resistance R5 and institute
Another I/O mouth for stating MCU is connected, and the tie point between resistance R5 and the I/O mouths of the MCU is connect by resistance R7
Ground, Schottky diode D2 positive pole pin 2 also passes sequentially through the eject key switch SW1, resistance R1 meets high level PS.
2. eject key switch electromechanics road according to claim 1, it is characterised in that the USB supplies power detection circuit
Including isolating diode D1, resistance R4, R9 and electric capacity C4, isolating diode D1 positive pole meets USB feeder ear USB-VBus, every
Negative pole from diode D1 is connected with Schottky diode D2 negative pin 3, and isolating diode D1 negative pole also passes through electricity
R9 ground connection is hindered, resistance R4 one end is connected with isolating diode D1 negative pole, and the other end is grounded by electric capacity C4.
3. eject key switch electromechanics road according to claim 2, it is characterised in that the power control circuit includes
PMOS Q1, NPN triode Q2, resistance R2, R3 and electric capacity C1, NPN triode Q2 base stage pass through resistance R4 and Schottky two
Pole pipe D2 negative pin 3 is connected, and NPN triode Q2 grounded emitter, NPN triode Q2 colelctor electrode passes through electricity respectively
Resistance R2 is connected to high level PS and PMOS Q1 grid is connected to by resistance R3, and PMOS Q1 drain electrode connects high level
PS, PMOS Q1 source electrode meet power control terminal VCC-SYS, and PMOS Q1 source electrode is also grounded by electric capacity C1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720608601.XU CN206833202U (en) | 2017-05-27 | 2017-05-27 | A kind of eject key switch electromechanics road |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720608601.XU CN206833202U (en) | 2017-05-27 | 2017-05-27 | A kind of eject key switch electromechanics road |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206833202U true CN206833202U (en) | 2018-01-02 |
Family
ID=60773946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720608601.XU Expired - Fee Related CN206833202U (en) | 2017-05-27 | 2017-05-27 | A kind of eject key switch electromechanics road |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206833202U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109981090A (en) * | 2019-04-26 | 2019-07-05 | 福建科立讯通信有限公司 | A kind of Sofe Switch electromechanics road that can restore on-off state automatically |
-
2017
- 2017-05-27 CN CN201720608601.XU patent/CN206833202U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109981090A (en) * | 2019-04-26 | 2019-07-05 | 福建科立讯通信有限公司 | A kind of Sofe Switch electromechanics road that can restore on-off state automatically |
| CN109981090B (en) * | 2019-04-26 | 2022-10-25 | 福建科立讯通信有限公司 | Soft on-off circuit capable of automatically recovering on-off state |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180102 Termination date: 20190527 |