CN206759423U - A kind of high-speed annular oscillator for being suitable for the anti-SET reinforcement techniques of triplication redundancy - Google Patents
A kind of high-speed annular oscillator for being suitable for the anti-SET reinforcement techniques of triplication redundancy Download PDFInfo
- Publication number
- CN206759423U CN206759423U CN201720657735.0U CN201720657735U CN206759423U CN 206759423 U CN206759423 U CN 206759423U CN 201720657735 U CN201720657735 U CN 201720657735U CN 206759423 U CN206759423 U CN 206759423U
- Authority
- CN
- China
- Prior art keywords
- ring retard
- delay cell
- ring
- input
- retard
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The utility model discloses a kind of high-speed annular oscillator for being suitable for the anti-SET reinforcement techniques of triplication redundancy, SET based on Capacitance Coupled Phase synchronization mould redundancy reinforces differential voltage controlled oscillator by three ring retard (i.e. the first ring retards, second ring retard and the 3rd ring retard), three coupled capacitors (i.e. the first coupled capacitor C1, the second coupled capacitor C2 and the 3rd coupled capacitor C3) and one voting electric capacity (the first voting circuit) composition.Wherein, in first ring retard, the second ring retard and the 3rd ring retard composition Three links theory, the Phase synchronization of three loops is realized by coupled capacitor C1, C2 and C3, the input of three loops is just the same, and the control voltage end Vcont of ring retard is connected with control voltage in three loops.The strong and high-speed annular oscillator of raising VCO frequencies of oscillation the utility model proposes a kind of suitable anti-SET abilities.
Description
Technical field
The utility model relates to radiation hardened integrated circuit field, more particularly, is related to one kind and is based on triplication redundancy technology
Anti-single particle transition (Single-Event Transient, SET) reinforce high-speed annular voltage controlled oscillator (Voltage-
Controlled-Oscillator, VCO).
Background technology
The chip being operated in radiation environment, can be in " the electricity that the node of chip circuit ionizes out by high-energy particle bombardment
Son-hole ", so that node voltage or electric current produce instantaneity fluctuation, cause circuit to produce the output of mistake, produce SET
Effect.Research shows that integrated circuit is susceptible to SET influence and causes various failures.
Annular V CO is mainly used in the circuits such as frequency multiplication, frequency synthesis and clock generation.In clock system steady-working state
Under VCO by high-energy particle bombardment when, may cause its output produce phase and frequency deviation, or even vibration stop.
The technology associated with the utility model is recorded in following document：
The B of Chinese patent CN 101958713,《A kind of SET based on triplication redundancy technology reinforces differential voltage controlled oscillator》
It is proposed the anti-SET reinforcement techniques of triplication redundancy VCO.
Fig. 1 is the VCO structures directly realized based on conventional difference VCO using triplication redundancy technology, and it is by the first difference
VCO, the second difference VCO, the 3rd difference VCO and the first voting circuit composition.Wherein, control voltage connects the first difference VCO, the
Two difference VCO and the 3rd difference VCO control voltage input Vcont, the first difference VCO output OUT connections first are decided by vote
The input B of the input A, the second difference VCO of circuit output OUT the first voting circuits of connection, the 3rd difference VCO output
The output of the input C of OUT the first voting circuits of connection, the output Z of the first voting circuit as integrated circuit.
Fig. 2 show the utility model technology by the first ring retard, the second ring retard, the 3rd ring retard, the first voting electricity
Road and the second voting circuit composition.Wherein the first ring retard and the first voting circuit, the second voting circuit form the first loop, the
Two ring retards and the first voting circuit, the second voting circuit form the second loop, the 3rd ring retard and the first voting circuit, second
Voting circuit forms Three links theory.The input of three loops is just the same, the control voltage end Vcont of ring retard in three loops
It is connected with control voltage, the first ring retard, the second ring retard, the Differential Input IN+ of the 3rd ring retard are electric with the second voting
The output Z2 on road is connected, the first ring retard, the second ring retard, the 3rd ring retard Differential Input IN- with the first voting circuit
Output Z1 be connected, the input A1 of difference output OUT1+ the first voting circuits of connection of the first ring retard, the difference of the second ring retard
Divide the input B1 of output OUT2+ the first voting circuits of connection, difference output OUT3+ the first voting circuits of connection of the 3rd ring retard
Input C1, the input A2 of difference output OUT1- the second voting circuits of connection of the first ring retard, the difference of the second ring retard is defeated
Go out the input B2 of OUT2- the second voting circuits of connection, difference output OUT3- the second voting circuits of connection of the 3rd ring retard it is defeated
Enter C2, so as to form the differential VCO structure based on triplication redundancy technology.
For the VCO structures for directly using the realization of triplication redundancy technology, the common port of three difference VCO loops is only
Control voltage Vcont, it can only ensure that the frequency of oscillation of three difference VCO loops is identical, and uncontrollable loop phase, therefore three
Clock phase caused by individual loop is random, causes voting circuit can not export correct clock.For voting circuit is drawn
Enter triplication redundancy technology in ring retard, voting machine is different from the structure of delay cell, increases the delay of ring oscillator, causes
VCO frequency of oscillation is limited.Therefore, how to improve the high speed VCO designs of anti-SET abilities is that most difficulty and challenge is asked
Topic.
Utility model content
The strong and high-speed annular oscillator of raising VCO frequencies of oscillation the utility model proposes a kind of suitable anti-SET abilities.
What the technical solution of the utility model was realized in：
A kind of high-speed annular oscillator for being suitable for the anti-SET reinforcement techniques of triplication redundancy, including the first ring retard, second prolong
Three loops that slow ring and the 3rd ring retard are formed, three loops realize Phase synchronization by coupled capacitor C1, C2 and C3；Three
The input of individual loop is identical, and the control voltage end Vcont of each ring retard is connected with control voltage in three loops；Also include
First voting circuit；
Wherein, the output end CO11 of delay cell 1 in the first ring retard connect respectively phase coupling estimation electric capacity C1 one end and
The input of delay cell 2 in first ring retard；The output end CO12 connections first of delay cell 2 in first ring retard are prolonged
The input of delay cell 3 in slow ring；The output end CO13 of delay cell 3 in first ring retard connects phase coupling estimation respectively
The input of delay cell 1 in electric capacity C3 one end and the first ring retard, the output end of the delay cell 3 in the first ring retard
CO13 is also connected with the input A of the first voting circuit；
The output end CO21 connection phase coupling estimation electric capacity C1 of delay cell 1 in the second ring retard other end and second prolong
The input of delay cell 2 in slow ring, the output end CO22 of the delay cell 2 in the second ring retard connect phase coupling estimation respectively
The input of delay cell 3 in electric capacity C2 one end and the second ring retard, the output end of the delay cell 3 in the second ring retard
The input B of the input of delay cell 1 and the first voting circuit in CO23 the second ring retards of connection；
The input of the delay cell 2 in the ring retard of 1 output end CO31 connections of delay cell the 3rd in 3rd ring retard,
The output end CO32 of delay cell 2 in 3rd ring retard connects the phase coupling estimation electric capacity C2 other end and the 3rd ring retard respectively
In delay cell 3 input；The output end CO33 connection phase coupling estimation electric capacity C3's of delay cell 3 in 3rd ring retard
The input of delay cell 1 in the other end, and the 3rd ring retard, the output end CO33 of the delay cell 3 in the 3rd ring retard is also
Connect the input C of the first voting circuit；
The output end O connections VCO of first voting circuit output.
The utility model proposes a kind of high-speed annular oscillator for being suitable for the anti-SET reinforcement techniques of triplication redundancy, use
Capacitance Coupled Phase synchronization technology, the first ring retard and the second ring retard realize Phase synchronization by coupled capacitor C1, and second prolongs
Slow ring and the 3rd ring retard realize Phase synchronization by coupled capacitor C2, and the 3rd ring retard and the first ring retard pass through coupled capacitor
C3 realizes Phase synchronization, and so as to realize the Phase synchronization of three loops, the output of three loops connects the input of voting circuit,
Correct VCO output signals are decided by vote by way of alternative.
Following technique effect can be reached using the utility model：
1. the phase of three VCO loops is effectively synchronized using coupled capacitor, so as to reduce because voting circuit introduces
Loop delay, improve radioresistance VCO frequency of oscillation.
2. realizing triplication redundancy VCO structures, sensitivitys of the VCO to SET is effectively reduced.When some VCO loop by
When being bombarded to single-particle, the output signals of the VCO delay cells will produce phase deviation, and the delay of other two VCO loops
The output signal of unit is normal and phase is consistent, and voting circuit is by selecting two identical delay cells in three VCO loops
Output signal and obtain correct clock signal, so as to reach shielding erroneous clock signal signal target so that VCO is to SET's
Sensitivity substantially reduces.
Brief description of the drawings
, below will be to embodiment in order to illustrate more clearly of the utility model embodiment or technical scheme of the prior art
Or the required accompanying drawing used is briefly described in description of the prior art, it should be apparent that, drawings in the following description are only
It is some embodiments of the utility model, for those of ordinary skill in the art, before creative labor is not paid
Put, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the VCO circuits directly realized in the prior art using triplication redundancy technology.
Fig. 2 is to introduce the VCO circuits that voting circuit triplication redundancy technology is realized in ring retard in the prior art.
Fig. 3 is a kind of circuit for the high-speed annular oscillator for being suitable for the anti-SET reinforcement techniques of triplication redundancy of the utility model.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the embodiment of the utility model is carried out
Clearly and completely describing, it is clear that described embodiment is only the utility model part of the embodiment, rather than whole
Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made
The every other embodiment obtained, belong to the scope of the utility model protection.
Refer to Fig. 3, a kind of high-speed annular oscillator for being suitable for the anti-SET reinforcement techniques of triplication redundancy, including first prolong
Three loops that Chi Huan, the second ring retard and the 3rd ring retard are formed, three loops are realized by coupled capacitor C1, C2 and C3
Phase synchronization；The input of three loops is identical, and the control voltage end Vcont of each ring retard is and control voltage in three loops
It is connected；Also include the first voting circuit；
Wherein, the output end CO11 of delay cell 1 in the first ring retard connect respectively phase coupling estimation electric capacity C1 one end and
The input of delay cell 2 in first ring retard；The output end CO12 connections first of delay cell 2 in first ring retard are prolonged
The input of delay cell 3 in slow ring；The output end CO13 of delay cell 3 in first ring retard connects phase coupling estimation respectively
The input of delay cell 1 in electric capacity C3 one end and the first ring retard, the output end of the delay cell 3 in the first ring retard
CO13 is also connected with the input A of the first voting circuit；
The output end CO21 connection phase coupling estimation electric capacity C1 of delay cell 1 in the second ring retard other end and second prolong
The input of delay cell 2 in slow ring, the output end CO22 of the delay cell 2 in the second ring retard connect phase coupling estimation respectively
The input of delay cell 3 in electric capacity C2 one end and the second ring retard, the output end of the delay cell 3 in the second ring retard
The input B of the input of delay cell 1 and the first voting circuit in CO23 the second ring retards of connection；
The input of the delay cell 2 in the ring retard of 1 output end CO31 connections of delay cell the 3rd in 3rd ring retard,
The output end CO32 of delay cell 2 in 3rd ring retard connects the phase coupling estimation electric capacity C2 other end and the 3rd ring retard respectively
In delay cell 3 input；The output end CO33 connection phase coupling estimation electric capacity C3's of delay cell 3 in 3rd ring retard
The input of delay cell 1 in the other end, and the 3rd ring retard, the output end CO33 of the delay cell 3 in the 3rd ring retard is also
Connect the input C of the first voting circuit；
The output end O connections VCO of first voting circuit output.
The utility model proposes a kind of high-speed annular oscillator for being suitable for the anti-SET reinforcement techniques of triplication redundancy, be base
Differential voltage controlled oscillator is reinforced in the SET of Capacitance Coupled Phase synchronization mould redundancy, using Capacitance Coupled Phase synchronization technology,
First ring retard and the second ring retard realize Phase synchronization by coupled capacitor C1, and the second ring retard and the 3rd ring retard pass through coupling
Close electric capacity C2 and realize Phase synchronization, the 3rd ring retard and the first ring retard realize Phase synchronization by coupled capacitor C3, so as to real
The Phase synchronization of existing three loops, the input of the output connection voting circuit of three loops, is decided by vote by way of alternative
Correct VCO output signals.
The utility model proposes a kind of high-speed annular oscillator operation side for being suitable for the anti-SET reinforcement techniques of triplication redundancy
Formula is that under control of a control voltage, delay cell chain circuit passes through when VCO three loops are not bombarded by SET
The consistent periodic swinging output signal of phase coupling estimation electric capacity generation phase exports produces signal output to voting circuit.Now,
The difference output of the delay circuit of three VCO loops is normal, i.e., the frequency of oscillation of output signal and phase are completely the same, the first table
Certainly circuit receives the clock signal of three Complete Synchronizations and produces correctly output clock.
When some loop is by high-energy particle bombardment, it is assumed that when SET occurs by the first ring retard, the delay of the first loop
The phase of the output signal of loop produces deviation, and the output signal of the delay circuit of the second loop and Three links theory is normal, table
Certainly circuit receives the clock signal of two synchronizations caused by three loops and produces correctly output clock.Therefore, voting circuit
It can shield and correctly be exported clock by the SET output signals for being influenceed and producing the first loop of deviation so as to produce.
Described in the utility model the phase between each ring is realized logical step using capacitive coupling technique, it is applied to various rings
The delay cell of shape oscillator, suitable for the ring oscillator of various delay series, the multi-mode redundant for being not limited to triplication redundancy resists
SET ring oscillators.
Preferred embodiment of the present utility model is the foregoing is only, it is all at this not to limit the utility model
Within the spirit and principle of utility model, any modification, equivalent substitution and improvements made etc., the utility model should be included in
Protection domain within.
Claims (1)
1. a kind of high-speed annular oscillator for being suitable for the anti-SET reinforcement techniques of triplication redundancy, it is characterised in that including the first delay
Three loops that ring, the second ring retard and the 3rd ring retard are formed, three loops realize phase by coupled capacitor C1, C2 and C3
Bit synchronization；The input of three loops is identical, in three loops the control voltage end Vcont of each ring retard with control voltage phase
Even；Also include the first voting circuit；
Wherein, the output end CO11 of delay cell 1 in the first ring retard connects phase coupling estimation electric capacity C1 one end and first respectively
The input of delay cell 2 in ring retard；Output end CO12 the first ring retards of connection of delay cell 2 in first ring retard
In delay cell 3 input；The output end CO13 of delay cell 3 in first ring retard connects phase coupling estimation electric capacity respectively
The input of delay cell 1 in C3 one end and the first ring retard, the output end CO13 of the delay cell 3 in the first ring retard
It is also connected with the input A of the first voting circuit；
The output end CO21 connection phase coupling estimation electric capacity C1 of delay cell 1 in the second ring retard other end and the second ring retard
In delay cell 2 input, the output end CO22 of the delay cell 2 in the second ring retard connects phase coupling estimation electric capacity respectively
The input of delay cell 3 in C2 one end and the second ring retard, the output end CO23 of the delay cell 3 in the second ring retard
Connect the input B of the input of delay cell 1 and the first voting circuit in the second ring retard；
The input of the delay cell 2 in the ring retard of 1 output end CO31 connections of delay cell the 3rd in 3rd ring retard, the 3rd
The output end CO32 of delay cell 2 in ring retard is connected in phase coupling estimation electric capacity the C2 other end and the 3rd ring retard respectively
The input of delay cell 3；The output end CO33 connection phase coupling estimation electric capacity C3's of delay cell 3 in 3rd ring retard is another
End, and the input of delay cell 1 in the 3rd ring retard, the output end CO33 of the delay cell 3 in the 3rd ring retard are also connected with
The input C of first voting circuit；
The output end O connections VCO of first voting circuit output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720657735.0U CN206759423U (en) | 2017-06-07 | 2017-06-07 | A kind of high-speed annular oscillator for being suitable for the anti-SET reinforcement techniques of triplication redundancy |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720657735.0U CN206759423U (en) | 2017-06-07 | 2017-06-07 | A kind of high-speed annular oscillator for being suitable for the anti-SET reinforcement techniques of triplication redundancy |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206759423U true CN206759423U (en) | 2017-12-15 |
Family
ID=60622439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720657735.0U Expired - Fee Related CN206759423U (en) | 2017-06-07 | 2017-06-07 | A kind of high-speed annular oscillator for being suitable for the anti-SET reinforcement techniques of triplication redundancy |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206759423U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107147389A (en) * | 2017-06-07 | 2017-09-08 | 佛山科学技术学院 | A kind of high-speed annular oscillator for being suitable for the anti-SET reinforcement techniques of triplication redundancy |
-
2017
- 2017-06-07 CN CN201720657735.0U patent/CN206759423U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107147389A (en) * | 2017-06-07 | 2017-09-08 | 佛山科学技术学院 | A kind of high-speed annular oscillator for being suitable for the anti-SET reinforcement techniques of triplication redundancy |
| CN107147389B (en) * | 2017-06-07 | 2023-05-02 | 佛山科学技术学院 | High-speed ring oscillator suitable for triple-modular redundancy anti-SET reinforcement technology |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102122953B (en) | Fast lock-in all-digital phase-locked loop with extended tracking range | |
| CN106936426A (en) | A kind of triplication redundancy radiation hardening clock forming circuit based on phaselocked loop | |
| CN101901176B (en) | Redundant clock system | |
| CN103546151B (en) | High-speed DLL (Delay-locked loop) | |
| CN106972857A (en) | A kind of many loop self-biased phase-locked loop circuits and clock generator | |
| US7646254B2 (en) | Radiation hard oscillator and differential circuit design | |
| CN108768385A (en) | A kind of annular voltage controlled oscillator that power supply rejection ratio is promoted | |
| CN206759423U (en) | A kind of high-speed annular oscillator for being suitable for the anti-SET reinforcement techniques of triplication redundancy | |
| CN105515577B (en) | A kind of reinforcing ring oscillator of anti-SET | |
| CN110212915B (en) | Coupling type frequency multiplication delay phase-locked loop circuit with uniform split-phase output | |
| EP0180342A3 (en) | Signal comparison circuit and phase-locked-loop using same | |
| CN105322952B (en) | Multi-modulus frequency divider and communication means | |
| CN102724033A (en) | Method and main control veneer for realizing alignment of phase positions of master clock and reserved clock | |
| CN203870506U (en) | Low frequency clock signal synchronous circuit for multiple redundant computer systems | |
| CN101958713B (en) | Triple-modular redundancy technology-based single event transient (SET) reinforcement differential voltage-controlled oscillator (VCO) | |
| CN107634751A (en) | A kind of radioresistance latch circuit latched based on multichannel | |
| Robles et al. | A 0.6 v programmable frequency divider and digitally controlled oscillator for use in a digital pll in the subthreshold region | |
| CN107147389A (en) | A kind of high-speed annular oscillator for being suitable for the anti-SET reinforcement techniques of triplication redundancy | |
| CN102055443A (en) | Duty cycle detection circuit | |
| Chen et al. | A radiation-tolerant ring oscillator phase-locked loop in 0.13 µm CMOS | |
| CN103888099B (en) | A kind of anti-single particle transient state redundancy filter circuit | |
| CN109525243B (en) | Frequency divider circuit with anti-radiation function | |
| CN109560813B (en) | Cross-coupling voltage-controlled oscillator with anti-irradiation function | |
| CN208316703U (en) | A kind of X-band scene surveillance radar multichannel high stable local oscillator source circuit | |
| CN111934679A (en) | Phase-locked loop high-speed frequency division circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20171215 Termination date: 20200607 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |