CN206726209U - Peripheral hardware insertion detection circuit and terminal device - Google Patents
Peripheral hardware insertion detection circuit and terminal device Download PDFInfo
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- CN206726209U CN206726209U CN201720610892.6U CN201720610892U CN206726209U CN 206726209 U CN206726209 U CN 206726209U CN 201720610892 U CN201720610892 U CN 201720610892U CN 206726209 U CN206726209 U CN 206726209U
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Abstract
The disclosure is directed to peripheral hardware insertion detection circuit and terminal device.This method includes：First control circuit and second control circuit are set, first control circuit is connected with PCI and second control circuit respectively, and first control circuit is used for the first control signal according to corresponding to peripheral hardware whether being inserted in PCI and send to second control circuit；Second control circuit is also connected with main control chip, second control circuit is used for the second control signal according to corresponding to the first control signal received to main control chip input, so that main control chip judges whether insert peripheral hardware in PCI according to the second control signal.The safety and reliability that main control chip uses can effectively be lifted by above-mentioned structure.
Description
Technical field
This disclosure relates to communication technical field, more particularly to peripheral hardware insertion detection circuit and terminal device.
Background technology
Be in terminal device by main control chip control corresponding to circuit to USB (Universal Serial
Bus, referred to as：USB) peripheral hardware inserted in interface is charged or data transfer operation, therefore, it is necessary to notifies main control chip
Whether peripheral hardware is inserted in USB interface.At present, USB supply voltages can be inputted in terminal device to the input of main control chip, with
The magnitude of voltage for allowing main control chip to be inputted according to input determines whether insert peripheral hardware in USB interface.
Utility model content
To overcome problem present in correlation technique, the embodiment of the present disclosure provides peripheral hardware insertion detection circuit and terminal is set
It is standby.The technical scheme is as follows：
According to the first aspect of the embodiment of the present disclosure, there is provided a kind of peripheral hardware insertion detection circuit, including：
One end of first control circuit is connected with PCI, the other end of the first control circuit and second
Control circuit is connected, the first control circuit be used for according to whether insert peripheral hardware in the PCI and to described
First control signal corresponding to second control circuit transmission；
The other end of the second control circuit is connected with main control chip, and the second control circuit is used for according to reception
First control signal arrived to the main control chip input corresponding to the second control signal so that the main control chip according to
Second control signal judges whether insert peripheral hardware in the PCI.
The technical scheme provided by this disclosed embodiment can include the following benefits：First control circuit and the are set
Two control circuits, first control circuit are connected with PCI and second control circuit respectively, and first control circuit is used
In the first control signal according to corresponding to peripheral hardware whether being inserted in PCI and send to second control circuit；Second control
Circuit processed is connected with power supply and main control chip respectively, and second control circuit is used for according to the first control signal for receiving to master
Control chip input corresponding to the second control signal so that main control chip judged according to the second control signal be in PCI
No insertion peripheral hardware.The safety and reliability that main control chip uses can effectively be lifted by above-mentioned structure.
In one embodiment, the first control circuit includes：Triode；
The base stage of the triode is connected with the power pins of the PCI；
The grounded emitter of the triode；
The colelctor electrode of the triode is connected with the second control circuit.
The technical scheme provided by this disclosed embodiment can include the following benefits：Realized by triode to peripheral hardware
The detection of peripheral hardware is inserted in connecting interface, effectively improves the reliability of circuit.
In one embodiment, the second control circuit includes：Field-effect transistor and power supply；
The source electrode of the field-effect transistor is connected with the power supply, the grid of the field-effect transistor and described three
The colelctor electrode of pole pipe is connected, and the drain electrode of the field-effect transistor is connected with the input of the main control chip.
The technical scheme provided by this disclosed embodiment can include the following benefits：Combined by field-effect transistor
The input signal of power supply and triode determines the second control signal exported to main control chip, so as to which main control chip can be according to the
Two control signals determine whether insert peripheral hardware in PCI, effectively improve the reliability of main control chip.
In one embodiment, the first control circuit also includes：First divider resistance and the second divider resistance；
One end of first divider resistance is connected with the power pins in the PCI, described first point
The other end of piezoresistance is connected with one end of second divider resistance and the base stage of the triode respectively, described second point
The other end ground connection of piezoresistance.
The technical scheme provided by this disclosed embodiment can include the following benefits：By using the first divider resistance
With the second divider resistance, the reliability of triode is improved.
In one embodiment, the second control circuit also includes：First resistor；
One end of the first resistor is connected with the source electrode of the field-effect transistor；The other end of the first resistor
It is connected with the grid of the field-effect transistor.
The technical scheme provided by this disclosed embodiment can include the following benefits：By setting first resistor, carry
The reliability of field-effect transistor is risen.
In one embodiment, the circuit also includes：Second resistance；
The second resistance is connected between the drain electrode of the field-effect transistor and the input of the main control chip, and
One end of the second resistance is connected with the drain electrode of the field-effect transistor；The other end of the second resistance and the master
The input of control chip is connected.
The technical scheme provided by this disclosed embodiment can include the following benefits：By setting second resistance, carry
The reliability of main control chip is risen.
In one embodiment, it is described also to include：3rd resistor；
One end of the 3rd resistor is connected with the input of the main control chip；Another termination of the 3rd resistor
Ground.
The technical scheme provided by this disclosed embodiment can include the following benefits：By setting 3rd resistor, when
When peripheral hardware is not inserted into PCI, it can be ensured that the input end of main control chip avoids the occurrence of erroneous judgement in low level.
In one embodiment, the triode is NPN, and the field-effect transistor is：Enhanced PMOS field-effects are brilliant
Body pipe.
According to the second aspect of the embodiment of the present disclosure, there is provided a kind of terminal device, including as described in above-mentioned any embodiment
Peripheral hardware insertion detection circuit.
It should be appreciated that the general description and following detailed description of the above are only exemplary and explanatory, not
The disclosure can be limited.
Brief description of the drawings
Accompanying drawing herein is merged in specification and forms the part of this specification, shows the implementation for meeting the disclosure
Example, and be used to together with specification to explain the principle of the disclosure.
Fig. 1 is the peripheral hardware insertion detection circuit schematic diagram according to an exemplary embodiment one.
Fig. 2 is the peripheral hardware insertion detection circuit schematic diagram according to an exemplary embodiment two.
Embodiment
Here exemplary embodiment will be illustrated in detail, its example is illustrated in the accompanying drawings.Following description is related to
During accompanying drawing, unless otherwise indicated, the same numbers in different accompanying drawings represent same or analogous key element.Following exemplary embodiment
Described in embodiment do not represent all embodiments consistent with the disclosure.On the contrary, they be only with it is such as appended
The example of the consistent apparatus and method of some aspects be described in detail in claims, the disclosure.
At present, in terminal device USB supply voltages can be inputted to the input of main control chip, with allow main control chip according to
The magnitude of voltage of input input determines whether insert peripheral hardware in USB interface.And because the acceptable magnitude of voltage of main control chip is smaller,
Therefore, partial pressure can be carried out to USB supply voltages by resistance, by the input of the control source after partial pressure to control chip.
But with the development of electronic technology, in order to lift the charging rate of terminal device, fast charge mode arises at the historic moment, and
Due to fast charge mode be by improving USB supply voltages, since lift charge power, and then accelerate charging rate.But due to USB
The lifting of supply voltage, so as to which USB supply voltages are inputted to main control chip by existing circuit, it will result in main control chip
Damage.
In the disclosure, first control circuit and second control circuit, first control circuit is set to be connected connect with peripheral hardware respectively
Mouthful be connected with second control circuit, first control circuit for according to whether insert peripheral hardware in PCI and to second
First control signal corresponding to control circuit transmission；Second control circuit also main control chip is connected, and second control circuit is used for
According to the second control signal corresponding to the first control signal received to main control chip input, so that main control chip is according to second
Control signal judges whether insert peripheral hardware in PCI.Wherein, because first control circuit can connect according to peripheral hardware
Whether insert peripheral hardware in mouthful and to second control circuit send corresponding to the first control signal, and then second control circuit is used for root
According to the second control signal corresponding to the first control signal received to main control chip input, due to main control chip receive for the
Second control signal of two control circuit outputs, rather than voltage of the peripheral hardware connection supply voltage after electric resistance partial pressure is received, from
And the safety and reliability that main control chip uses is improved, avoid main control chip and damage or judge by accident because input voltage is too high
Situation.
It is worth noting that, the PCI in the disclosure includes but is not limited to USB interface.
Fig. 1 is the peripheral hardware insertion detection circuit schematic diagram according to an exemplary embodiment one, as shown in figure 1, the electricity
Road includes：
One end of first control circuit 11 is connected with PCI 12, the other end of first control circuit 11 and
One end of two control circuits 13 is connected, wherein, whether first control circuit 11 is used to insert according in PCI 12
Peripheral hardware and to second control circuit 13 send corresponding to the first control signal.
The other end of second control circuit 13 is connected with main control chip 14, wherein, second control circuit 13 is used for basis
The first control signal received inputs corresponding second control signal to main control chip 14, so that main control chip 14 is according to second
Control signal judges whether insert peripheral hardware in PCI.
Wherein, when being not inserted into peripheral hardware in insertion peripheral hardware and PCI in PCI 12, the first control
The first control signal that circuit 11 is sent to second control circuit 13 differs.
Such as：When inserting peripheral hardware in PCI 12, first control circuit 11 is sent to second control circuit 13
The first control signal be low level signal；And when being not inserted into peripheral hardware in PCI 12, first control circuit 11 to
The first control signal that second control circuit 13 is sent is high level signal.
When being not inserted into peripheral hardware in peripheral hardware and PCI 12 due to being inserted in PCI 12, the first control electricity
The first control signal that road 11 is sent to second control circuit 13 differs.Therefore, second control circuit 13 can basis
The first different control signals inputs the second different control signals to main control chip 14, to allow main control chip 14 according to different
Second control signal determines whether insert peripheral hardware in PCI 12.
Continue according to above-mentioned example, when the first control signal that first control circuit 11 is sent to second control circuit 13
When being low level signal, second control circuit 13 controls according to the low level signal received to main control chip 14 inputs second
Signal is high level signal, so as to which main control chip 14 determines to insert peripheral hardware in PCI 12 according to the high level signal；
When the first control signal that first control circuit 11 is sent to second control circuit 13 is high level signal, second control circuit
13 according to the high level signal that receives to the second control signal that main control chip 14 input be low level signal so that master control core
Piece 14 determines to be not inserted into peripheral hardware in PCI 12 according to the low level signal.
Because main control chip 14 is that the second control signal sent according to the second control circuit 13 of reception determines that peripheral hardware connects
Peripheral hardware whether is not inserted into connection interface 12, rather than receives voltage of the peripheral hardware connection supply voltage after electric resistance partial pressure, so as to
The safety and reliability that main control chip 14 uses is improved, main control chip 14 is avoided and damages or miss because input voltage is too high
Situation about sentencing.
In the disclosure, first control circuit and second control circuit, first control circuit is set to be connected connect with peripheral hardware respectively
Mouthful be connected with second control circuit, first control circuit for according to whether insert peripheral hardware in PCI and to second
First control signal corresponding to control circuit transmission；Second control circuit is connected with power supply and main control chip respectively, the second control
Circuit processed is used for the second control signal according to corresponding to the first control signal received to main control chip input, so that master control core
Piece judges whether insert peripheral hardware in PCI according to the second control signal.Master can effectively be lifted by above-mentioned structure
The safety and reliability that control chip uses.
In one embodiment, as shown in Fig. 2 above-mentioned first control circuit 11 includes：Triode Q1；
Wherein, triode Q1 base stage is connected with the power pins of PCI；Triode Q1 emitter stage connects
Ground；Triode Q1 colelctor electrode is connected with second control circuit.
In a kind of achievable mode, triode Q1 can be NPN triode, when peripheral hardware connects power on,
That is, when peripheral hardware is inserted in PCI, voltage difference can be formed between triode Q1 base stage and triode Q1 emitter stage,
So as to which triode enters saturation state, triode Q1 colelctor electrode is close consistent with the level of triode Q1 emitter stage, three poles
Turned between pipe Q1 colelctor electrode and triode Q1 emitter stage, due to triode Q1 grounded emitter, therefore, triode Q1
Current collection extremely low level, that is, now, triode Q1 is to second control circuit input low level signal.
When peripheral hardware connects power supply access failure, that is, when peripheral hardware is not inserted into PCI, triode Q1 base stage
Separated with triode Q1 emitter stage, triode Q1 is not to second control circuit incoming level signal.
Detection to inserting peripheral hardware in PCI is realized by triode Q1, it is outer when being inserted in PCI
If when, triode Q1 conductings, when being not inserted into peripheral hardware in PCI, triode Q1 disconnects, and then, triode Q1 is to the
Two control circuits 13 export corresponding control signal, without the supply voltage in PCI is directly inputted into master control
Chip 14, so as to improve the reliability of circuit.
It is worth noting that, microcontroller or logical device can also be used as first control circuit.The disclosure is not right
The implementation of first control circuit is any limitation as.
The technical scheme provided by this disclosed embodiment can include the following benefits：Realized by triode to peripheral hardware
The detection of peripheral hardware is inserted in connecting interface, effectively improves the reliability of circuit.
When the power pins of PCI 12 are directly connected with triode Q1 base stage, if PCI
The magnitude of voltage of 12 power pins output is excessive, triode Q1 damage can be caused, therefore, in order to protect triode Q1, such as Fig. 2
Shown, first control circuit 11 also includes：First divider resistance R2 and the second divider resistance R3；
First divider resistance R2 one end is connected with the power pins in PCI, the first divider resistance R2's
The other end is connected with the second divider resistance R3 one end and the base stage of triode respectively, the second divider resistance R3 another termination
Ground.
The power supply of PCI is lit a cigarette point by using the first divider resistance R2 and the second divider resistance R3
Pressure, makes triode Q1 base voltage be in rational section, so as to avoid triode Q1 because base stage inputs too high electricity
Press and damage, improve triode Q1 reliability.
The technical scheme provided by this disclosed embodiment can include the following benefits：By using the first divider resistance
With the second divider resistance, the reliability of triode is improved.
In one embodiment, as shown in Fig. 2 second control circuit 13 includes：Field-effect transistor Q2 and power supply；
Field-effect transistor Q2 source electrode is connected with power supply, field-effect transistor Q2 grid and triode Q1 current collection
Pole is connected, and field-effect transistor Q2 drain electrode is connected with the input of main control chip 14.
Example, above-mentioned field-effect transistor Q2 can be enhanced PMOS FETs.
When peripheral hardware connects power on, that is, when inserting peripheral hardware in PCI 12, triode Q1 current collection is extremely
Low level, that is, triode Q1 to field-effect transistor Q2 input for low level signal, now, field-effect transistor Q2's
Voltage difference is formed between grid and field-effect transistor Q2 source electrode, drain electrode and field-effect transistor so as to field-effect transistor Q2
Turned between Q2 source electrode, field-effect transistor Q2 drain electrode can form high level, by the high level signal (high level signal
As the second control signal) to main control chip 14, main control chip 14 can be to determine that peripheral hardware connects according to the high level signal for input
Peripheral hardware is inserted in connection interface 12.
It is worth noting that, microcontroller or logical device can also be used as second control circuit.The disclosure is not right
The implementation of second control circuit is any limitation as.
The technical scheme provided by this disclosed embodiment can include the following benefits：Combined by field-effect transistor
The input signal of power supply and triode determines the second control signal exported to main control chip, so as to which main control chip can be according to the
Two control signals determine whether insert peripheral hardware in PCI, effectively improve the reliability of main control chip.
When peripheral hardware connects power supply access failure, that is, when being not inserted into peripheral hardware in PCI, triode Q1 base stage with
Triode Q1 emitter stage it is separated, now, the open circuit of field-effect transistor Q2 grid and field-effect transistor Q2 source electrode
Connect power supply, then, now it is possible to shape between the source electrode for the grid and field-effect transistor Q2 that field-effect transistor Q2 occurs
Into voltage difference, so as to situation about being turned between field-effect transistor Q2 drain electrode and field-effect transistor Q2 source electrode, so as to make
The second control signal sent into field-effect transistor Q2 to main control chip 14 is wrong, and then the feelings for causing main control chip 14 to be judged by accident
Condition, as shown in Fig. 2 second control circuit 13 also includes：First resistor R1；First resistor R1 one end and field-effect transistor
Q2 source electrode is connected；The first resistor R1 other end is connected with field-effect transistor Q2 grid.
When peripheral hardware connects power supply access failure, first resistor R1 can ensure that field-effect transistor Q2 is in the state disconnected,
So as to prevent field-effect transistor Q2 grid drop-in low levels, system erroneous judgement is caused.
Example, after first resistor R1 is accessed, when peripheral hardware connects power supply access failure, triode Q1 base stage and three poles
Pipe Q1 emitter stage it is separated, and due to first resistor R1 presence, now field-effect transistor Q2 grid and field-effect
There is no voltage difference between transistor Q2 source electrode, so as to field-effect transistor Q2 drain electrode and field-effect transistor Q2 source electrode it
It is separated, and now field-effect transistor Q2 does not input any level signal to main control chip 14, so as to the not work of main control chip 14
Make, and peripheral hardware is now also not inserted into PCI 12, it is not necessary to which main control chip 14 controls corresponding circuit to connect peripheral hardware
The peripheral hardware inserted in connection interface 12 is charged or data transfer operation, effectively improves the accuracy of the judgement of main control chip 14.
The technical scheme provided by this disclosed embodiment can include the following benefits：By setting first resistor, carry
The reliability of field-effect transistor is risen.
In order to avoid in the case of accident (such as：Field-effect transistor Q2 is due to being damaged and non-normal working), power supply
The input of main control chip 14 is directly poured into larger current, causes input pin to damage.Therefore, as shown in Fig. 2 on
Stating circuit also includes：Second resistance R4；
Second resistance R4 is connected between field-effect transistor Q2 drain electrode and the input of main control chip 14, and the second electricity
Resistance R4 one end is connected with field-effect transistor Q2 drain electrode；The second resistance R4 other end and the input of main control chip 14
It is connected.
By setting second resistance R4 to carry out partial pressure to the voltage inputted to the input of main control chip 14, avoid leading
Control chip 14 damages.
The technical scheme provided by this disclosed embodiment can include the following benefits：By setting second resistance, carry
The reliability of main control chip is risen.
When peripheral hardware connects power supply access failure, it is possible that input to the level of main control chip 14 is high level signal,
So as to cause main control chip 14 to be judged by accident, therefore, as shown in Fig. 2 foregoing circuit also includes：3rd resistor R5；
3rd resistor R5 one end is connected with the input of main control chip 14；3rd resistor R5 other end ground connection.
The technical scheme provided by this disclosed embodiment can include the following benefits：By setting 3rd resistor, when
When peripheral hardware is not inserted into PCI, it can be ensured that the input end of main control chip avoids the occurrence of erroneous judgement in low level.
It is worth noting that, the main control chip in the disclosure includes but is not limited to：Central processing unit (Central
Processing Unit, referred to as：CPU), micro-control unit (Microcontroller Unit, is referred to as：MCU it is), live
Programmable gate array (Field-Programmable Gate Array, referred to as：), or CPLD FPGA
(Complex Programmable Logic Device, referred to as：The control class chip such as CPLD).
Describe the realization principle of the circuit of the disclosure in detail with reference to Fig. 2, PCI is in this embodiment
USB interface：
In the present embodiment, the input of main control chip 14 is the I/O pin of main control chip 14, and power supply is master control chip I/O
Power supply.
When USB interface is not inserted into peripheral hardware, that is, when USB power source is not present, between Q1 colelctor electrode and Q1 emitter stage
Disconnect, Q1 colelctor electrode is pulled upward to high level by main control chip I O power supply, that is, Q1 colelctor electrode inputted to Q2 grid the
One control signal is high level signal, and now Q2 grid is in high level.Due to not having between Q2 grid and Q2 source electrode
Voltage difference, therefore, Q2 are off.Now, Q2 drain electrode is in vacant state, can pull down to low level by R5, Q2's
The second control signal inputted to main control chip 14 that drains is low level signal, and the I/O pin of main control chip recognizes low level letter
After number, USB interface is inserted currently without peripheral hardware so as to learn.
When peripheral hardware is inserted in USB interface, that is, in the presence of USB power source, the voltage official post of Q1 base stage and Q1 emitter stage
Q1 enters saturation state, and the voltage of Q1 colelctor electrode and Q1 emitter stage reaches unanimity, that is, grid of the Q1 colelctor electrode to Q2
First control signal of input is low level signal, and low level is pulled down to so as to Q2 grid.So, Q2 grid and Q2
Voltage difference between source electrode be present, turn on Q2, there is high level in Q2 drain electrode, Q2 drain electrode inputted to main control chip 14 second
Control signal is low level signal, main control chip I/O pin is recognized high level, and learning currently has peripheral hardware to insert USB interface.
After peripheral hardware is extracted from USB interface, that is, USB power source disappears, now circuit can enter above-mentioned USB interface
The state of peripheral hardware is not inserted into, main control chip I/O pin can recognize low level, be connect so as to learn currently without peripheral hardware insertion USB
Mouthful.
It is worth noting that, the low level voltage difference of main control chip I O power supply and Q2 grid, therefore, to assure that can make at Q2
In conducting state.
The disclosure also provides a kind of terminal device, and the terminal device includes the peripheral hardware insertion inspection described in any of the above-described embodiment
Slowdown monitoring circuit.
Those skilled in the art will readily occur to the disclosure its after considering specification and putting into practice disclosure disclosed herein
Its embodiment.The application is intended to any modification, purposes or the adaptations of the disclosure, these modifications, purposes or
Person's adaptations follow the general principle of the disclosure and including the undocumented common knowledges in the art of the disclosure
Or conventional techniques.Description and embodiments are considered only as exemplary, and the true scope of the disclosure and spirit are by following
Claim is pointed out.
It should be appreciated that the precision architecture that the disclosure is not limited to be described above and is shown in the drawings, and
And various modifications and changes can be being carried out without departing from the scope.The scope of the present disclosure is only limited by appended claim.
Claims (9)
- A kind of 1. peripheral hardware insertion detection circuit, it is characterised in that including：One end of first control circuit is connected with PCI, the other end of the first control circuit and the second control One end of circuit is connected, the first control circuit be used for according to whether insert peripheral hardware in the PCI and to institute State the first control signal corresponding to second control circuit transmission；The other end of the second control circuit is connected with main control chip, and the second control circuit is used for what basis received Second control signal corresponding to first control signal to main control chip input, so that the main control chip is according to Second control signal determines whether insert peripheral hardware in the PCI.
- 2. circuit according to claim 1, it is characterised in that the first control circuit includes：Triode；The base stage of the triode is connected with the power pins of the PCI；The grounded emitter of the triode；The colelctor electrode of the triode is connected with the second control circuit.
- 3. circuit according to claim 2, it is characterised in that the second control circuit includes：Field-effect transistor and Power supply；The source electrode of the field-effect transistor is connected with the power supply, the grid of the field-effect transistor and the triode Colelctor electrode be connected, the drain electrode of the field-effect transistor is connected with the input of the main control chip.
- 4. the circuit according to Claims 2 or 3, it is characterised in that the first control circuit also includes：First partial pressure electricity Resistance and the second divider resistance；One end of first divider resistance is connected with the power pins in the PCI, the first partial pressure electricity The other end of resistance is connected with one end of second divider resistance and the base stage of the triode respectively, the second partial pressure electricity The other end ground connection of resistance.
- 5. circuit according to claim 3, it is characterised in that the second control circuit also includes：First resistor；One end of the first resistor is connected with the source electrode of the field-effect transistor；The other end of the first resistor and institute The grid for stating field-effect transistor is connected.
- 6. circuit according to claim 3, it is characterised in that the circuit also includes：Second resistance；The second resistance is connected between the drain electrode of the field-effect transistor and the input of the main control chip, and described One end of second resistance is connected with the drain electrode of the field-effect transistor；The other end of the second resistance and the master control core The input of piece is connected.
- 7. circuit according to claim 6, it is characterised in that described also to include：3rd resistor；One end of the 3rd resistor is connected with the input of the main control chip；The other end ground connection of the 3rd resistor.
- 8. circuit according to claim 3, it is characterised in that the triode is NPN, and the field-effect transistor is： Enhanced pmos fet.
- 9. a kind of terminal device, it is characterised in that including the peripheral hardware insertion detection circuit as described in claim any one of 1-8.
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| CN201720610892.6U CN206726209U (en) | 2017-05-27 | 2017-05-27 | Peripheral hardware insertion detection circuit and terminal device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112929099A (en) * | 2019-12-06 | 2021-06-08 | 惠州视维新技术有限公司 | Signal detection method, terminal and storage medium |
| CN113295956A (en) * | 2021-06-04 | 2021-08-24 | 广州朗国电子科技有限公司 | DP signal source detection circuit, DP signal source detection method and display device |
-
2017
- 2017-05-27 CN CN201720610892.6U patent/CN206726209U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112929099A (en) * | 2019-12-06 | 2021-06-08 | 惠州视维新技术有限公司 | Signal detection method, terminal and storage medium |
| CN112929099B (en) * | 2019-12-06 | 2022-10-11 | 惠州视维新技术有限公司 | Signal detection method, terminal and storage medium |
| CN113295956A (en) * | 2021-06-04 | 2021-08-24 | 广州朗国电子科技有限公司 | DP signal source detection circuit, DP signal source detection method and display device |
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