CN206686079U

CN206686079U - Booster circuit

Info

Publication number: CN206686079U
Application number: CN201720429115.1U
Authority: CN
Inventors: 易克
Original assignee: Chipsea Technologies Shenzhen Co Ltd
Current assignee: Chipsea Technologies Shenzhen Co Ltd
Priority date: 2017-04-20
Filing date: 2017-04-20
Publication date: 2017-11-28
Anticipated expiration: 2027-04-20

Abstract

The utility model discloses a kind of booster circuit, the booster circuit includes power input, power output end, the first NMOS tube, the second NMOS tube, the first drive circuit unit, the second drive circuit unit, inductance, output capacitance array and main control circuit unit；Power input is connected through inductance with the source electrode of the first NMOS tube and the drain electrode of the second NMOS tube, the drain electrode of first NMOS tube is connected with one end of output capacitance array and power output end, the other end ground connection of output capacitance array, the grid of the first NMOS tube are connected with the output end of the first drive circuit unit；The source ground of second NMOS tube, the grid of the second NMOS tube are connected with the output end of the second drive circuit unit；The input of first drive circuit unit and the second drive circuit unit is connected with main control circuit unit, and main control circuit unit is also connected with power output end.The utility model reduces cost while meeting boosting requirement and improving load capacity.

Description

Booster circuit

Technical field

Electronic technology field is the utility model is related to, more particularly to a kind of booster circuit.

Background technology

At present, lithium battery is widely used in all kinds of consumer electronics products, such as desk lamp, portable power source, atomizer, shaves Knife, small fan and toy etc., but due to the discharge voltage range of lithium battery be usually 2.8V to 4.3V, and disappear for above-mentioned Take electronic product, be generally required for using 5V voltages or higher voltage, therefore, using the consumer electronics of lithium battery power supply Corresponding DC-DC booster circuit is both provided with product.

In the prior art, the DC-DC booster circuit in most of consumer electronics products is all using Boost boosting cores Piece realizes the boost function to lithium battery voltage, but the DC-DC booster circuit of boosting is realized using Boost boost chips The magnitude of voltage exported is changeless, and its band carries electric current generally all within 1A, so as to limit consumer electronics production The maximum power value of product；Also, when above-mentioned DC-DC booster circuit is applied to the application scenarios of high pressure or heavy duty, it is necessary to additional MOSFET driving chips realize the purpose of adjustment boost value, and the DC-DC booster circuit of additional MOSFET driving chips, due to The price of MOSFET driving chips is costly so that the DC-DC booster circuit has the defects of circuit cost is higher.

Utility model content

Main purpose of the present utility model is to propose a kind of booster circuit, it is intended to meets that boosting requires and improved band and carries energy While power, the cost of circuit is reduced.

To achieve these goals, the utility model provides a kind of booster circuit, and the booster circuit includes power input End, power output end, the first NMOS tube, the second NMOS tube, for driving the first of the first NMOS tube switch motion to drive Circuit unit, the second drive circuit unit for driving the second NMOS tube switch motion, for according to described first The switch motion of NMOS tube and second NMOS tube carries out electrical power storage or the releasable inductance of electricity, for defeated to the power supply Enter the electric energy that the electric energy at end and the inductance are discharged to be stored, be powered the power output end and to the electricity Output capacitance array that the voltage of source output terminal is filtered and for the voltage according to the power output end and default Target boost value controls the main control circuit unit of first drive circuit unit and second drive circuit unit work；Its In：

The power input is connected with the first end of the inductance, the second end of the inductance respectively with the first NMOS tube Source electrode and the second NMOS tube drain electrode connection, drain electrode one end with the output capacitance array respectively of first NMOS tube And power output end connection, the other end ground connection of the output capacitance array, the grid of first NMOS tube with it is described The output end connection of first drive circuit unit；The source ground of second NMOS tube, the grid of second NMOS tube with The output end connection of second drive circuit unit；The input of first drive circuit unit and the second driving electricity Control output end of the input of road unit with the main control circuit unit is connected；The sampling input of the main control circuit unit End is connected with the power output end.

Preferably, first drive circuit unit includes first resistor, second resistance, 3rd resistor, the 4th resistance, the One NPN triode, the first PNP triode, the 3rd NMOS tube, the first electric capacity and the first diode；Wherein：

The grid of 3rd NMOS tube is the input of first drive circuit unit, the 3rd NMOS tube Grid is connected with the control output end of the main control circuit unit and the first end of the first resistor respectively, the 3rd NMOS The drain electrode of pipe is connected with the base stage of first NPN triode and the base stage of first PNP triode respectively, and the described 3rd Second end of the source electrode of NMOS tube and the first resistor is grounded；The colelctor electrode of first NPN triode and described second The first end connection of resistance, the second end of the second resistance are connected with the base stage of first NPN triode, and described first The emitter stage of NPN triode is connected with the emitter stage of first PNP triode and the first end of the 3rd resistor respectively；Institute State the grounded collector of the first PNP triode；Second end of the 3rd resistor is the output of first drive circuit unit End, the second end of the 3rd resistor is connected with the grid of first NMOS tube；The first end of 4th resistance with it is described The grid connection of first NMOS tube, the second end of the 4th resistance is connected with the drain electrode of second NMOS tube；Described second The first end of resistance is also connected with the negative electrode of first diode and the first end of first electric capacity respectively；Described 1st The anode of pole pipe is connected with the power output end；Second end of first electric capacity is connected with the second end of the inductance.

Preferably, second drive circuit unit includes the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, the Two NPN triodes and the second PNP triode；Wherein：

The first end of 5th resistance be second drive circuit unit input, the first of the 5th resistance End is connected with the control output end of the main control circuit unit, the second end of the 5th resistance respectively with the 2nd NPN tri- The first end connection of the base stage of pole pipe, the base stage of second PNP triode and the 6th resistance, the of the 6th resistance Two ends are grounded；The colelctor electrode of second NPN triode is connected with the power output end, the hair of second NPN triode Emitter-base bandgap grading is connected with the emitter stage of the 2nd PNP triodes and the first end of the 7th resistance respectively；2nd PNP tri- The grounded collector of pole pipe；Second end of the 7th resistance be second drive circuit unit output end, the described 7th Second end of resistance is connected with the grid of second NMOS tube, first end and second NMOS tube of the 8th resistance Grid connects, the second end ground connection of the 8th resistance.

Preferably, the output capacitance array includes at least two electric capacity, one end after at least two electric capacity parallel connection with The power output end connection, the other end ground connection after at least two electric capacity parallel connection.

Preferably, the voltage that the main control circuit unit includes being used to sample the voltage of the power output end is adopted Sample circuit subelement and the voltage for being sampled according to the voltage sampling circuit subelement and the default target Boost value controls first drive circuit unit and the controller of second drive circuit unit work；Wherein：

The sampling input of the voltage sampling circuit subelement is connected with the power output end, the voltage sample electricity The sampled output of way unit is connected with the sampling input of the controller；The control output end of the controller includes the One control output end and the second control output end, the first control output end of the controller and first drive circuit unit Input connection, the second control output end of the controller is connected with the input of second drive circuit unit.

Preferably, the voltage sampling circuit subelement includes the 9th resistance and the tenth resistance；Wherein：

The first end of 9th resistance be the voltage sampling circuit subelement sampling input, the 9th resistance First end be connected with the power output end, the second end of the 9th resistance being adopted for the voltage sampling circuit subelement Sample output end, the second end of the 9th resistance respectively with the sampling input of the controller and the tenth resistance first End connection, the second end ground connection of the tenth resistance.

Preferably, the booster circuit also includes being used for the filter circuit for being filtered the voltage of the power input Unit, one end of the filter circuit unit are connected with the power input, the other end ground connection of the filter circuit unit.

Preferably, the filter circuit unit includes the second electric capacity, the 3rd electric capacity and the 4th electric capacity；Wherein：

Second electric capacity, the 3rd electric capacity and the 4th electric capacity it is parallel with one another after one end and the power input End connection, second electric capacity, the 3rd electric capacity and the 4th electric capacity it is parallel with one another after the other end ground connection.

The utility model provides a kind of booster circuit, and the booster circuit includes power input, power output end, first NMOS tube, the second NMOS tube, the first drive circuit unit for driving the first NMOS tube switch motion, for driving State the second drive circuit unit of the second NMOS tube switch motion, for according to first NMOS tube and second NMOS tube Switch motion carry out electrical power storage or the releasable inductance of electricity, for the electric energy to the power input and inductance institute The electric energy of release is stored, the power output end is powered and the voltage of the power output end is filtered Output capacitance array and for the voltage according to the power output end and default target boost value control described first Drive circuit unit and the main control circuit unit of second drive circuit unit work；The power input and the inductance First end connection, the second end of the inductance is connected with the source electrode of the first NMOS tube and the drain electrode of the second NMOS tube respectively, institute The drain electrode for stating the first NMOS tube is connected with one end of the output capacitance array and the power output end respectively, the output electricity Hold the other end ground connection of array, the grid of first NMOS tube is connected with the output end of first drive circuit unit；Institute The source ground of the second NMOS tube is stated, the output end of the grid of second NMOS tube and second drive circuit unit connects Connect；The input of the input of first drive circuit unit and second drive circuit unit with the governor circuit The control output end connection of unit；The sampling input of the main control circuit unit is connected with the power output end.This practicality New booster circuit reduces the cost of circuit while meeting that boosting requires and improves load capacity；Meanwhile this practicality It is new also have it is simple in construction and the advantages of easily realize.

Brief description of the drawings

, below will be to embodiment in order to illustrate more clearly of the utility model embodiment or technical scheme of the prior art Or the required accompanying drawing used is briefly described in description of the prior art, it should be apparent that, drawings in the following description are only It is some embodiments of the utility model, for those of ordinary skill in the art, is not paying the premise of creative work Under, other accompanying drawings can also be obtained according to the structure shown in these accompanying drawings.

Fig. 1 is the structural representation of the embodiment of the utility model booster circuit one；

Fig. 2 be the embodiment of the utility model booster circuit one described in controller output the first control signal PWM1 and Second control signal PWM2 waveform diagram.

Realization, functional characteristics and the advantage of the utility model purpose will be described further referring to the drawings in conjunction with the embodiments.

Embodiment

It should be appreciated that specific embodiment described herein is not used to limit this only to explain the utility model Utility model.

Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the embodiment of the utility model is carried out Clearly and completely describing, it is clear that described embodiment is only part of the embodiment of the present utility model, rather than all Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not making creative work premise Lower obtained every other embodiment, belong to the scope of the utility model protection.

It is to be appreciated that the description for being related to " first ", " second " etc. in the utility model is only used for describing purpose, and can not It is interpreted as indicating or implies its relative importance or imply the quantity of the technical characteristic indicated by indicating.Thus, define " the One ", at least one this feature can be expressed or be implicitly included to the feature of " second ".In addition, the skill between each embodiment Art scheme can be combined with each other, but must can be implemented as basis with those of ordinary skill in the art, when technical scheme With reference to occurring conflicting or will be understood that the combination of this technical scheme is not present when can not realize, also not in the utility model It is required that protection domain within.

The utility model provides a kind of booster circuit, reference picture 1, and Fig. 1 is the embodiment of the utility model booster circuit one Structural representation, in the present embodiment, the booster circuit includes power input VIN, power output end VOUT, the first NMOS tube 101st, the second NMOS tube 102, switch motion for driving the first NMOS pipes 101 the first drive circuit unit 103, The second drive circuit unit 104 for the switch motion that drives second NMOS tube 102, for according to the first NMOS The switch motion of pipe 101 and second NMOS tube 102 carries out electrical power storage or the releasable inductance L1 of electricity, for described The electric energy that power input VIN electric energy and the inductance L1 are discharged is stored, the power output end VOUT is carried out Power supply and the output capacitance array 105 being filtered to the voltage of the power output end VOUT, for according to the power supply Output end VOUT voltage and default target boost value control first drive circuit unit 103 and second driving The main control circuit unit 106 that circuit unit 104 works.In the present embodiment, the voltage of the power input VIN is by lithium battery There is provided.

Specifically, in the present embodiment, the power input VIN is connected with the first end of the inductance L1, the inductance L1 the second end is connected with the source electrode of the first NMOS tube 101 and the drain electrode of the second NMOS tube 102 respectively, first NMOS tube 101 drain electrode is connected with one end of the output capacitance array 105 and the power output end VOUT respectively, the output capacitance The other end ground connection of array 105, the output end of the grid of first NMOS tube 101 and first drive circuit unit 103 Connection；The source ground of second NMOS tube 102, the grid of second NMOS tube 102 and the second drive circuit list The output end connection of member 104；The input of first drive circuit unit 103 and second drive circuit unit 104 Control output end of the input with the main control circuit unit 106 is connected；The sampling input of the main control circuit unit 106 It is connected with the power output end VOUT.

In the present embodiment, first NMOS tube 101 and second NMOS tube 102 are the NMOS of 8 pin packages Pipe.Wherein, the 1st pin, the 2nd pin and the 3rd pin of first NMOS tube 101 are the source electrode of first NMOS tube 101, described 4th pin of the first NMOS tube 101 be the first NMOS pipes 101 grid, the 5th pin of first NMOS tube 101, the 6th Pin, the 7th pin and the 8th pin are the drain electrode of first NMOS tube 101, the diode D2's inside first NMOS tube 101 Negative electrode is connected with the drain electrode of first NMOS tube 101, the anode of the diode D2 and the source of first NMOS tube 101 Pole connects.The 1st pin, the 2nd pin and the 3rd pin of second NMOS tube 102 are the source electrode of second NMOS tube 102, described 4th pin of the second NMOS tube 102 be second NMOS tube 102 grid, the 5th pin of second NMOS tube 102, the 6th Pin, the 7th pin and the 8th pin are the drain electrode of second NMOS tube 102, the diode D3's inside second NMOS tube 102 Negative electrode is connected with the drain electrode of second NMOS tube 102, the anode of the diode D3 and the source electrode of second NMOS tube 102 Connection.

In the present embodiment, first drive circuit unit 103 includes first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the first NPN triode Q1, the first PNP triode Q2, the 3rd NMOS tube Q3, the first electric capacity C1 and first Diode D1.

Specifically, the 3rd NMOS tube Q3 is the NMOS tube of 3 pin encapsulation, and the grid G of the 3rd NMOS tube Q3 is The input of first drive circuit unit 103, the grid G of the 3rd NMOS tube Q3 respectively with the main control circuit unit 106 the first control output end P1 and the first resistor R1 first end connection, the drain electrode point of the 3rd NMOS tube Q3 It is not connected with the base stage of first NPN triode Q1 and the base stage of the first PNP triode Q2, the 3rd NMOS tube Q3 source electrode and the first resistor R1 the second end are grounded；The colelctor electrode of first NPN triode Q1 and described second Resistance R2 first end connection, the second end of the second resistance R2 are connected with the base stage of first NPN triode Q1, institute State the emitter stage of the first NPN triode Q1 respectively with the emitter stage of the first PNP triode Q2 and the 3rd resistor R3 First end connects；The grounded collector of the first PNP triode Q2；The second end of the 3rd resistor R3 is the described first drive The output end of dynamic circuit unit 103, the second end of the 3rd resistor R3 is connected with the grid of first NMOS tube 101；Institute The first end for stating the 4th resistance R4 is connected with the grid of first NMOS tube 101, the second end of the 4th resistance R4 and institute State the drain electrode connection of the second NMOS tube 102；The first end of the second resistance R2 also the moon with the first diode D1 respectively Pole and the first electric capacity C1 first end connect；The anode of the first diode D1 connects with the power output end VOUT Connect；The second end of the first electric capacity C1 is connected with the second end of the inductance L1.

In the present embodiment, second drive circuit unit 104 includes the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the second NPN triode Q4 and the second PNP triode Q5.

Specifically, the first end of the 5th resistance R5 is the input of second drive circuit unit 104, described the Five resistance R5 first end is connected with the second control output end P2 of the main control circuit unit 106, the 5th resistance R5's Second the end base stage with the second NPN triode Q4, the base stage of the second PNP triode Q5 and the 6th resistance respectively R6 first end connection, the second end ground connection of the 6th resistance R6；The colelctor electrode of the second NPN triode Q4 with it is described Power output end VOUT connections, the emitter stage transmitting with the second PNP triode Q5 respectively of the second NPN triode Q4 Pole and the 7th resistance R7 first end connect；The grounded collector of the second PNP triode Q5；The 7th resistance R7 The second end be second drive circuit unit 104 output end, the second end and described second of the 7th resistance R7 The grid connection of NMOS tube 102, the first end of the 8th resistance R8 is connected with the grid of second NMOS tube 102, described 8th resistance R8 the second end ground connection.

In the present embodiment, the output capacitance array 105 includes 4 electric capacity, respectively electric capacity C5, electric capacity C6, electric capacity C7 And electric capacity C8, the electric capacity C5, electric capacity C6, electric capacity C7 and electric capacity C8 it is parallel with one another after one end and the power output end VOUT Connection, the electric capacity C5, electric capacity C6, electric capacity C7 and electric capacity C8 it is parallel with one another after the other end ground connection.

In the present embodiment, the main control circuit unit 106 includes being used to carry out the voltage of the power output end VOUT The voltage sampling circuit subelement 1061 of sampling and the electricity for being sampled according to the voltage sampling circuit subelement 1061 Pressure and the default target boost value control first drive circuit unit 103 and second drive circuit unit The controller 1062 of 104 work.Wherein, the sampling input of the voltage sampling circuit subelement 1061 exports with the power supply Hold VOUT connections, the sampling input of the sampled output of the voltage sampling circuit subelement 1061 and the controller 1062 (the non-label of figure) connection；The control output end of the controller 1062 includes the first control output end P1 and the second control output end P2, the first control output end P1 of the controller 1062 are connected with the input of first drive circuit unit 103, i.e. institute The the first control output end P1 for stating controller 1062 is connected with the grid G of the 3rd NMOS tube Q3, the controller 1062 The second control output end P2 be connected with the input of second drive circuit unit 104, i.e., the of described controller 1062 Two control output end P2 are connected with the first end of the 5th resistance R5.

In the present embodiment, the voltage sampling circuit subelement 1061 includes the 9th resistance R9 and the tenth resistance R10.Its In, the first end of the 9th resistance R9 is the sampling input of the voltage sampling circuit subelement 1061, the 9th electricity Resistance R9 first end is connected with the power output end VOUT, and the second end of the 9th resistance R9 is the voltage sampling circuit The sampled output of subelement 1061, the second end of the 9th resistance R9 sampling input with the controller 1062 respectively And the first end connection of the tenth resistance R10, the second end ground connection of the tenth resistance R10.

The present embodiment booster circuit also includes being used for the filter circuit for being filtered the voltage of the power input VIN Unit 107, one end of the filter circuit unit 107 are connected with the power input VIN, the filter circuit unit 107 The other end ground connection.Specifically, in the present embodiment, the filter circuit unit 107 include the second electric capacity C2, the 3rd electric capacity C3 and 4th electric capacity C4.Wherein, one end after the second electric capacity C2, the 3rd electric capacity C3 and the 4th electric capacity C4 are parallel with one another It is connected with the power input VIN, the second electric capacity C2, the 3rd electric capacity C3 and the 4th electric capacity C4 are mutually simultaneously Other end ground connection after connection.

The operation principle of the present embodiment booster circuit is described in detail below：In the present embodiment, the basis of controller 1062 The voltage and default target boost value that the voltage sampling circuit subelement 1061 is sampled, from its first control output P1 is held to export the first pwm control signal PWM1 to the input of first drive circuit unit 103, first drive circuit Unit 103 drives the switch motion of first NMOS tube 101 according to the first pwm control signal PWM1 received；Together When, the controller 1062 is electric from its second control output end P2 output drivings of the second pwm control signal PWM2 to described second The input of road unit 104, second drive circuit unit 104 is according to the second pwm control signal PWM2 received The switch motion of second NMOS tube 102 is driven, the inductance L1 is according to first NMOS tube 101 and the 2nd NMOS The switch motion of pipe 102 carries out electrical power storage or electric energy release, the inductance L1 coordinate the output capacitance array 105 to realize again To the boost function of the power input VIN voltage.

Specifically, in the present embodiment, when the voltage difference between the grid and source electrode of second NMOS tube 102 is higher than described During the unlatching threshold value of the second NMOS tube 102, second NMOS tube 102 can turn on；When the grid of second NMOS tube 102 When voltage difference between source electrode is less than the unlatching threshold value of second NMOS tube 102, second NMOS tube 102 then turns off. In the present embodiment, it could be turned on when due to the base stage of the second PNP triode Q5 being low level, and the poles of the 2nd NPN tri- Pipe Q4 base stage could turn on when being high level.Therefore, when the second control output end P2 of the controller 1062 export the When two control signal PWM2 are high level, the second PNP triode Q5 shut-offs, the second NPN triode Q4 conductings, institute The voltage for stating power output end VOUT is directly added to second NMOS tube 102 by the CE knots of the second NPN triode Q4 Grid so that second NMOS tube 102 turns on；And exported as the second control output end P2 of the controller 1062 When second control signal PWM2 is low level, the second NPN triode Q4 shut-offs, the second PNP triode Q5 conductings, from And so that the grid of second NMOS tube 102 is low level so that second NMOS tube 102 turns off.

In the present embodiment, when the voltage difference between the grid and source electrode of first NMOS tube 101 is higher than described first During the unlatching threshold value of NMOS tube 101, first NMOS tube 101 can turn on；Grid and source when first NMOS tube 101 When voltage difference between pole is less than the unlatching threshold value of first NMOS tube 101, first NMOS tube 101 then turns off.This reality Apply in example, could be turned on when due to the base stage of the first PNP triode Q2 being low level, and first NPN triode Q1 Base stage could turn on when being high level.Therefore, when the first control that the first control output end P1 of the controller 1062 is exported When signal PWM1 processed is high level, the 3rd NMOS tube Q3 conducting, the base stage of the first PNP triode Q2 and described the The base stage of one NPN triode Q1 is low level, the first PNP triode Q2 conductings, so that first NMOS tube 101 grid is low level, and first NMOS tube 101 turns off.When the first control output end P1 of the controller 1062 is defeated When the first control signal PWM1 gone out is low level, the 3rd NMOS tube Q3 shut-offs, the base stage of the first PNP triode Q2 And the base stage of first NPN triode Q1 is high level, first NPN triode Q1 conducting, so that described the The grid of one NMOS tube 101 is high level so that first NMOS tube 101 turns on.

The present embodiment booster circuit, when second NMOS tube 102 turns on, and first NMOS tube 101 turns off, institute State inductance L1 and energy storage is carried out to the electric energy of the power input VIN, now by electric capacity C5, electric capacity C6, electric capacity C7 and electric capacity C8 The output capacitance array 105 formed is powered to the power output end VOUT；When first NMOS tube 101 turns on, When second NMOS tube 102 turns off, the inductance L1 discharges electric energy, now the voltage of the power input VIN and described The power output end VOUT is powered after voltage on inductance L1 is superimposed, while the output capacitance array 105 is carried out Charging, now voltage of the voltage of the power output end VOUT far above the power input VIN, the present embodiment are worked as described When first NMOS tube 101 and the persistent switch of the second NMOS tube 102 act, the voltage of the power output end VOUT is with regard to that can reach To default target boost value so that the present embodiment booster circuit realizes the function of boosting.It is understood that the present embodiment Described in default target boost value can be set according to being actually needed.

In the present embodiment, when second NMOS tube 102 turns off, the inductance L1 can produce inverse electromotive force, described Electric current on inductance L1 will not be mutated, but slowly be diminished, and now control first NMOS tube 101 to turn on again, now institute State voltage on power input VIN voltage and the inductance L1 it is superimposed after the power output end VOUT is powered, together When the output capacitance array 105 is charged, now the voltage of the power output end VOUT is equal to the power input VIN voltage and the voltage sum on the inductance L1 are held, here it is the boosting principle of the present embodiment booster circuit.

In addition, it is necessary to illustrate, in the present embodiment, the 7th resistance R7 is the grid of the 2nd NMOS pipes 102 Current-limiting resistance, the 8th resistance R8 are the grid pull down resistor of second NMOS tube 102, second described in when electric in guarantee The grid of NMOS tube 102 is low level, that is, what the second NMOS tube 102 described in when ensureing upper electric was off.Similarly, the present embodiment In, the 3rd resistor R3 is the grid current-limiting resistance of first NMOS tube 101, and the 4th resistance R4 is described first The grid pull down resistor of NMOS tube 101.

Fig. 2 be the embodiment of the utility model booster circuit one described in controller output the first control signal PWM1 and Second control signal PWM2 waveform diagram.In the lump with reference to figure 1 and Fig. 2, the present embodiment booster circuit, when the controller When second pwm control signal PWM2 of 1062 the second control output end P2 outputs is high level, second NMOS tube 102 Conducting, when the second pwm control signal PWM2 that the second control output end P2 of the controller 1062 is exported is low level, institute The second NMOS tube 102 is stated to turn off.Exactly because the conducting of second NMOS tube 102, the power input VIN, the electricity Sense L1 and second NMOS tube 102 can just form loop, and the inductance L1 is carried out to the electric energy of the power input VIN Energy storage.In the present embodiment, the effect of the first electric capacity C1 is primarily to raise the voltage (i.e. described first of a points in Fig. 1 The voltage of the colelctor electrode of NPN triode Q1), so as to ensure that the grid voltage of first NMOS tube 101 is higher than described first The source voltage of NMOS tube 101, realize the conducting of first NMOS tube 101.Specifically, when second NMOS tube 102 is led Logical, when the inductance L1 carries out energy storage to the electric energy of the power input VIN, the second end of the first electric capacity C1 is (corresponding First electric capacity C1 left end described in figure) voltage be low level, the first end of the first electric capacity C1 is (described in corresponding diagram One electric capacity C1 right-hand member) voltage of the magnitude of voltage equal to the power output end VOUT subtract the pressure of the first diode D1 Drop；When second NMOS tube 102 turns off, the inductance L1 can produce inverse electromotive force, and the inductance L1 can be to described One electric capacity C1 charges, and causes the voltage rise of the first end of the first electric capacity C1, and when the first control of the controller 1062 When first pwm control signal PWM1 of output end P1 processed output be low level, the 3rd NMOS tube Q3 is turned off, now a points Voltage Va is added on the grid of first NMOS tube 101 by the CE knots of first NPN triode Q1, and the voltage of a points Va is higher than the source voltage of first NMOS tube 101 so that and first NMOS tube 101 turns on, now, the described 1st Pole pipe D1 plays buffer action.

In summary, the present embodiment booster circuit, when the second control output end P2 of the controller 1062 export the First pwm control signal PWM1 of the first control output end P1 of two pwm control signal PWM2 and the controller 1062 outputs When being simultaneously low level, second NMOS tube 102 turns off, and first NMOS tube 101 turns on, the inductance L1 releases electricity Can, to the power output end after now the voltage on the voltage of the power input VIN and the inductance L1 is superimposed VOUT is powered, while the output capacitance array 105 is charged；As the second control output end P2 of the controller 1062 Second pwm control signal PWM2 of output be low level, the first control output end P1 of the controller 1062 export first When pwm control signal PWM1 is high level, first NMOS tube 101 and second NMOS tube 102 are not turned on；Work as institute State the second control output end P2 outputs of controller 1062 the second pwm control signal PWM2 and the controller 1062 the When first pwm control signal PWM1 of one control output end P1 outputs is simultaneously high level, second NMOS tube 102 turns on, First NMOS tube 101 turns off, and now the inductance L1 carries out energy storage to the electric energy of the power input VIN, described defeated Go out capacitor array 105 to power to the power output end VOUT ends.

The present embodiment booster circuit, due to driving first drive circuit of the switch motion of the first NMOS tube 101 Unit 103 and second drive circuit unit 104 of the driving switch motion of the second NMOS tube 102 are by simple Component is formed, and instead of the scheme for using MOSFET driving chips in the prior art, therefore, the present embodiment booster circuit can While meeting that boosting requires and improves load capacity, the cost of circuit is reduced；Also, the present embodiment can also improve liter Press efficiency and power output；Meanwhile the present embodiment also have it is simple in construction and the advantages of easily realize.

Preferred embodiment of the present utility model is these are only, not thereby limits the scope of the claims of the present utility model, it is every The equivalent structure or equivalent flow conversion made using the utility model specification and accompanying drawing content, or be directly or indirectly used in Other related technical areas, similarly it is included in scope of patent protection of the present utility model.

Claims

1. a kind of booster circuit, it is characterised in that the booster circuit includes power input, power output end, the first NMOS Pipe, the second NMOS tube, the first drive circuit unit for driving the first NMOS tube switch motion, for driving described Second drive circuit unit of two NMOS tube switch motions, for opening according to first NMOS tube and second NMOS tube Pass action carries out electrical power storage or the releasable inductance of electricity, discharged for the electric energy to the power input and the inductance Electric energy stored, the power output end is powered and the voltage of the power output end is filtered defeated Go out capacitor array and for first driving of the voltage according to the power output end and the control of default target boost value Circuit unit and the main control circuit unit of second drive circuit unit work；Wherein：

The power input is connected with the first end of the inductance, the second end of inductance source with the first NMOS tube respectively The drain electrode connection of pole and the second NMOS tube, drain one end with the output capacitance array and the institute respectively of first NMOS tube State power output end connection, the other end ground connection of the output capacitance array, the grid of first NMOS tube and described first The output end connection of drive circuit unit；The source ground of second NMOS tube, the grid of second NMOS tube with it is described The output end connection of second drive circuit unit；The input of first drive circuit unit and the second drive circuit list Control output end of the input of member with the main control circuit unit is connected；The sampling input of the main control circuit unit with The power output end connection.

2. booster circuit as claimed in claim 1, it is characterised in that first drive circuit unit include first resistor, Second resistance, 3rd resistor, the 4th resistance, the first NPN triode, the first PNP triode, the 3rd NMOS tube, the first electric capacity and First diode；Wherein：

The grid of 3rd NMOS tube is the input of first drive circuit unit, and the grid of the 3rd NMOS tube divides It is not connected with the control output end of the main control circuit unit and the first end of the first resistor, the leakage of the 3rd NMOS tube Pole is connected with the base stage of first NPN triode and the base stage of first PNP triode respectively, the 3rd NMOS tube Second end of source electrode and the first resistor is grounded；The of the colelctor electrode of first NPN triode and the second resistance One end is connected, and the second end of the second resistance is connected with the base stage of first NPN triode, first NPN triode Emitter stage be connected respectively with the emitter stage of first PNP triode and the first end of the 3rd resistor；First PNP The grounded collector of triode；Second end of the 3rd resistor is the output end of first drive circuit unit, described the Second end of three resistance is connected with the grid of first NMOS tube；The first end of 4th resistance and first NMOS tube Grid connection, the second end of the 4th resistance is connected with the drain electrode of second NMOS tube；The first of the second resistance End is also connected with the negative electrode of first diode and the first end of first electric capacity respectively；The anode of first diode It is connected with the power output end；Second end of first electric capacity is connected with the second end of the inductance.

3. booster circuit as claimed in claim 1, it is characterised in that second drive circuit unit include the 5th resistance, 6th resistance, the 7th resistance, the 8th resistance, the second NPN triode and the second PNP triode；Wherein：

The first end of 5th resistance be second drive circuit unit input, the first end of the 5th resistance with The control output end connection of the main control circuit unit, the second end of the 5th resistance respectively with second NPN triode Base stage, the connection of the first end of the base stage of second PNP triode and the 6th resistance, the second end of the 6th resistance Ground connection；The colelctor electrode of second NPN triode is connected with the power output end, the emitter stage of second NPN triode It is connected respectively with the emitter stage of second PNP triode and the first end of the 7th resistance；Second PNP triode Grounded collector；Second end of the 7th resistance is the output end of second drive circuit unit, the 7th resistance Second end is connected with the grid of second NMOS tube, and the first end of the 8th resistance connects with the grid of second NMOS tube Connect, the second end ground connection of the 8th resistance.

4. booster circuit as claimed in claim 1, it is characterised in that the output capacitance array includes at least two electric capacity, institute State one end after at least two electric capacity parallel connection to be connected with the power output end, another termination after at least two electric capacity parallel connection Ground.

5. booster circuit as claimed in claim 1, it is characterised in that the main control circuit unit includes being used for the power supply Voltage sampling circuit subelement that the voltage of output end is sampled and for being adopted according to the voltage sampling circuit subelement The voltage and the default target boost value that sample arrives control first drive circuit unit and second drive circuit The controller of cell operation；Wherein：

The sampling input of the voltage sampling circuit subelement is connected with the power output end, voltage sampling circuit The sampled output of unit is connected with the sampling input of the controller；The control output end of the controller includes the first control Output end processed and the second control output end, the first control output end of the controller are defeated with first drive circuit unit Enter end connection, the second control output end of the controller is connected with the input of second drive circuit unit.

6. booster circuit as claimed in claim 5, it is characterised in that the voltage sampling circuit subelement includes the 9th resistance With the tenth resistance；Wherein：

The first end of 9th resistance is the sampling input of the voltage sampling circuit subelement, the of the 9th resistance One end is connected with the power output end, and the second end of the 9th resistance is defeated for the sampling of the voltage sampling circuit subelement Go out end, the second end of the 9th resistance connects with the sampling input of the controller and the first end of the tenth resistance respectively Connect, the second end ground connection of the tenth resistance.

7. the booster circuit as any one of claim 1 to 6, it is characterised in that the booster circuit also includes being used for The filter circuit unit being filtered to the voltage of the power input, one end and the power supply of the filter circuit unit Input connects, the other end ground connection of the filter circuit unit.

8. booster circuit as claimed in claim 7, it is characterised in that the filter circuit unit includes the second electric capacity, the 3rd Electric capacity and the 4th electric capacity；Wherein：

Second electric capacity, the 3rd electric capacity and the 4th electric capacity it is parallel with one another after one end and the power input connect Connect, second electric capacity, the 3rd electric capacity and the 4th electric capacity it is parallel with one another after the other end ground connection.