Detailed Description
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. It may be evident, however, that such embodiment(s) may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more embodiments.
An equipment is connected respectively at the both ends of OTG line, and one of them is master equipment, and another is slave unit, the utility model discloses use master equipment to explain OTG's power supply control system as the example, the slave unit can be obtained by reason.
Fig. 1 shows a structure of a power supply control system of an OTG according to an embodiment of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a control device for an OTG, including: the CPU1, the micro USB interface 2, the voltage output control module, and the voltage input control module are described below.
CPU1 includes OTG _ DN pin, OTG _ DP pin, USB _ OTG _ ID pin, OTG _ POW _ EN pin and P5V0_ OTG _ VBUS pin, and CPU1 needs an accurate power supply order the utility model discloses in only need two power supply voltages of 5V and 3.3V in the power supply order.
The micro USB interface 2 is used for being connected with equipment through an OTG (over the go) line, and the micro USB interface 2 comprises a D + pin, a D-pin, an ID (identity) pin, a VBUS (voltage source bus) pin and a GND (ground) pin.
The voltage output control module is used for controlling the connection or disconnection of the voltage output by the CPU1 to the slave device, and includes a first P-channel enhancement MOS (meta Oxide semiconductor) transistor 3, which is fully called a metal Oxide semiconductor field effect transistor.
The voltage input control module is used for connecting the 5V voltage output to the slave device to the CPU1, connecting the 5V voltage input by the master device to the CPU1 when the master device is switched to the slave device, and disconnecting the 5V voltage connected to the CPU1 when the master device is switched to the slave device and the CPU1 stops working. The voltage input control module comprises an N-channel enhancement type MOS tube 4 and a second P-channel enhancement type MOS tube 5.
The above description has been made on the structure of the five components of the power supply control system of the OTG, and the connection manner between the five components of the power supply control system of the OTG will be described in detail below.
Referring to fig. 1, an OTG _ DN pin of the CPU1 is connected to a D-pin of the micro USB interface 2, and an OTG _ DP pin of the CPU is connected to a D + pin of the micro USB interface, thereby implementing differential data transmission between the CPU1 and the micro USB interface 2.
The USB _ OTG _ ID pin of the CPU1 is connected with the ID pin of the micro USB interface, the ID pin of the micro USB interface 2 is used for detecting whether the device inserted into the micro USB interface 2 is a master device or a slave device, the master device and the slave device both comprise the micro USB interface 2, between the two devices, the default device with the grounded ID pin of the micro USB interface 2 is the master device, namely, when the ID pin of the micro USB interface 2 corresponding to the CPU1 is grounded, the device inserted into the micro USB interface 2 is detected to be the slave device, and when the ID pin of the micro USB interface 2 corresponding to the CPU1 is floating, the device identified as being inserted into the micro USB interface 2 is the master device.
It should be noted that the ID pin of the micro USB interface 2 is detected only when the CPU1 is operating, and the micro USB interface 2 is inserted into any device and is not detected when the CPU1 stops operating.
An OTG _ POW _ EN pin of the CPU1 is connected with a grid electrode of a first P-channel enhancement type MOS tube 3, a source electrode of the first P-channel enhancement type MOS tube 3 is connected with a 5V power supply of the CPU1, a drain electrode of the first P-channel enhancement type MOS tube 3 is connected with a VBUS pin of the micro USB interface 2, and a substrate of the first P-channel enhancement type MOS tube 3 is grounded.
The OTG _ POW _ EN pin is an enable pin of the CPU1, and outputs a low level to be valid and a high level to be invalid, and when the OTG _ POW _ EN pin of the CPU1 outputs a low level, the source and the drain of the first P-channel enhancement type MOS transistor 3 are turned on, so that the 5V power supply of the CPU1 is connected to the VBUS pin of the micro USB interface 2, and a 5V voltage is output to the slave device through the VBUS pin of the micro USB interface 2.
A first resistor 6 is connected in parallel between the gate and the source of the first P-channel enhancement type MOS transistor, the first resistor 6 is in a high level state, that is, a non-output state, of the OTG _ POW _ EN pin of the default CPU1, and the on or off of the first P-channel enhancement type MOS transistor is controlled by the high and low level state output by the OTG _ POW _ EN pin of the CPU1, so that the voltage output control module is controlled to be in an on state or an off state.
A P5V0_ OTG _ VBUS pin of the CPU1 is connected with a drain electrode of a second P-channel enhancement type MOS tube 5, a grid electrode of the second P-channel enhancement type MOS tube 5 is connected with a drain electrode of an N-channel enhancement type MOS tube 4, a source electrode of the second P-channel enhancement type MOS tube 5 is connected with a VBUS pin of the micro USB interface 2, a substrate of the second P-channel enhancement type MOS tube 5 is connected with the source electrode, a first Schottky diode 12 is connected in parallel between the source electrode and the drain electrode of the second P-channel enhancement type MOS tube 5, an anode of the first Schottky diode 12 is connected with the drain electrode of the second P-channel enhancement type MOS tube 5, and a cathode of the first Schottky diode 12 is connected with the source electrode of the second P-channel enhancement type MOS tube 5 to play a role in protecting the second P-channel enhancement type MOS tube 5.
A second resistor 7 is connected in parallel between the source and the gate of the second P-channel enhancement type MOS transistor 5, and the second resistor 7 is in a high level state, that is, a non-output state, of the VBUS pin of the default micro USB interface 2.
A first capacitor 9 is connected in parallel between the drain and the gate of the second P-channel enhancement type MOS transistor, and the first capacitor 9 plays a role of filtering.
The source electrode of the N-channel enhanced MOS tube 4 is connected with the substrate of the N-channel enhanced MOS tube 4 and then grounded, and the grid electrode of the N-channel enhanced MOS tube 4 is connected with a 3.3V power supply of the CPU1 through a third resistor 8. When the CPU1 works, the 3.3V power supply always provides 3.3V voltage for the CPU1, and the 3.3V voltage is in a low level, namely an output state; when the 3.3V power supply is disconnected, the N-channel enhancement type MOS transistor 4 is turned off, the second P-channel enhancement type MOS transistor 5 is turned off, the P5V0_ OTG _ VBUS of the CPU1 is disconnected from the VBUS of the microUSB interface 2, and the CPU1 stops working.
When the CPU1 works, the N-channel enhancement type MOS transistor 4 is turned on, and the drain of the N-channel enhancement type MOS transistor 4 is connected to the gate of the second P-channel enhancement type MOS transistor 5, so as to turn on the second P-channel enhancement type MOS transistor 5, at this time, the voltage input control module is in an on state, the 5V voltage output from the VBUS pin of the micro USB interface 2 to the slave is connected to the P5V0_ OTG _ VBUS pin of the CPU1 through the voltage input control module, specifically, the 5V voltage output from the VBUS pin of the micro USB interface 2 to the slave is connected to the P5V0_ OTG _ VBUS pin of the CPU1 through the second P-channel enhancement type MOS transistor 5, the N-channel enhancement type MOS transistor 4 is in an on state, the second P-channel enhancement type MOS transistor 5 is also in an on state, and the N-channel enhancement type MOS transistor 4 is in an off state, the second P-channel enhancement type MOS transistor 5 is also in an off state, that is, the state of the second P-channel enhancement type MOS transistor 5 is the same as the state of the N-channel enhancement type MOS transistor 4.
When the CPU1 stops working, the N-channel enhancement type MOS transistor 4 is turned off, and the drain of the N-channel enhancement type MOS transistor 4 is connected to the gate of the second P-channel enhancement type MOS transistor 5, so that the second P-channel enhancement type MOS transistor 5 is turned off, and the voltage input control module is in an off state, and when the micro USB interface 2 is connected to a master device, the 5V voltage provided by the master device to the P5V0_ OTG _ VBUS pin of the CPU1 is turned off due to the fact that the voltage input control module is in the off state.
The utility model discloses well CPU1 stop work indicates the condition of CPU1 power failure back dormancy.
A second schottky diode 13 is connected in parallel between the source and the drain of the N-channel enhancement type MOS transistor, the anode of the second schottky diode 13 is connected with the source of the N-channel enhancement type MOS transistor 13 and then grounded, and the cathode of the second schottky diode 13 is connected with the drain of the N-channel enhancement type MOS transistor 13, so that the N-channel enhancement type MOS transistor 13 is prevented from being damaged due to the fact that the drain voltage of the N-channel enhancement type MOS transistor 13 is lower than the source voltage, and the source 13 of the N-channel enhancement type MOS transistor is protected.
The GND pin of the micro USB interface 2 is grounded; and the VBUS pin of the micro USB interface 2 is grounded through a second capacitor 10, and the second capacitor 10 plays a role in filtering.
The above details describe the structure of the power supply control system of the OTG provided by the present invention. The process of controlling the VBUS voltage of the master device and the slave device by using the power supply control system of the OTG includes the following three conditions:
the first case is: when the CPU works and the micro USB interface is connected to the slave equipment, the OTG _ POW _ EN pin of the CPU outputs a low level, a first P-channel enhanced MOS tube of the voltage output control module is conducted, a 5V power supply of the CPU is connected with a VBUS pin of the micro USB interface, and 5V voltage is output to the slave equipment through the VBUS pin of the micro USB interface; and connecting the 5V voltage to a P5V0_ OTG _ VBUS pin of the CPU through a second P channel enhancement type MOS tube of the voltage input control module.
The first case is that the master device supplies power to the slave device through the micro USB interface, the power supply voltage is 5V, and the power supply voltage is connected to the P5V0_ OTG _ VBUS pin of the CPU.
The second case is: when the CPU works and the micro USB interface is connected to the main equipment, the OTG _ POW _ EN pin of the CPU outputs a high level, the first P-channel enhanced MOS tube is cut off, and a 5V power supply of the CPU is disconnected with the VBUS pin of the micro USB interface; and connecting the 5V voltage output by the main equipment to a P5V0_ OTG _ VBUS pin of the CPU through a second P-channel enhancement type MOS tube.
The second case is that the master device is switched to the slave device, the 5V voltage output outwards is disconnected, the 5V voltage provided by the master device to the slave device is received, and the 5V voltage is connected to the P5V0_ OTG _ VBUS pin of the CPU of the slave device.
The third case is: when the CPU stops working, the 3.3V power supply of the CPU is disconnected, and the micro USB interface is connected to the main equipment, the 5V power supply of the CPU is disconnected with the VBUS pin of the micro USB interface by stopping the first P-channel enhanced MOS tube; and the second P-channel enhancement type MOS tube is cut off by cutting off the N-channel enhancement type MOS tube of the voltage input control module, and the 5V voltage of the main equipment connected to the P5V0_ OTG _ VBUS pin of the CPU is disconnected.
When the CPU of the slave device stops operating, the master device supplies power to the CPU of the slave device again, which may burn out the CPU of the slave device. Therefore, when the CPU of the slave device stops operating, it is necessary to disconnect the voltage supplied from the master device to the slave device.
When the CPU of the slave device stops working, the 3.3V power supply for supplying power to the slave device is automatically disconnected and changed into a non-output state, so that the N-channel enhancement type MOS tube is cut off, the second P-channel enhancement type MOS tube is cut off, the voltage input control module is in a disconnected state, and the 5V voltage on the P5V0_ OTG _ VBUS pin of the CPU of the slave device connected to the master device is disconnected.
The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present invention, and all should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.