CN206532770U - The new SOP structures of chip package - Google Patents
The new SOP structures of chip package Download PDFInfo
- Publication number
- CN206532770U CN206532770U CN201720164465.XU CN201720164465U CN206532770U CN 206532770 U CN206532770 U CN 206532770U CN 201720164465 U CN201720164465 U CN 201720164465U CN 206532770 U CN206532770 U CN 206532770U
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- CN
- China
- Prior art keywords
- chip
- metal pad
- side pin
- several
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 59
- 239000002184 metal Substances 0.000 claims abstract description 59
- 239000006071 cream Substances 0.000 claims abstract description 19
- 238000003860 storage Methods 0.000 claims abstract description 19
- 238000005253 cladding Methods 0.000 claims abstract description 15
- 239000003822 epoxy resin Substances 0.000 claims abstract description 15
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 15
- 241000218202 Coptis Species 0.000 claims description 10
- 235000002991 Coptis groenlandica Nutrition 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 239000003292 glue Substances 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract description 4
- 238000012545 processing Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005485 electric heating Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004021 metal welding Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model discloses a kind of new SOP structures of chip package, including chip, metal pad, several left side pins, several right side pins and epoxy resin cladding, the chip is fixed on the middle section of metal pad upper surface by heat conductive insulating glue-line, it is arranged at the left side of chip several left side pin spacing side by side, it is arranged at the right side of chip several right side pin spacing side by side, the metal pad its lower edge is provided with the first gap slot, and the left side pin is provided with the second gap slot with the opposite medial extremity bottom of metal pad；The metal pad upper surface is provided with the annular storage cream groove of a closure along edge, and the cross sectional shape of this annular storage cream groove is inverted trapezoidal, and this annular storage cream groove is located at immediately below chip and close to the fringe region of chip.The utility model effectively prevent thermal conductive insulation glue it is excessive caused by short trouble, improve finished product rate so that processing it is more simple and convenient, improve the stability and reliability of integrated chip.
Description
Technical field
The utility model is related to a kind of chip-packaging structure, is related to technical field of semiconductors.
Background technology
In recent decades, chip encapsulation technology is always with the development of integrated circuit technique.Encapsulating structure refers to
The shell of semiconductor integrated circuit chip, it not only plays installation, fixation, sealing, protection chip and enhancing electric heating property etc.
The effect of aspect, but also be wired to by the contact on chip on the pin of package casing, these pins further through
Wire on printed circuit board (PCB) is connected with other devices.Therefore, encapsulating structure generally comprise for installing, fixed and lead
Lead frame, while also including the packaging body for being used to protect chip, seal and with lead frame match.
The encapsulating structure of traditional SOP classes uses total incapsulation design, without exposed radiator structure, mainly passes through modeling
Envelope material radiating, and the poor heat dispersion for causing such a encapsulation of the heat conductivility of plastic packaging material is poor.Power it is increasing, encapsulation
Under the less and less demand of size, the radiating shortcoming of traditional SOP structures is more and more obvious.In addition, some chip products need
Two mutually isolated chips are encapsulated in an encapsulating structure.
The content of the invention
The utility model purpose is to provide a kind of new SOP structures of chip package, the new SOP structures of the chip package
Effectively prevent thermal conductive insulation glue it is excessive caused by short trouble, improve finished product rate so that processing it is more simple
Folk prescription just, improves the stability and reliability of integrated chip.
To reach above-mentioned purpose, the technical solution adopted in the utility model is：A kind of new SOP structures of chip package,
Including chip, metal pad, several left side pins, several right side pins and epoxy resin cladding, the chip passes through
Heat conductive insulating glue-line is fixed on the middle section of metal pad upper surface, is arranged at several left side pin spacing side by side
The left side of chip, is arranged at the right side of chip, the metal pad lower edge several right side pin spacing side by side
Place is provided with the first gap slot, and the left side pin is provided with the second gap slot, the right side with the opposite medial extremity bottom of metal pad
Side pin and the opposite medial extremity bottom of metal pad are provided with the 3rd gap slot, the epoxy resin cladding be coated on chip,
Metal pad, several left side pins, several right side pins on, the metal pad, left side pin and right side pin are each
Lower surface expose the bottom of epoxy resin cladding；
Some first gold thread two ends are electrically connected with chip and left side pin respectively, some second gold thread two ends respectively with
Chip and the electrical connection of right side pin, the metal pad upper surface are provided with the annular storage cream groove of a closure, this annular storage along edge
The cross sectional shape of cream groove is inverted trapezoidal, and this annular storage cream groove is located at immediately below chip and close to the fringe region of chip.
Further improved scheme is as follows in above-mentioned technical proposal：
1. in such scheme, the left side pin, the metal-coated coating of lower surface of right side pin.
2. in such scheme, the coat of metal is tin layers or NiPdAu layer.
3. in such scheme, the thickness ratio of the coat of metal and left side pin or right side pin is 1：6~12.
4. in such scheme, the number of the left side pin and right side pin is 3 ~ 10.
Because above-mentioned technical proposal is used, the utility model has following advantages compared with prior art：
1. the new SOP structures of the utility model chip package, its metal pad its lower edge is provided with the first breach
Groove, the left side pin is provided with the second gap slot, the right side pin and metal welding with the opposite medial extremity bottom of metal pad
The opposite medial extremity bottom of disk is provided with the 3rd gap slot, is conducive to pin and metal pad being more firmly fixed, improves
The reliability welded between PCB；Secondly, its chip is fixed on the central area of metal pad upper surface by heat conductive insulating glue-line
Domain, metal pad, left side pin and the respective lower surface of right side pin expose the bottom of epoxy resin cladding, exposed gold
Belong to pad, so that chip operationally quickly conducts heat, good heat dissipation effect.
2. the new SOP structures of the utility model chip package, its metal pad upper surface is provided with a closure along edge
Annular storage cream groove, the cross sectional shape of this annular storage cream groove is inverted trapezoidal, and this annular storage cream groove is located at immediately below chip and close to core
The fringe region of piece, effectively prevent thermal conductive insulation glue it is excessive caused by short trouble, improve finished product rate so that plus
Work production is more simple and convenient, improves the stability and reliability of integrated chip.
3. the new SOP structures of the utility model chip package, its left side pin, the lower surface of right side pin are plated with
The coat of metal, had both reduced device and PCB conductive contact resistance, the raising for the weld strength being also beneficial between PCB.
Brief description of the drawings
Accompanying drawing 1 is the new SOP structures structural representation of the utility model chip package；
Accompanying drawing 2 is the A-A cross-sectional views of accompanying drawing 1.
In the figures above：1st, chip；2nd, metal pad；3rd, left side pin；4th, right side pin；5th, epoxy resin cladding；
6th, heat conductive insulating glue-line；7th, the first gap slot；8th, the second gap slot；9th, the 3rd gap slot；10th, annular storage cream groove；11st, metal-plated
Layer；15th, the first gold thread；16th, the second gold thread.
Embodiment
Below in conjunction with the accompanying drawings and embodiment is further described to the utility model：
Embodiment 1：A kind of new SOP structures of chip package, including chip 1, metal pad 2, several left side pins
3rd, several right side pins 4 and epoxy resin cladding 5, the chip 1 are fixed on metal pad 2 by heat conductive insulating glue-line 6
The middle section of upper surface, is arranged at the left side of chip 1, several described right sides several spacing side by side of left side pin 3
It is arranged at the right side of chip 1, its lower edge of metal pad 2 is provided with the first gap slot 7, institute the spacing side by side of side pin 4
State left side pin 3 and be provided with the second gap slot 8, the right side pin 4 and metal pad with the opposite medial extremity bottom of metal pad 2
2 opposite medial extremity bottoms are provided with the 3rd gap slot 9, if the epoxy resin cladding 5 be coated on chip 1, metal pad 2,
On dry individual left side pin 3, several right side pins 4, the metal pad 2, left side pin 3 and the respective following table of right side pin 4
Face exposes the bottom of epoxy resin cladding 5；
Some two ends of first gold thread 15 are electrically connected with chip 1 and left side pin 3 respectively, some two ends of second gold thread 16
Electrically connected respectively with chip 1 and right side pin 4, the upper surface of metal pad 2 is provided with the annular storage cream groove of a closure along edge
10, the cross sectional shape of this annular storage cream groove 10 is inverted trapezoidal, and this annular storage cream groove 10 is located at immediately below chip 1 and close to chip 1
Fringe region.
The metal-coated coating 11 of lower surface of above-mentioned left side pin 3, right side pin 4, the above-mentioned coat of metal 11 is tin layers.
The thickness ratio of the above-mentioned coat of metal 11 and left side pin 3 or right side pin 4 is 1：7.
The number of above-mentioned left side pin 3 and right side pin 4 is 4.
Embodiment 2：A kind of new SOP structures of chip package, including chip 1, metal pad 2, several left side pins
3rd, several right side pins 4 and epoxy resin cladding 5, the chip 1 are fixed on metal pad 2 by heat conductive insulating glue-line 6
The middle section of upper surface, is arranged at the left side of chip 1, several described right sides several spacing side by side of left side pin 3
It is arranged at the right side of chip 1, its lower edge of metal pad 2 is provided with the first gap slot 7, institute the spacing side by side of side pin 4
State left side pin 3 and be provided with the second gap slot 8, the right side pin 4 and metal pad with the opposite medial extremity bottom of metal pad 2
2 opposite medial extremity bottoms are provided with the 3rd gap slot 9, if the epoxy resin cladding 5 be coated on chip 1, metal pad 2,
On dry individual left side pin 3, several right side pins 4, the metal pad 2, left side pin 3 and the respective following table of right side pin 4
Face exposes the bottom of epoxy resin cladding 5；
Some two ends of first gold thread 15 are electrically connected with chip 1 and left side pin 3 respectively, some two ends of second gold thread 16
Electrically connected respectively with chip 1 and right side pin 4, the upper surface of metal pad 2 is provided with the annular storage cream groove of a closure along edge
10, the cross sectional shape of this annular storage cream groove 10 is inverted trapezoidal, and this annular storage cream groove 10 is located at immediately below chip 1 and close to chip 1
Fringe region.
The metal-coated coating 11 of lower surface of above-mentioned left side pin 3, right side pin 4, the above-mentioned coat of metal 11 is nickel palladium
Layer gold.
The thickness ratio of the above-mentioned coat of metal 11 and left side pin 3 or right side pin 4 is 1：9.
The number of above-mentioned left side pin 3 and right side pin 4 is 6.
During the new SOP structures encapsulated using said chip, it is conducive to pin and metal pad is more solid
It is fixed, improve the reliability welded between PCB；Secondly, its exposed metal pad, so that chip operationally quickly conducts
Heat, good heat dissipation effect；Again, effectively prevent thermal conductive insulation glue it is excessive caused by short trouble, improve finished product
Rate；So that processing is more simple and convenient, the stability and reliability of integrated chip are improved.
Above-described embodiment is only to illustrate technical concepts and features of the present utility model, and its object is to allow be familiar with technique
Personage can understand content of the present utility model and implement according to this, protection domain of the present utility model can not be limited with this.
All equivalent change or modifications made according to the utility model Spirit Essence, should all cover protection domain of the present utility model it
It is interior.
Claims (5)
1. a kind of new SOP structures of chip package, it is characterised in that：Including chip（1）, metal pad（2）, several left side
Pin（3）, several right side pins（4）With epoxy resin cladding（5）, the chip（1）Pass through heat conductive insulating glue-line（6）Gu
Due to metal pad（2）The middle section of upper surface, several described left side pins（3）It is arranged at chip spacing side by side（1）
Left side, several described right side pins（4）It is arranged at chip spacing side by side（1）Right side, the metal pad（2）Bottom
Edge is provided with the first gap slot（7）, the left side pin（3）With metal pad（2）Opposite medial extremity bottom is provided with second
Gap slot（8）, the right side pin（4）With metal pad（2）Opposite medial extremity bottom is provided with the 3rd gap slot（9）, it is described
Epoxy resin cladding（5）It is coated on chip（1）, metal pad（2）, several left side pins（3）, several right side pins
（4）On, the metal pad（2）, left side pin（3）With right side pin（4）Respective lower surface exposes epoxy resin cladding
Body（5）Bottom；
Some first gold threads（15）Two ends respectively with chip（1）With left side pin（3）Electrical connection, some second gold threads（16）
Two ends respectively with chip（1）With right side pin（4）Electrical connection, the metal pad（2）Upper surface is provided with a closure along edge
Annular storage cream groove（10）, this annular storage cream groove（10）Cross sectional shape be inverted trapezoidal, this annular storage cream groove（10）Positioned at chip（1）
Underface and close chip（1）Fringe region.
2. the new SOP structures of chip package according to claim 1, it is characterised in that：The left side pin（3）, it is right
Side pin（4）The metal-coated coating of lower surface（11）.
3. the new SOP structures of chip package according to claim 2, it is characterised in that：The coat of metal（11）For
Tin layers or NiPdAu layer.
4. the new SOP structures of chip package according to claim 2, it is characterised in that：The coat of metal（11）With
Left side pin（3）Or right side pin（4）Thickness ratio be 1：6~12.
5. the new SOP structures of chip package according to claim 2, it is characterised in that：The left side pin（3）And the right side
Side pin（4）Number be 3 ~ 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720164465.XU CN206532770U (en) | 2017-02-23 | 2017-02-23 | The new SOP structures of chip package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720164465.XU CN206532770U (en) | 2017-02-23 | 2017-02-23 | The new SOP structures of chip package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206532770U true CN206532770U (en) | 2017-09-29 |
Family
ID=59920057
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720164465.XU Expired - Fee Related CN206532770U (en) | 2017-02-23 | 2017-02-23 | The new SOP structures of chip package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206532770U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037182A (en) * | 2018-09-12 | 2018-12-18 | 深圳三地芯电子有限责任公司 | Chip-packaging structure and memory device |
-
2017
- 2017-02-23 CN CN201720164465.XU patent/CN206532770U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037182A (en) * | 2018-09-12 | 2018-12-18 | 深圳三地芯电子有限责任公司 | Chip-packaging structure and memory device |
| CN109037182B (en) * | 2018-09-12 | 2024-05-03 | 深圳三地一芯电子股份有限公司 | Chip packaging structure and memory device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170929 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |