CN206452327U - A kind of H bridges motor driver and motor device - Google Patents
A kind of H bridges motor driver and motor device Download PDFInfo
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- CN206452327U CN206452327U CN201720030939.1U CN201720030939U CN206452327U CN 206452327 U CN206452327 U CN 206452327U CN 201720030939 U CN201720030939 U CN 201720030939U CN 206452327 U CN206452327 U CN 206452327U
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Abstract
The utility model discloses a kind of H bridges motor driver and motor device, including H bridge commutating circuits：Including the first PMOS, the second PMOS, the first NMOS tube and the second NMOS tube, the first PMOS and the second NMOS tube constitute the first path, and the second PMOS and the first NMOS tube constitute alternate path；The grid of first PMOS and the second PMOS is connected to first switch circuit and second switch circuit；Also include the 3rd on-off circuit, the 4th on-off circuit and control circuit, 3rd on-off circuit includes the first nor gate, 4th on-off circuit includes the second nor gate, circuit is controlled to include the 3rd nor gate, the two inputs connection pwm signal of 3rd nor gate, one input of output the first nor gate of termination and an input of the second nor gate, another input of the first nor gate terminate the first low and high level signal, the grid of output the first NMOS tube of termination of the first nor gate；Another input of second nor gate terminates the second low and high level signal, the grid of output the second NMOS tube of termination of the second nor gate.
Description
Technical field
The utility model is related to electric machines control technology, more particularly to a kind of H bridges motor driver and motor device.
Background technology
At present, the control to motor is main by following two schemes：
One kind is to use H bridge architectures, and NMOS1-NMOS4, additional two special chips are constituted by four N-channel FETs
Driving, operation principle is that single-chip microcomputer provides double switch pulse signal PWM1, PWM2, during output PWM1 (PWM2 is set low),
NMOS1, NMOS4 are turned on, and NMOS2, NMOS3 cut-off, motor are rotated forward；When exporting PWM2 (PWM1 is set low), NMOS2, NMOS3 are led
Logical, NMOS1, NMOS4 cut-off, motor reversal, by changing PWM1, PWM2 dutycycle, adjust the rotating speed of motor.The program
Advantage is non-relay interference, and Electro Magnetic Compatibility is preferable；Have the disadvantage that each motor need to take two PWM mouthfuls, to single-chip microcomputer type selecting
It is required that high, cost is high.
Another is to be combined to constitute with a N communication FET by a dpdt relay, and operation principle is：Electricity
When machine works, the adhesive by control relay realizes the rotating of motor with disconnection；By adjusting PWM dutycycle, control
The make-and-break time of FET processed, realizes the speed governing of motor.The advantage of the program is simple circuit, and cost is low, and weak point is
Relay has noise, and Electro Magnetic Compatibility is poor.
Utility model content
The utility model provides a kind of H bridges motor driver and motor device, for overcoming the motor of prior art to drive
Weak point present in dynamic device.
The utility model solves the technical scheme that its technical problem used：A kind of H bridges motor driver, including H bridges
Commutating circuit, the H bridges commutating circuit includes connection motor and the first PMOS positioned at high-end upper left, the positioned at high-end upper right
Two PMOSs, the first NMOS tube positioned at low side lower-left and the second NMOS tube positioned at low side bottom right, the first PMOS and second
NMOS tube constitutes the first path, and the second PMOS and the first NMOS tube constitute alternate path；First PMOS and the second PMOS
Grid be connected to first switch circuit and second switch circuit；Also include the 3rd on-off circuit, the 4th on-off circuit and
Circuit is controlled, the 3rd on-off circuit includes the first nor gate, and the 4th on-off circuit includes the second nor gate, and control circuit includes the
Three nor gates, the 3rd nor gate two inputs connection pwm signal, output termination the first nor gate an input and second or
One input of NOT gate, another input of the first nor gate terminates the first low and high level signal, the output termination of the first nor gate
The grid of first NMOS tube；Another input of second nor gate terminates the second low and high level signal, the second low and high level signal
It is opposite with the first low and high level signal phase in motor forward or reverse state；The output of second nor gate terminates the second NMOS tube
Grid.
Further, the 3rd on-off circuit also includes resistance R3, resistance R7 and electric capacity C3, and resistance R3 is connected to first
Between the output end of the grid of NMOS tube and the first nor gate, resistance R7 and electric capacity C3 are connected in the grid of the first NMOS tube in parallel
Between source electrode；4th on-off circuit also includes resistance R4, resistance R8 and electric capacity C4, and resistance R4 is connected to the second NMOS tube
Grid and the second nor gate output end between, resistance R8 and electric capacity C4 are connected in the grid and source electrode of the second NMOS tube in parallel
Between.
Further, the 3rd on-off circuit also includes magnetic bead S1, and magnetic bead S1 is connected to the grid of the first NMOS tube
And first nor gate output end between；4th on-off circuit also includes magnetic bead S2, and magnetic bead S2 is connected to the 2nd NMOS
Between the output end of the grid of pipe and the second nor gate.
Further, the first switch circuit and second switch circuit are respectively transistor switching circuit, and first opens
Powered-down road connects the first low and high level signal, and second switch circuit connects the second low and high level signal.
Further, the first switch circuit includes triode Q1, resistance R1, electric capacity C1, voltage-regulator diode ZD1, electricity
R5, resistance R9, resistance R13, resistance R15 are hindered, resistance R1, electric capacity C1, voltage-regulator diode ZD1 are connected in power vd D and the in parallel
Between the grid of one PMOS, triode Q1 colelctor electrode passes through resistance R9, the grid of resistance R5 the first PMOSs of connection, three poles
Pipe Q1 base stage is connected by resistance R13 connections the first low and high level signal, triode Q1 grounded emitter, resistance R15
It is connected between triode Q1 base stage and emitter stage.
Further, the second switch circuit includes triode Q2, resistance R2, electric capacity C2, voltage-regulator diode ZD2, electricity
R6, resistance R10, resistance R14, resistance R16 are hindered, resistance R2, electric capacity C2, voltage-regulator diode ZD2 are connected in power vd D and the in parallel
Between the grid of two PMOSs, triode Q2 colelctor electrode passes through resistance R10, the grid of resistance R6 the second PMOSs of connection, three
Pole pipe Q2 base stage passes through resistance R14 connections the first low and high level signal, triode Q2 grounded emitter, resistance R16
It is connected between triode Q2 base stage and emitter stage.
Further, the control circuit also includes resistance R17, resistance R18, and two inputs of the 3rd nor gate are simultaneously
Together and connect resistance R17 one end, resistance R17 other end connection pwm signal, resistance R18 one end connection resistance R17
One end, resistance R18 the other end ground connection.
Further, in addition to detection circuit, the detection circuit include resistance R11, resistance R12, resistance R11, resistance R12
It is connected in parallel, and the connection end in parallel of the two one connects the source electrode of first NMOS tube and the second NMOS tube, and constitute detection
Signal output part, the another of the two is connected in parallel end ground connection.
Further, first nor gate, the second nor gate, the 3rd nor gate are integrated on the same chip.
The utility model separately provides a kind of motor device, including motor, single-chip microcomputer, in addition to the H described in any of the above-described
Bridge motor driver, the single-chip microcomputer is used to produce the pwm signal, the first low and high level signal and the second low and high level letter
Number.
Compared to prior art, the utility model has the advantages that：
Due to constituting the core devices of the 3rd on-off circuit, the 4th on-off circuit using nor gate so that the utility model
A PWM port and two common I/O ports need to be only used to single motor, the requirements of type selecting to unit piece is moderate, and cost is low, and
The noise jamming of relay can be excluded, and Electro Magnetic Compatibility is preferable.
The utility model is described in further detail below in conjunction with drawings and Examples；But a kind of H of the present utility model
Bridge motor driver and motor device are not limited to embodiment.
Brief description of the drawings
Fig. 1 is electrical block diagram of the present utility model；
Fig. 2 is the structure chart of 4 road nor gate integrated chip of the present utility model.
Embodiment
Embodiment, is referred to shown in Fig. 1, Fig. 2, a kind of H bridges motor driver of the present utility model, including H bridges commutation electricity
Road, the H bridges commutating circuit includes connection motor M1 and is located at the first PMOS P1 of high-end upper left, second positioned at high-end upper right
PMOS P2, the first NMOS tube N1 positioned at low side lower-left and the 2nd RNMOS the pipe N2, the first PMOS P1 positioned at low side bottom right
The first path is constituted with the 2nd RNMOS pipes N2, the second PMOS P2 and the first NMOS tube N1 constitute alternate path；First PMOS
P1 and the second PMOS P2 grid are connected to first switch circuit 1 and second switch circuit 2；Also include the 3rd switch electricity
Road 3, the 4th on-off circuit 4 and control circuit；3rd on-off circuit 3 includes the first nor gate U1, and the 4th on-off circuit 4 includes the
Two nor gate U2, in addition to control circuit, the control circuit include the 3rd nor gate U3, and the 3rd nor gate U3 two inputs connect
Connect pwm signal (i.e. MOTOR-PWM signals in Fig. 1), the first nor gate U1 of output termination an input and the second nor gate
A U2 input, the first nor gate U1 another input terminates the first low and high level signal (i.e. MOTOR-P letters in Fig. 1
Number), the first nor gate U1 the first NMOS tube N1 of output termination grid；Second nor gate U2 another input termination second is high
Low level signal (i.e. MOTOR-F signals in Fig. 1), the second low and high level signal is in motor forward or reverse state and first
The opposite in phase of low and high level signal；Second nor gate U2 the 2nd RNMOS pipes N2 of output termination grid.
In the present embodiment, the 3rd on-off circuit 3 also includes resistance R3, resistance R7 and electric capacity C3, and resistance R3 is connected to
Between first NMOS tube N1 grid and the first nor gate U1 output end, resistance R7 and electric capacity C3 are connected in the first NMOS in parallel
Between pipe N1 grid and source electrode；4th on-off circuit 4 also includes resistance R4, resistance R8 and electric capacity C4, resistance R4 connections
Between the 2nd RNMOS pipes N2 grid and the second nor gate U2 output end, resistance R8 and electric capacity C4 are connected in second in parallel
Between RNMOS pipes N2 grid and source electrode.3rd on-off circuit 3 also includes magnetic bead S1, and magnetic bead S1 is connected to first
Between NMOS tube N1 grid and the first nor gate U1 output end；4th on-off circuit 4 also includes magnetic bead S2, the magnetic bead
S2 is connected between the 2nd RNMOS pipes N2 grid and the second nor gate U2 output end.
In the present embodiment, the first switch circuit 1 and second switch circuit 2 are respectively transistor switching circuit, and the
One on-off circuit 1 connects the first low and high level signal, and second switch circuit 2 connects the second low and high level signal.
Specifically, the first switch circuit 1 includes triode Q1, resistance R1, electric capacity C1, voltage-regulator diode ZD1, resistance
R5, resistance R9, resistance R13, resistance R15, resistance R1, electric capacity C1, voltage-regulator diode ZD1 are connected in power vd D and first in parallel
Between PMOS P1 grid, triode Q1 colelctor electrode passes through resistance R9, resistance R5 the first PMOSs of connection P1 grid, three
Pole pipe Q1 base stage passes through resistance R13 connections the first low and high level signal, triode Q1 grounded emitter, resistance R15
It is connected between triode Q1 base stage and emitter stage.The second switch circuit 2 include triode Q2, resistance R2, electric capacity C2,
Voltage-regulator diode ZD2, resistance R6, resistance R10, resistance R14, resistance R16, resistance R2, electric capacity C2, voltage-regulator diode ZD2 are in parallel
Between the grid for being connected to power vd D and the second PMOS P2, triode Q2 colelctor electrode passes through resistance R10, resistance R6 connections
Second PMOS P2 grid, triode Q2 base stage passes through resistance R14 connections the first low and high level signal, triode Q2
Grounded emitter, resistance R16 is connected between triode Q2 base stage and emitter stage.The setting of described two voltage-regulator diodes
Two PMOSs can be played a protective role.
In the present embodiment, the control circuit also includes resistance R17, resistance R18, two inputs of the 3rd nor gate U3
Hold and together and connect resistance R17 one end, resistance R17 other end connection pwm signal, resistance R18 one end connection is electric
Hinder R17 one end, resistance R18 other end ground connection.
In the present embodiment, in addition to circuit 5 is detected, the detection circuit 5 includes resistance R11, resistance R12, resistance R11, electricity
Resistance R12 is connected in parallel, and the connection end in parallel of the two one connects the source electrode of the first NMOS tube N1 and the 2nd RNMOS pipes N2,
And detection signal output part MOTOR-DET is constituted, the another of the two is connected in parallel end ground connection.The pwm signal, the first height electricity
Ordinary mail number and the second low and high level signal are produced by single-chip microcomputer, the feedback letter of the detection signal output part MOTOR-DET outputs
To output to single-chip microcomputer number after Phototube Coupling and Linear Amplifer, single-chip microcomputer control pwm signal output duty cycle, so that
Motor adjusts output current size accordingly according to different loads, reaches the effect of constant current.In addition, once exception occurs for motor
(such as stall), the electric current that electric current moment becomes during than normal work is much bigger, and detection signal output part MOTOR-DET is abnormal
Signal feeds back to single-chip microcomputer, and single-chip microcomputer stops output pwm signal, so as to reach the effect of abnormal protection by processing.
In the present embodiment, the first nor gate U1, the second nor gate U2, the 3rd nor gate U3 are integrated in same chip
On.Specifically, can be directly using being integrated with 4 road nor gate integrated chip IC of four nor gates in the prior art (such as Fig. 2 institutes
Show), and during concrete application, need to only use 4 road nor gate integrated chip IC wherein three nor gates.
In the present embodiment, the first PMOS P1 and the second PMOS P2 drain electrode are connected on power vd D, power vd D respectively
It is also associated with adjustable resistance RT1.
The utility model separately provides a kind of motor device, including motor M1, single-chip microcomputer (not embodied in figure), in addition to above-mentioned
H bridge motor drivers described in any one, the single-chip microcomputer is used to produce the pwm signal, the first low and high level signal and the
Two low and high level signals.
When motor M1 works, under the control of single-chip microcomputer, the first PMOS P1, the 2nd RNMOS pipes N2 and the second PMOS
P2, the first NMOS tube N1 are turned in turn, so as to control positive and negative rotation of motor, by changing the dutycycle of pwm signal, change first
PMOS P1, the 2nd RNMOS pipes N2 and the second PMOS P2, the first NMOS tube N1 ON-OFF time, so as to adjust motor M1
Rotating speed.
Specific control process of the present utility model is as follows：
1) pwm signal, the first low and high level signal, the second low and high level signal export low level, then the 3rd nor gate
U3 export high level, the first nor gate U1 and the second nor gate U2 is exported low level respectively so that the first NMOS tube N1 and
2nd RNMOS pipes N2 ends respectively；Because the first low and high level signal, the second low and high level signal export low level so that
Triode Q1, triode Q2 end, so that the first PMOS P1, the second PMOS P2 end, now, motor M1, which is in, to be stopped
State；
2) pwm signal, the first low and high level signal output low level, the second low and high level signal output high level, then
Three nor gate U3 export high level, the first nor gate U1 and the second nor gate U2 is exported low level respectively, so that first
NMOS tube N1 and the 2nd RNMOS pipes N2 end respectively；Due to the first low and high level signal output low level, the second low and high level letter
Number output high level so that triode Q1 cut-off, triode Q2 conducting so that the first PMOS P1 cut-off, the second PMOS
P2 is turned on, now, and motor M1 is in halted state；
3) pwm signal output low level, the first low and high level signal output high level, the second low and high level signal output is low
Level, then the 3rd nor gate U3 outputs high level, makes the first nor gate U1 and the second nor gate U2 export low level respectively, so that
The first NMOS tube N1 and the 2nd RNMOS pipes N2 is set to end respectively；Due to the first low and high level signal output high level, the second height
Level signal exports low level so that triode Q1 conductings, triode Q2 cut-offs, so that the first PMOS P1 conductings, second
PMOS P2 ends, now, and motor M1 is in halted state；
4) pwm signal output low level, the first low and high level signal output high level, the second low and high level signal output is high
Level, then the 3rd nor gate U3 outputs high level, makes the first nor gate U1 and the second nor gate U2 export low level respectively, so that
The first NMOS tube N1 and the 2nd RNMOS pipes N2 is set to end respectively；Because the first low and high level signal, the second low and high level signal are equal
Export high level so that triode Q1, triode Q2 are both turned on, so that the first PMOS P1, the second PMOS P2 are turned on, this
When, motor M1 is in halted state；
5) pwm signal output high level, the first low and high level signal, the second low and high level signal output low level, then the
Three nor gate U3 export low level, the first nor gate U1 and the second nor gate U2 is exported high level respectively, so that first
NMOS tube N1 and the 2nd RNMOS pipes N2 are respectively turned on；Because the first low and high level signal, the second low and high level signal export low
Level so that triode Q1, triode Q2 are turned off, so that the first PMOS P1, the second PMOS P2 end, now, electricity
Machine M1 is in halted state；
6) pwm signal output high level, the first low and high level signal output high level, the second low and high level signal output is low
Level, then the 3rd nor gate U3 outputs low level, makes the first nor gate U1 export low level, the high electricity of the second nor gate U2 outputs
It is flat, so that the first NMOS tube N1 ends, the 2nd RNMOS pipes N2 conductings；Due to the first low and high level signal output high level,
Two low and high level signal output low levels so that triode Q1 is turned on, triode Q2 cut-offs, so that the first PMOS P1 is led
It is logical, the second PMOS P2 cut-offs, now, motor M1 is rotated forward；
7) pwm signal output high level, the first low and high level signal output low level, the second low and high level signal output is high
Level, then the 3rd nor gate U3 outputs low level, makes the first nor gate U1 export high level, and the second nor gate U2 exports low electricity
It is flat, so that the first NMOS tube N1 is turned on, the 2nd RNMOS pipes N2 cut-offs；Due to the first low and high level signal output low level,
Two low and high level signal output high level so that triode Q1 ends, triode Q2 conductings, so that the first PMOS P1 is cut
Only, the second PMOS P2 is turned on, now, motor M1 reversions；
8) pwm signal output high level, the first low and high level signal, the second low and high level signal output high level, then the
Three nor gate U3 export low level, make the first nor gate U1 outputs, the second nor gate U2 output low levels, so that the first NMOS
Pipe N1, the 2nd RNMOS pipes N2 end；Due to the first low and high level signal, the second low and high level signal output high level so that three
Pole pipe Q1, triode Q2 are turned on, so that the first PMOS P1, the second PMOS P2 are turned on, now, motor M1, which is in, stops shape
State.
Above-described embodiment is only used for further illustrating a kind of H bridges motor driver of the present utility model and motor device, but
The utility model is not limited to embodiment, it is every according to technical spirit of the present utility model above example is made it is any
Simple modification, equivalent variations and modification, each fall within the protection domain of technical solutions of the utility model.
Claims (10)
1. a kind of H bridges motor driver, including H bridge commutating circuits, the H bridges commutating circuit include connection motor and positioned at a high-end left side
On the first PMOS, the second PMOS positioned at high-end upper right, the first NMOS tube positioned at low side lower-left and right positioned at low side
Under the second NMOS tube, the first PMOS and the second NMOS tube constitute the first path, and the second PMOS and the first NMOS tube are constituted
Alternate path；The grid of first PMOS and the second PMOS is connected to first switch circuit and second switch circuit；Its
It is characterised by：Also include the 3rd on-off circuit, the 4th on-off circuit and control circuit, the 3rd on-off circuit includes first or non-
Door, the 4th on-off circuit includes the second nor gate, and control circuit includes the 3rd nor gate, and two inputs of the 3rd nor gate are connected
Pwm signal, output termination the first nor gate an input and the second nor gate an input, the first nor gate it is another defeated
Enter the first low and high level signal of termination, the grid of output the first NMOS tube of termination of the first nor gate；Second nor gate it is another
Input the second low and high level signal of termination, the second low and high level signal is in motor forward or reverse state and the first low and high level
Signal phase is opposite；The grid of output the second NMOS tube of termination of second nor gate.
2. H bridges motor driver according to claim 1, it is characterised in that：3rd on-off circuit also includes resistance
R3, resistance R7 and electric capacity C3, resistance R3 are connected between the output end of the grid of the first NMOS tube and the first nor gate, resistance R7
And electric capacity C3 is connected in parallel between the grid of the first NMOS tube and source electrode；4th on-off circuit also includes resistance R4, electricity
R8 and electric capacity C4 is hindered, resistance R4 is connected between the output end of the grid of the second NMOS tube and the second nor gate, resistance R8 and electricity
Hold C4 to be connected in parallel between the grid of the second NMOS tube and source electrode.
3. H bridges motor driver according to claim 2, it is characterised in that：3rd on-off circuit also includes magnetic bead
S1, magnetic bead S1 is connected between the output end of the grid of the first NMOS tube and the first nor gate；4th on-off circuit is also
Including magnetic bead S2, magnetic bead S2 is connected between the output end of the grid of the second NMOS tube and the second nor gate.
4. H bridges motor driver according to claim 1, it is characterised in that：The first switch circuit and second switch
Circuit is respectively transistor switching circuit, and first switch circuit connects the first low and high level signal, second switch circuit
Connect the second low and high level signal.
5. H bridges motor driver according to claim 4, it is characterised in that：The first switch circuit includes triode
Q1, resistance R1, electric capacity C1, voltage-regulator diode ZD1, resistance R5, resistance R9, resistance R13, resistance R15 are resistance R1, electric capacity C1, steady
Pressure diode ZD1 is connected in parallel between the grid of power vd D and the first PMOS, and triode Q1 colelctor electrode passes through resistance
R9, resistance R5 the first PMOSs of connection grid, triode Q1 base stage are believed by resistance R13 connections first low and high level
Number, triode Q1 grounded emitter, resistance R15 is connected between triode Q1 base stage and emitter stage.
6. H bridges motor driver according to claim 4, it is characterised in that：The second switch circuit includes triode
Q2, resistance R2, electric capacity C2, voltage-regulator diode ZD2, resistance R6, resistance R10, resistance R14, resistance R16, resistance R2, electric capacity C2,
Voltage-regulator diode ZD2 is connected in parallel between the grid of power vd D and the second PMOS, and triode Q2 colelctor electrode passes through resistance
R10, resistance R6 the second PMOSs of connection grid, triode Q2 base stage pass through resistance R14 connections first low and high level
Signal, triode Q2 grounded emitter, resistance R16 is connected between triode Q2 base stage and emitter stage.
7. H bridges motor driver according to claim 1, it is characterised in that：It is described control circuit also include resistance R17,
Resistance R18, two inputs of the 3rd nor gate simultaneously together and connect resistance R17 one end, and the resistance R17 other end connects
Connect pwm signal, resistance R18 one end connection resistance R17 one end, resistance R18 other end ground connection.
8. H bridges motor driver according to claim 1, it is characterised in that：Also include detection circuit, the detection circuit bag
Resistance R11, resistance R12 are included, resistance R11, resistance R12 are connected in parallel, and the connection end connection described first in parallel of the two one
The source electrode of NMOS tube and the second NMOS tube, and detection signal output part is constituted, the another of the two is connected in parallel end ground connection.
9. H bridges motor driver according to claim 1, it is characterised in that：First nor gate, the second nor gate,
3rd nor gate is integrated on the same chip.
10. a kind of motor device, including motor, single-chip microcomputer, it is characterised in that：Also include such as any one of claim 1-9 institutes
The H bridge motor drivers stated, the single-chip microcomputer is used to produce the pwm signal, the first low and high level signal and the second height electricity
Ordinary mail number.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201720030939.1U CN206452327U (en) | 2017-01-11 | 2017-01-11 | A kind of H bridges motor driver and motor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720030939.1U CN206452327U (en) | 2017-01-11 | 2017-01-11 | A kind of H bridges motor driver and motor device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109217775A (en) * | 2018-06-28 | 2019-01-15 | 珠海市诚立信电子科技有限公司 | A kind of stepless speed regulation circuit driving alternating current generator |
| CN112073628A (en) * | 2019-06-10 | 2020-12-11 | 海信视像科技股份有限公司 | Motor control circuit, driving device and display device |
| CN112187120A (en) * | 2020-08-21 | 2021-01-05 | 天津市天波科达科技有限公司 | Output circuit of PWM-saving control port |
| CN113078856A (en) * | 2021-03-15 | 2021-07-06 | 天津市天波科达科技有限公司 | Circuit device and brush motor |
-
2017
- 2017-01-11 CN CN201720030939.1U patent/CN206452327U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109217775A (en) * | 2018-06-28 | 2019-01-15 | 珠海市诚立信电子科技有限公司 | A kind of stepless speed regulation circuit driving alternating current generator |
| CN109217775B (en) * | 2018-06-28 | 2021-09-14 | 珠海市诚立信电子科技有限公司 | Stepless speed regulating circuit for driving alternating current motor |
| CN112073628A (en) * | 2019-06-10 | 2020-12-11 | 海信视像科技股份有限公司 | Motor control circuit, driving device and display device |
| CN112073628B (en) * | 2019-06-10 | 2022-02-11 | 海信视像科技股份有限公司 | Motor control circuit, driving device and display device |
| CN112187120A (en) * | 2020-08-21 | 2021-01-05 | 天津市天波科达科技有限公司 | Output circuit of PWM-saving control port |
| CN113078856A (en) * | 2021-03-15 | 2021-07-06 | 天津市天波科达科技有限公司 | Circuit device and brush motor |
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