CN206422754U - A kind of electrification reset circuit - Google Patents
A kind of electrification reset circuit Download PDFInfo
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- CN206422754U CN206422754U CN201720078919.1U CN201720078919U CN206422754U CN 206422754 U CN206422754 U CN 206422754U CN 201720078919 U CN201720078919 U CN 201720078919U CN 206422754 U CN206422754 U CN 206422754U
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Abstract
The utility model discloses a kind of electrification reset circuit, it is characterised in that：Including undervoltage detection circuit, pierce circuit, counter, digital comparator, trigger, undervoltage detection circuit is used for outputs level signals after the supply voltage of detection is compared with reference voltage, and its output result inputs the reset terminal of the input of oscillator control circuit, the reset terminal of trigger and counter respectively；Pierce circuit is used to produce clock pulse signal, counter is used to count clock pulse signal, the input of digital comparator inputs the output signal and time delay setting numerical value of counter respectively, the output end of digital comparator connects the input of trigger and the input of oscillator control circuit respectively, the output end output reset signal POR of trigger, oscillator control circuit controls the work of oscillator according to the output signal of undervoltage detection circuit and digital comparator.Its advantage is, in supply voltage reduction, voltage big ups and downs, accurately to produce low level reset signal.
Description
Technical field
The utility model belongs to circuit system field, more particularly to a kind of time delay adjustable low level electrification reset electricity
Road.
Background technology
With the development of very large scale integration technology, circuit system requires that electrification reset circuit possesses more functions
More preferably performance.Circuit system electrification reset (Pow-on Reset, POR) circuit can reset to digital circuit, protect
Card circuit can reliably start in power supply electrifying.Power-on reset signal is always maintained at low level during rising on the supply voltage,
Now, circuit system is in reset state, and high level is changed into after supply voltage stably reaches desired operating voltage, multiple
Position state terminates, and circuit system enters normal operating conditions.
In general, in circuit system after electricity, after supply voltage reaches nominal voltage, in addition it is also necessary to safety
Resetting time, with ensure circuit system internal circuit working condition all in stable and controllable state.Usual safety reset
Time refers to that the low level state of reset signal continues the instruction cycle of three or more, in order to which reset routine starts initially
Change the original state of chip internal.
As shown in figure 1, the reset circuit of prior art is the characteristic that can not be mutated using the voltage on electric capacity, pass through electricity
Electric capacity charging modes are hindered to produce low level reset signal RET.Its operation principle is：During energization, electric capacity two ends are the equal of short
Road, is then low level on reset pin, then power supply is charged by resistance to electric capacity, and reset pin voltage slowly rises, on
It is raised to a certain degree, capacitance charging current is zero, pin voltage is high level, reseting stage terminates, and circuit system starts just
Often work.
Traditional reset circuit implementation is simple, but there is the problem of resetting time adjustment is difficult, moreover, this structure
Secondary during electric or supply voltage big ups and downs, the voltage at electric capacity two ends can not effectively discharge, thus it is possible to occurring
Reset circuit disabler, causes when supply voltage is reduced, it is impossible to produce correct low level reset signal.
The content of the invention
The utility model is intended at least solve one of technical problem present in prior art.Therefore, the utility model is carried
For a kind of electrification reset circuit, it is therefore an objective to can produce accurate delayed reset signal, and the delayed management time is adjustable.
To achieve these goals, the technical scheme that the utility model is taken is：A kind of electrification reset circuit, its feature exists
In：Including undervoltage detection circuit, pierce circuit, counter, digital comparator, trigger, the undervoltage detection circuit is used for
Outputs level signals after the supply voltage of detection is compared with reference voltage, its output result inputs oscillator control circuit respectively
Input, the RESET input of the RESET input of trigger and counter；The pierce circuit is used to produce clock arteries and veins
Signal is rushed, the counter is used to count clock pulse signal, and the input of the digital comparator inputs meter respectively
The output signal of number device and the pulse delay signals of setting, the output end of the digital comparator connect the clock of trigger respectively
The input of input and oscillator control circuit, the output end output reset signal POR of the trigger, the oscillator control
Circuit processed controls the work of oscillator according to the output signal of undervoltage detection circuit and counter.
The undervoltage detection circuit includes resistance R1, R2, R3, diode D1 and comparator COMP；Resistance R1 one end is connected
Power vd D, the other end connects comparator COMP negative input end and resistance R2 one end, resistance R2 other end ground connection respectively；
Resistance R3 one end is connected with power vd D, other end connection diode D1 anode, diode D1 minus earth, diode
Anode is connected with comparator COMP positive input terminal, and the output end difference connection oscillator of comparator controls circuit input end, touched
Send out the RESET input of device and the RESET input of counter.
The pierce circuit includes current reference circuit, capacitor charge and discharge circuit, Schmidt circuit, NAND gate, described
Current reference circuit include resistance R4 and transistor M1, M2, the capacitor charge and discharge circuit include electric capacity C1 and transistor M3,
M4, M5, transistor M1 drain electrode connection power vd D, transistor M1 source electrode connection transistor M2 drain electrode, transistor M2 source
Pole is grounded by resistance R4, and transistor M2 grid is connected with its source electrode, and the grid of the transistor M1 connects transistor respectively
M1 source electrode and transistor M3 grid, transistor M3 drain electrode connection power vd D, transistor M3 source electrode connection transistor M4
Drain electrode, transistor M4 source electrode connects transistor M5 source electrode and the input of Schmidt circuit, transistor M5 leakage respectively
Pole is grounded, and electric capacity C1 is connected in parallel on transistor M5 source electrodes and drain electrode two ends, and the output end of Schmidt circuit connects the input of NAND gate
End, another input connection oscillator of NAND gate controls the output end of circuit, the output end difference linkage counter of NAND gate
Input and transistor M4 grid, transistor M4 grid connection transistor M5 grid.
The oscillator control circuit is made up of nor gate, two inputs of the nor gate connect respectively numeric ratio compared with
The output end of device and comparator COMP output end, the output end of the nor gate connect the input of NAND gate.
The utility model produces pulse signal by pierce circuit, and counter enters to the pulse signal of clock oscillator circuit
Row is counted, and is compared with the default reset delay time of outside input.When count pulse number is not up to preset value,
Low level reset signal is produced, the reset control of circuit system is completed.When count pulse reaches preset value, the high electricity of output
Ordinary mail number, closes clock oscillator, and circuit system enters normal operating conditions, meanwhile, close internal clock oscillators.Work as power supply
When voltage is reduced, by undervoltage detection circuit, low level reset signal can also be produced；Meanwhile, internal clock oscillators are closed,
The numerical value of counter is initialized as zero, when upper electricity or supply voltage recover again again, to produce correct pulsimeter
Number function.
It is of the present utility model to be counted by the output pulse to pierce circuit, accurate reset can be obtained and prolonged
The slow time, and the time delay is adjustable.By the detection to supply voltage, accurate under-voltage reset signal can be produced, is allowed
The performance of electrification reset circuit is relatively reliable；In supply voltage reduction, supply voltage big ups and downs, can accurately it produce low
Level reset signal.
Brief description of the drawings
This specification includes the following drawings, and shown content is respectively：
Fig. 1 is electrification reset circuit schematic diagram in the prior art；
Fig. 2 is the utility model electrification reset circuit schematic diagram；
Embodiment
Below against accompanying drawing, by the description to embodiment, further detailed is made to embodiment of the present utility model
Thin explanation, it is therefore an objective to help those skilled in the art have to design of the present utility model, technical scheme it is more complete, accurate and
Deep understanding, and contribute to it to implement.
A kind of electrification reset circuit, including undervoltage detection circuit, pierce circuit, counter, digital comparator, triggering
Device, undervoltage detection circuit is used for outputs level signals after the supply voltage of detection is compared with reference voltage, its output result point
Not Shu Ru the input of oscillator control circuit, the RESET input of trigger and counter the RESET input；Oscillator electricity
Road is used to produce clock pulse signal, and counter is used to count clock pulse signal, the input point of digital comparator
Not Shu Ru counter output signal and setting pulse daley signal, digital comparator output end connect respectively trigger when
The input of clock input and oscillator control circuit, the output end output reset signal POR of trigger, oscillator control circuit
The work of oscillator is controlled according to the output signal of undervoltage detection circuit and digital comparator.When under-voltage detection in power up
When detecting supply voltage more than reference voltage, under-voltage reference circuit exports low level, passes through oscillator control circuit and vibration
Device circuit so that oscillator operation, counter is counted to clock pulses, digital comparator compare setting delay pulse and
The umber of pulse of step-by-step counting, when the time delay of not up to setting setting numerical value, digital comparator output low level, the low electricity
The low level of gentle undervoltage detection circuit output is input to the input of oscillator control circuit jointly so that oscillator continues work
Make, when the numerical value of counter reaches the delay time of setting, digital comparator exports high level, then oscillator control circuit
With pierce circuit collective effect, stop oscillation device pulse, close oscillator, while the high level of digital comparator be input to it is tactile
Send out the input end of clock of device so that the reset signal POR of trigger is high level, circuit system or chip reset terminate, normally
Work.
Physical circuit of the present utility model is explained below in conjunction with accompanying drawing.
Power supply is that system or chip provide electric energy, needs to reset system in power supply electrifying, both ends of power point
Not Wei VDD and GND, as shown in Fig. 2 undervoltage detection circuit is by including resistance R1, R2, R3, diode D1 and comparator COMP shake
Swing device control circuit to be made up of nor gate, resistance R1 and resistance R2 first connect and be connected in parallel on chip power two ends afterwards.Resistance R1 and electricity
R2 formation bleeder circuits are hindered, power supply voltage division signal VN11 are drawn between resistance R1 and resistance R2, signal VN11, which is input to, to be compared
Device COMP negative input end.Resistance R3 and diode D1 form simple voltage reference circuit, resistance R3 one end and power vd D
Connection, other end connection diode D1 anode, diode D1 minus earth, diode anode is just defeated with comparator COMP's
Enter end connection.The signal that diode D1 anodes are drawn is VN10 voltage reference signal, and the signal is input to comparator COMP's
Positive input terminal, comparator, which is compared the level after output relatively to power supply voltage division signal VN11 and reference electrical signal VN10, to be believed
Number, i.e., when VN11 voltage is more than VN10, comparator COMP output high level VN12, when VN11 voltages are less than VN10, than
It is low level compared with device output signal VN12.Comparator COMP output end connects nor gate NOR2 input, trigger respectively
DFFR the RESET input and counter Counter the RESET input.Nor gate NOR2 another input connection numeric ratio
Compared with the output end of device.
Nor gate NOR2 collectively constitutes work and the control circuit of oscillator with pierce circuit.Nor gate NOR2 is control
The critical piece of pierce circuit.Pierce circuit includes current reference circuit, capacitor charge and discharge circuit, Schmidt circuit
Schmidt, NAND gate NAND, current reference circuit include resistance R4 and transistor M1, M2, and capacitor charge and discharge circuit includes electric capacity
C1 and transistor M3, M4, M5, transistor M1 drain electrode connection power vd D, transistor M1 source electrode connection transistor M2 leakage
Pole, transistor M2 source electrode is grounded by resistance R4, and transistor M2 grid is connected with its source electrode, transistor M1 grid difference
Transistor M1 source electrode and transistor M3 grid are connected, transistor M3 drain electrode connection power vd D, transistor M3 source electrode connect
Connect transistor M4 drain electrode, transistor M4 source electrode connect respectively transistor M5 source electrode and Schmidt circuit Schmidt it is defeated
Enter end, transistor M5 grounded drain, electric capacity C1 is connected in parallel on transistor M5 source electrodes and drain electrode two ends, Schmidt circuit Schmidt
Output end connection NAND gate NAND input, NAND gate NAND another input connection nor gate NOR2 output end,
NAND gate NAND output end difference linkage counter Counter input and transistor M4 grid, transistor M4 grid
Pole connection transistor M5 grid.A counter Counter output end connection digital comparator DCOMP input, number
It is worth comparator DCOMP another input input delay time setting numerical value SET [5:0], digital comparator DCOMP logarithm values
Be compared outputs level signals, its output end connect respectively trigger DFFR input end of clock C pin and one of nor gate
Input, trigger DFFR output end exports reset signal POR to system or chip, to complete homing action.
During electrification reset, supply voltage slowly rises, at upper electric initial stage, and supply voltage is relatively low, by resistance R1 with
The voltage signal VN11 that R2 partial pressures are obtained is compared less than the reference voltage V N10 of resistance R3 and diode D1 formation by comparator
Afterwards, when VN11 voltages are less than VN10, comparator output signal VN12 is high level, and signal VN12 is separately input to for high level
Nor gate NOR2 input, counter Counter reset terminal RESET, trigger DFFR reset terminal R, signal VN12 are high
Level causes counter Counter to be zeroed out reset, and trigger DFFR also resets so that the reset letter of trigger DFFR outputs
Number POR is low level, and system or chip low level reset；Nor gate NOR2 is due to there is high level VN12 simultaneously in input, and its is defeated
Go out to hold output signal VN7 be low level signal, VN7 is input to NAND gate NAND input, because VN7 is low level, then by
In the characteristic of NAND gate, its output end output signal VN5 is high level signal, and VN5 is input to transistor M4 and M5 grid, made
Obtain transistor M4 to close, M5 conductings, electric capacity C1 enters discharge condition, and now pierce circuit is in reset state, after reset
Schmidt circuit Schmidt input is that signal VN4 is low level, and the output end signal VN6 of Schmidt circuit is high level,
VN6 is input to the input of NAND gate, and because a NAND gate NAND input signal VN7 is low level, it exports VN5 meetings one
It is directly high level, whole pierce circuit is in reset state, until VN12 level from height is changed into low.
When rising the expectation voltage for reaching system work on the supply voltage, the voltage obtained by resistance R1 and R2 partial pressures is believed
Number VN11 is more than the reference voltage V N10 of resistance R3 and diode D1 formation, i.e. VN11 voltages and is more than VN10 voltages, now compares
Device COMP output signals VN12 is changed into low level from high level, because digital comparator DCOMP output end output signal VN8 are in meter
When the signal VN9 of number device is not reaching to the time delay of setting, VN8 inputs are low level, and two inputs of nor gate NOR2 are
During low level, it is high level that it, which exports VN7, and VN7 was changed into high level from the low level at upper electric initial stage.VN7 is input to NAND gate
NAND input, because upper electric VN6 at initial stage is constantly in high level, therefore output end signal VN5 is changed into low level, now electric
The current reference generation circuit for hindering R4 and transistor M1, M2 composition produces reference current, and electric current is constituted by transistor M1 and M3
Mirror circuit charges reference current by transistor M3, M4 to electric capacity C1.Electric capacity C1 terminal voltage VN4 constantly rises, and is input to
Schmidt circuit Schmidt input, when VN4 voltages are more than Schmidt circuit Schmidt turnover voltage, Schmidt's electricity
Road Schmidt output signal VN6 is changed into low level from high level, now due to NAND gate property, and its output signal VN5 is changed into
High level, the grid that signal VN5 passes through controlling transistor M4 and M5 so that M4 is closed, M5 conductings, electric capacity C1 are in electric discharge shape
State, hereafter because VN7 is constantly in high level, electric capacity C1 alternately realizes charging and discharging state, so that in the output end of NAND gate
Output signal VN5 produces dagital clock signal, and counter Counter is counted to VN5 clock pulse signal, output result
VN9 numerical value and the delay time of setting are compared by VN9 to digital comparator DCOMP, digital comparator, less than setting
Delay time when, output signal VN8 be low level, when the time delay more than setting, output signal VN8 be high level,
VN8 is input to trigger DFFR input end of clock, and reset signal POR is exported by trigger DFFR, when VN8 is high level,
POR is high level, and system reset terminates to start to start work, and reset terminates.Nor gate output end letter when VN8 is high level simultaneously
Number VN7 is changed into low level, and NAND gate output end signal VN5 is high level, and electric capacity C1 is in discharge condition, because VN8 locates always
In high level, then VN5 is just constantly in high level, and now electric capacity discharges until be 0 always, now closes capacitor charge and discharge electricity
Road, completes oscillator shutoff operation, and whole pierce circuit is in reset state, does not produce clock signal.
When under-voltage condition occurs in supply voltage, VN12 is changed into high level, and now trigger DFFR is resetted, and produces
Under-voltage reset signal POR causes system reset, while be zeroed out reset to counter Counter, be easy to re-powering or
When person's voltage recovers again, counter Counter, which correctly starts from scratch, calculates the pulse signal of oscillator, it is ensured that accurately prolong
Late.Counter, comparator, digital comparator, trigger in the utility model are circuit element known to electricity field, this
In do not illustrate.
The utility model is exemplarily described above in association with accompanying drawing.Obviously, the utility model is implemented not
Limited by aforesaid way.As long as employ the various unsubstantialities that method design of the present utility model and technical scheme are carried out
Improvement；Or it is not improved, above-mentioned design of the present utility model and technical scheme are directly applied into other occasions, at this
Within the protection domain of utility model.
Claims (4)
1. a kind of electrification reset circuit, it is characterised in that：Including undervoltage detection circuit, pierce circuit, counter, numeric ratio compared with
Device, trigger, the undervoltage detection circuit are used for outputs level signals after the supply voltage of detection is compared with reference voltage, its
Output result inputs the reset input of the input of oscillator control circuit, the RESET input of trigger and counter respectively
End；The pierce circuit is used to produce clock pulse signal, and the counter is used to count clock pulse signal, institute
The input for stating digital comparator inputs the output signal and time delay setting numerical value of counter, the digital comparator respectively
Output end connect the input end of clock of trigger and the input of oscillator control circuit, the output end of the trigger respectively
Reset signal POR is exported, the oscillator control circuit is controlled according to the output signal of undervoltage detection circuit and digital comparator
The work of oscillator.
2. a kind of electrification reset circuit as claimed in claim 1, it is characterised in that：The undervoltage detection circuit includes resistance
R1, R2, R3, diode D1 and comparator COMP；Resistance R1 one end connects power vd D, and the other end connects comparator COMP respectively
Negative input end and resistance R2 one end, resistance R2 the other end ground connection；Resistance R3 one end is connected with power vd D, the other end
Diode D1 anode is connected, diode D1 minus earth, diode anode is connected with comparator COMP positive input terminal, than
The reset terminal of output end difference connection oscillator control circuit input end, the reset terminal of trigger and counter compared with device COMP.
3. a kind of electrification reset circuit as claimed in claim 2, it is characterised in that：The pierce circuit includes current reference
Circuit, capacitor charge and discharge circuit, Schmidt circuit, NAND gate, the current reference circuit include resistance R4 and transistor M1,
M2, the capacitor charge and discharge circuit includes electric capacity C1 and transistor M3, M4, M5, transistor M1 drain electrode connection power vd D, crystalline substance
Body pipe M1 source electrode connection transistor M2 drain electrode, transistor M2 source electrode is grounded by resistance R4, transistor M2 grid with
Its source electrode is connected, and the grid of the transistor M1 connects transistor M1 source electrode and transistor M3 grid, transistor M3 respectively
Drain electrode connection power vd D, transistor M3 source electrode connection transistor M4 drain electrode, transistor M4 source electrode connects crystalline substance respectively
Body pipe M5 source electrode and the input of Schmidt circuit, transistor M5 grounded drain, electric capacity C1 are connected in parallel on transistor M5 source electrodes
With drain electrode two ends, the output end of Schmidt circuit connects the input of NAND gate, another input connection oscillator of NAND gate
Control the output end of circuit, the input and transistor M4 grid of the output end difference linkage counter of NAND gate, transistor
M4 grid connection transistor M5 grid.
4. a kind of electrification reset circuit as claimed in claim 3, it is characterised in that：The oscillator control circuit is by nor gate
Composition, two inputs of the nor gate connect the output end of digital comparator and comparator COMP output end, institute respectively
The output end for stating nor gate connects the input of NAND gate.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720078919.1U CN206422754U (en) | 2017-01-20 | 2017-01-20 | A kind of electrification reset circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720078919.1U CN206422754U (en) | 2017-01-20 | 2017-01-20 | A kind of electrification reset circuit |
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| CN206422754U true CN206422754U (en) | 2017-08-18 |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107463236A (en) * | 2017-08-28 | 2017-12-12 | 珠海格力电器股份有限公司 | A kind of reset detection circuit and reset detection method |
| CN107733407A (en) * | 2017-11-03 | 2018-02-23 | 中国电子科技集团公司第五十四研究所 | A kind of fast charging and discharging and resetting time controllable electrification reset circuit |
| CN109739710A (en) * | 2019-01-04 | 2019-05-10 | 华大半导体有限公司 | A kind of method that undervoltage detection circuit is under-voltage with detection |
| CN110427089A (en) * | 2019-09-11 | 2019-11-08 | 深圳市富满电子集团股份有限公司 | Power-on reset system and method suitable for LED display chip |
| CN111181548A (en) * | 2020-01-16 | 2020-05-19 | 山东美创生物科技股份有限公司 | Counting and sampling circuit for mosquito killing equipment |
| CN111404522A (en) * | 2020-04-02 | 2020-07-10 | 上海集成电路研发中心有限公司 | Clock circuit |
| CN111817695A (en) * | 2020-07-28 | 2020-10-23 | 成都华微电子科技有限公司 | Power-on reset circuit capable of preventing power supply from shaking |
| CN112803743A (en) * | 2021-03-01 | 2021-05-14 | 波达通信设备（广州）有限公司 | Power supply starting circuit and switching power supply |
| CN113938628A (en) * | 2021-10-08 | 2022-01-14 | 中国电子科技集团公司第二十四研究所 | Current-frequency oscillator for digital pixel readout circuit |
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2017
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Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107463236A (en) * | 2017-08-28 | 2017-12-12 | 珠海格力电器股份有限公司 | A kind of reset detection circuit and reset detection method |
| CN107463236B (en) * | 2017-08-28 | 2023-05-12 | 珠海格力电器股份有限公司 | Reset detection circuit and reset detection method |
| CN107733407A (en) * | 2017-11-03 | 2018-02-23 | 中国电子科技集团公司第五十四研究所 | A kind of fast charging and discharging and resetting time controllable electrification reset circuit |
| CN109739710A (en) * | 2019-01-04 | 2019-05-10 | 华大半导体有限公司 | A kind of method that undervoltage detection circuit is under-voltage with detection |
| CN110427089A (en) * | 2019-09-11 | 2019-11-08 | 深圳市富满电子集团股份有限公司 | Power-on reset system and method suitable for LED display chip |
| CN111181548B (en) * | 2020-01-16 | 2022-11-22 | 山东美创生物科技股份有限公司 | Counting and sampling circuit for mosquito killing equipment |
| CN111181548A (en) * | 2020-01-16 | 2020-05-19 | 山东美创生物科技股份有限公司 | Counting and sampling circuit for mosquito killing equipment |
| CN111404522A (en) * | 2020-04-02 | 2020-07-10 | 上海集成电路研发中心有限公司 | Clock circuit |
| CN111404522B (en) * | 2020-04-02 | 2023-09-29 | 上海集成电路研发中心有限公司 | Clock circuit |
| CN111817695A (en) * | 2020-07-28 | 2020-10-23 | 成都华微电子科技有限公司 | Power-on reset circuit capable of preventing power supply from shaking |
| CN111817695B (en) * | 2020-07-28 | 2023-07-04 | 成都华微电子科技股份有限公司 | Power-on reset circuit capable of preventing power supply from shaking |
| CN112803743A (en) * | 2021-03-01 | 2021-05-14 | 波达通信设备（广州）有限公司 | Power supply starting circuit and switching power supply |
| CN113938628A (en) * | 2021-10-08 | 2022-01-14 | 中国电子科技集团公司第二十四研究所 | Current-frequency oscillator for digital pixel readout circuit |
| CN113938628B (en) * | 2021-10-08 | 2023-11-14 | 中国电子科技集团公司第二十四研究所 | Current-frequency oscillator for digital pixel readout circuit |
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