CN206364912U - Low frame frequency imaging system - Google Patents
Low frame frequency imaging system Download PDFInfo
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- CN206364912U CN206364912U CN201621469053.9U CN201621469053U CN206364912U CN 206364912 U CN206364912 U CN 206364912U CN 201621469053 U CN201621469053 U CN 201621469053U CN 206364912 U CN206364912 U CN 206364912U
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- 238000003384 imaging method Methods 0.000 title claims abstract description 14
- 230000005540 biological transmission Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 3
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Abstract
The utility model relates to a low frame frequency imaging system, which comprises an image detector, an image processing chip and an image temporary storage; the image temporary storage is arranged on an image transmission channel between the image detector and the image processing chip. The utility model discloses a set up the image temporary storage, carry out frame-by-frame buffer memory with the image information of image detector output earlier, then take out the frame by the image processing chip and read again, both guaranteed the image quality of image detector work when higher frequency and reading rate, can satisfy the image output demand of low frame frequency again simultaneously.
Description
Technical field
The utility model is related to a kind of low frame rate imaging system.
Background technology
It is well known that being limited to transmission channel bandwidth or back-end image disposal ability, space borne imagery system picture frame frequency is general
All over smaller, data rate request is relatively low.But, current cmos image detector, frame frequency is often higher, if forcing it to work in
Compared with low frame rate and read-out speed, dark current can be caused to accumulate, cause picture noise to increase, output image quality is poor.
The content of the invention
In order to solve the technical problem that existing cmos image detector is difficult in adapt to low frame rate imaging demand, this practicality is new
Type provides a kind of low frame rate imaging system.
Technical solution of the present utility model is：A kind of low frame rate imaging system, including at image detector and image
Chip is managed, it is characterized in that：Also include image buffer；Described image buffer is located at image detector and image procossing
On image transmitting passage between chip.
Above-mentioned image buffer is SRAM memory.
The capacity of above-mentioned SRAM memory is 1M*16bit.
The utility model also provides a kind of image output method of low frame rate imaging system, and it is characterized in that：Including
Following steps：
1) after system electrification, image detector starts to expose and gather image；
2) image detector exports the image collected into image buffer frame by frame, and image transmitting frame frequency is 2n
fps；Picture processing chip from image buffer by the way of taking out frame using reading image information；
2.1) in the 1st two field picture deposit image buffer, picture processing chip is not processed；
2.2) during the 2nd frame to n-th frame image deposit image buffer, picture processing chip is from image buffer
The 1st two field picture of middle reading；
2.3) in the (n+1)th two field picture deposit image buffer, picture processing chip is not processed；
2.4) during the n-th+2 frame to 2n two field pictures deposit image buffer, picture processing chip is temporary from image
The (n+1)th two field picture is read in storage；
3) picture processing chip carries out the image of reading to export after parallel-serial conversion.
The beneficial effects of the utility model are：The utility model is by setting image buffer, first by image detector
The image information of output is cached frame by frame, is then taken out frame by picture processing chip progress again and is read, both ensure that image detection
Device is operated in picture quality when upper frequency and read-out speed, while can meet the image output demand of low frame rate again.
Brief description of the drawings
Fig. 1 takes out frame principle schematic for the utility model low frame rate imaging system image output method.
Embodiment
Preferred embodiment of the present utility model carries out image from the cmos image detector vita1300 of ONSEMI companies
Collection, in order to overcome the contradiction of higher rate and frame frequency again between the constraint of camera image output format, the present embodiment is in image
Increasing the SRAM memory that a piece of capacity is 1M*16bit between detector and picture processing chip, (size of 1 two field picture is 1M*
10bit)。
Referring to Fig. 1, the specific workflow of the present embodiment low frame rate imaging system is as follows：
Detector working frequency 25MHz, when system exposure times are less than 50ms, frame frequency uses 18f/s, when the 1st frame figure
During as output detector, SRAM is deposited into, FPGA is disregarded when the 2nd~9 frame is exported, but in this period by the first frame
Image is read from SRAM；When the 10th two field picture output detector, SRAM is deposited into, FPGA is refused when the 11st~18 frame is exported
Processing, but read the 10th two field picture from SRAM in this period, the speed that image is read from SRAM is 2.5MHz, and is gone here and there turn
After changing, output speed is 25Mbps, meets application requirement.
When system exposure times be more than 50ms when, frame frequency can be reduced according to the time for exposure, still, the thinking of caching process and
Analysis above is consistent.
Claims (4)
1. a kind of low frame rate imaging system, including image detector and picture processing chip, it is characterised in that：Also include image temporary
Storage；Described image buffer is located on the image transmitting passage between image detector and picture processing chip.
2. low frame rate imaging system according to claim 1, it is characterised in that：Described image buffer stores for SRAM
Device.
3. low frame rate imaging system according to claim 2, it is characterised in that：The capacity of the SRAM memory is 1M*
16bit。
4. according to any described low frame rate imaging system in claim 1-3, it is characterised in that：Described image detector is
Cmos image detector vita1300.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621469053.9U CN206364912U (en) | 2016-12-29 | 2016-12-29 | Low frame frequency imaging system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621469053.9U CN206364912U (en) | 2016-12-29 | 2016-12-29 | Low frame frequency imaging system |
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| Publication Number | Publication Date |
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| CN206364912U true CN206364912U (en) | 2017-07-28 |
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| CN201621469053.9U Active CN206364912U (en) | 2016-12-29 | 2016-12-29 | Low frame frequency imaging system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106603936A (en) * | 2016-12-29 | 2017-04-26 | 中国科学院西安光学精密机械研究所 | Low frame frequency imaging system and image output method thereof |
-
2016
- 2016-12-29 CN CN201621469053.9U patent/CN206364912U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106603936A (en) * | 2016-12-29 | 2017-04-26 | 中国科学院西安光学精密机械研究所 | Low frame frequency imaging system and image output method thereof |
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