CN206292654U - A kind of low-voltage nanowatt magnitude whole CMOS current-mode reference voltage source - Google Patents
A kind of low-voltage nanowatt magnitude whole CMOS current-mode reference voltage source Download PDFInfo
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Abstract
The utility model discloses a kind of low-voltage nanowatt magnitude whole CMOS current-mode reference voltage source, it is characterized in that, including start-up circuit, IPTATaReference current source circuit, IPTATbReference current source circuit and temperature-compensation circuit；Start-up circuit is connected to IPTATaReference current source circuit and IPTATbReference current source circuit, and provide electric current when reference voltage source is opened so that reference voltage source breaks away from degeneracy bias point；IPTATaReference current source circuit and IPTATbReference current source circuit produces a bias current for temperature-compensation circuit provides current offset respectively；Temperature-compensation circuit is poor with different multiples respectively by 2 bias currents, obtains a temperature independent reference current, and metal-oxide-semiconductor obtains an output voltage not influenceed by supply voltage and temperature change in actuation temperature compensation circuit.The utility model has that low in energy consumption, chip area is small, device is matched with standard CMOS process, temperature coefficient is low and the characteristics of supply-voltage rejection ratio high.
Description
Technical Field
The utility model relates to an integrated circuit technical field, concretely relates to low-voltage nano watt level full CMOS current mode reference voltage source.
Background
The reference voltage source is an indispensable module in an analog integrated circuit and a hybrid integrated circuit, and is widely applied to circuit systems such as an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a DC-DC converter, and a power amplifier to generate a direct current voltage that is not affected by a power supply voltage and a temperature change. The conventional reference voltage source consumes a large amount of power due to a large current required, and requires a resistor, a diode, or a BJT transistor to generate a PTAT voltage during a design process, so that the device requires a large chip area. In order to make the rest of the circuit of the energy-saving application device compatible, the reference voltage source needs to use a standard CMOS process, and devices except a MOS tube are avoided. However, the CMOS reference voltage source circuit uses a CMOS and a resistor in a saturation region, so that power consumption is excessive and a chip area is large. The recently proposed non-resistance reference voltage source based on the sub-threshold region has poor parameters of temperature drift, power supply voltage regulation rate and power supply rejection ratio although the power consumption is low.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem that current reference voltage source has that the consumption is big, the territory area is big, the device does not match with standard CMOS technology, temperature coefficient is high and supply voltage suppression ratio low scheduling problem, provides a low-voltage nano watt level full CMOS current mode reference voltage source.
In order to solve the above problems, the utility model discloses a realize through following technical scheme:
a low-voltage nano-watt full CMOS current mode reference voltage source is characterized by comprising a starting circuit and an IPTATaReference current source circuit, IPTATbA reference current source circuit and a temperature compensation circuit; the starting circuit is connected toPTATaReference electricityFlow source circuit and IPTATbThe reference current source circuit provides current when the reference voltage source is started, so that the reference voltage source gets rid of a degenerated bias point and enters a normal working state; i isPTATaThe reference current source circuit generates a bias current IPaProviding a current bias for the temperature compensation circuit; i isPTATbThe reference current source circuit generates a bias current IPbProviding a current bias for the temperature compensation circuit; temperature compensation circuit IPTATaReference current source circuit and IPTATbBias current I proportional to temperature generated by reference current source circuitPaAnd IPbAre respectively represented by k1And k2Is multiplied by a factor of (c) to obtain a temperature-independent reference current IREFAnd driving the MOS tube in the temperature compensation circuit to obtain an output voltage which is not influenced by the power supply voltage and the temperature change.
In the scheme, the starting circuit consists of MOS tubes M1-M5 and a capacitor C1; the source electrodes of the MOS transistor M1 and the MOS transistor M2 are connected with a power supply VDD; the grid electrode of the MOS tube M1-M5, the drain electrode of the MOS tube M2 and the upper electrode plate of the capacitor C1 are connected; the MOS transistor M1 is connected with the drain electrode of the MOS transistor M5 and is connected with the source electrodes of the MOS transistor M3 and the MOS transistor M4; the drain of the MOS transistor M3 forms the start output terminal set _ Ipa of the start circuit and is connected to IPTATaA reference current source circuit; the drain of the MOS transistor M4 forms the start output terminal set _ Ipb of the start circuit and is connected to IPTATbA reference current source circuit; the source of the MOS transistor M5 and the lower plate of the capacitor C1 are connected to the ground GND.
In the above scheme, IPTATaThe reference current source circuit consists of MOS tubes M27-M45; the sources of the MOS transistors M27-M30 are connected to a power supply VDD; the gate of MOS transistor M27-M30 is connected with the drain of MOS transistor M28 and the source of MOS transistor M32, and forms IPTATaThe bias current output end Ipa1 of the reference current source circuit is connected with the grid electrode of the MOS tube M18 of the temperature compensation circuit; the drain electrode of the MOS transistor M27 is connected with the source electrode of the MOS transistor M31; the drain electrode of the MOS transistor M29 is connected with the source electrode of the MOS transistor M33; the drain electrode of the MOS transistor M30 is connected with the source electrode of the MOS transistor M34; the gates of the MOS transistors M31-M34 are connected with the drains of the MOS transistors M32 and M36 to form IPTATaBias of reference current source circuitThe current output end Ipa2 is connected to the grid of the MOS tube M21 of the temperature compensation circuit; the gates of MOS transistors M35-M38 are connected to the drains of MOS transistors M31 and M35 to form IPTATaThe starting input end set _ Ipa of the reference current source circuit is connected to the starting circuit; the drains of the MOS tubes M33 and M37 are connected; the drains of the MOS tubes M34 and M38 are connected; the gates of the MOS tubes M39, M43 and M45 are connected and are connected to the source electrode of the MOS tube M35 and the drain electrode of the MOS tube M39; the sources of the MOS transistors M39-M40 are connected and are connected to the drain of the MOS transistor M43; the source electrode of the MOS transistor M36 is connected with the drain electrode of the MOS transistor M40; the gates of the MOS transistors M40-M41 are connected and are connected to the source electrode of the MOS transistor M37 and the drain electrode of the MOS transistor M41; the sources of the MOS transistors M41-M42 are connected and are connected to the drain of the MOS transistor M44; the gates of the MOS transistors M42 and M44 are connected, and are connected to the source of the MOS transistor M38 and the drain of the MOS transistor M42; the sources of the MOS transistors M43-M44 are connected and are connected to the drain of the MOS transistor M45; the source of the MOS transistor M45 is connected to ground GND.
In the above scheme, IPTATbThe reference current source circuit consists of MOS tubes M6-M17; the sources of the MOS transistors M6-M8 are connected to a power supply VDD; the gates of the MOS transistors M6-M8 are connected and are connected to the drain of the MOS transistor M6 and the source of the MOS transistor M9; the drain electrode of the MOS transistor M7 is connected with the source electrode of the MOS transistor M10; the drain electrode of the MOS transistor M8 is connected with the source electrode of the MOS transistor M11; the gates of the MOS tubes M9-M11 are connected and are connected to the drains of the MOS tubes M9 and M12; the gates of the MOS transistors M12-M13 are connected and are connected to the drains of the MOS transistors M10 and M13 to form IPTATbThe reference current source circuit starting input end set _ Ipb is connected to the starting circuit; the source electrode of the MOS transistor M12 is connected with the drain electrode of the MOS transistor M14; the gates of the MOS transistors M14-M15 are connected and are connected to the source electrode of the MOS transistor M13 and the drain electrode of the MOS transistor M15; the source electrode of the MOS transistor M14 is connected with the drain electrode of the MOS transistor M16; the gates of the MOS transistors M16-M17 are connected with the drains of the MOS transistors M11 and M17 to form IPTATbA bias current output terminal Ipb1 of the reference current source circuit, and connected to the temperature compensation circuit; the sources of the MOS transistors M15-M17 are connected to the ground GND.
In the scheme, the temperature compensation circuit consists of MOS tubes M18-M26 and a capacitor C2; the sources of the MOS transistors M18-M20 are connected to a power supply VDD; the gate of MOS transistor M18 forms the bias current input of the temperature compensation circuitTerminal Ipa1, connected to IPTATaA reference current source circuit; the drain electrode of the MOS transistor M18 is connected with the source electrode of the MOS transistor M21; the gates of the MOS transistors M19-M20 are connected and are connected to the drain of the MOS transistor M19 and the source of the MOS transistor M22; the drain electrode of the MOS transistor M20 is connected with the source electrode of the MOS transistor M23; the gate of MOS transistor M21 forms the bias current input terminal Ipa2 of the temperature compensation circuit and is connected to IPTATaA reference current source circuit; the gates of the MOS tubes M22-M23 are connected and are connected with the drains of the MOS tubes M21, M22 and M26; the gates of the MOS transistors M24-M25 are connected and are connected to the drains of the MOS transistors M23-M24; the source electrode of the MOS transistor M24 is connected with the drain electrode of the MOS transistor M25, and is connected to the upper plate of the capacitor C2 to be used as the output end of the temperature compensation circuit, namely the whole reference voltage source; the gate of MOS transistor M26 forms the bias current input terminal Ipb1 and is connected to IPTATbA reference current source circuit; the source of the MOS transistor M25-M26 and the lower plate of the capacitor C2 are connected to the ground GND.
In the above scheme, the MOS transistor M24 is a MOS transistor with a standard voltage of 1.8V, and the MOS transistor M25 is a MOS transistor with a standard voltage of 3.3V.
Compared with the prior art, the utility model has the characteristics of as follows:
1. the power consumption is low and is only in the nano watt level;
2. because a passive resistor, a BJT (bipolar junction transistor) or a diode is not used, the layout area is greatly reduced, and the production cost is reduced;
3. the output reference voltage has extremely high power supply rejection ratio and low voltage regulation rate, and the performance is good;
4. and the current subtraction technology is adopted to realize temperature compensation and reduce quiescent current.
Drawings
Fig. 1 is a circuit diagram of a low-voltage nanowatt-level full CMOS current mode reference voltage source according to the present invention.
Fig. 2 is a schematic diagram of a core circuit of a low-voltage nanowatt-level full CMOS current mode reference voltage source according to the present invention.
Detailed Description
The technical scheme of the utility model is described in detail below with the accompanying drawings and embodiments:
a low-voltage nano-watt full CMOS current mode reference voltage source is shown in FIG. 1 and comprises a start-up circuit IPTATaReference current source circuit, IPTATbA reference current source circuit and a temperature compensation circuit.
The starting circuit is connected toPTATaReference current source circuit and IPTATbAnd the reference current source circuit provides current when the reference voltage source is started, so that the reference voltage source gets rid of a degenerate bias point and enters a normal working state. In the present invention, the start circuit is composed of a MOS transistor M1-M5 and a capacitor C1. The sources of MOS transistor M1 and MOS transistor M2 are connected to power supply VDD. The grid electrodes of the MOS tubes M1-M5, the drain electrode of the MOS tube M2 and the upper plate of the capacitor C1 are connected. And the MOS transistor M1 is connected with the drain electrode of the MOS transistor M5 and is connected with the source electrodes of the MOS transistor M3 and the MOS transistor M4. The drain of the MOS transistor M3 forms the start output terminal set _ Ipa of the start circuit and is connected to IPTATaThe grid electrode of MOS tube M35-M38 and the drain electrode of MOS tube M31 and M35 of the reference current source circuit. The drain of the MOS transistor M4 forms the start output terminal set _ Ipb of the start circuit and is connected to IPTATbThe grid electrode of MOS tube M12-M13 and the drain electrode of MOS tube M10, M13 of the reference current source circuit. The source of the MOS transistor M5 and the lower plate of the capacitor C1 are connected to the ground GND. When the power supply is powered on, the gate bias is provided for the MOS transistor M35 and the MOS transistor M13, so that the circuit works normally.
IPTATaA reference current source circuit for generating a bias current IPa(ii) a Meanwhile, a source coupling differential pair is adopted to replace a resistor and a Bipolar transistor adopted in a traditional reference voltage source, the power supply rejection ratio of the reference voltage source is improved, and current bias is provided for the temperature compensation circuit. In the utility model, IPTATaThe reference current source circuit is composed of MOS transistors M27-M45. The sources of the MOS transistors M27-M30 are connected to a power supply VDD. The gate of MOS transistor M27-M30 is connected with the drain of MOS transistor M28 and the source of MOS transistor M32, and forms IPTATaAnd the bias current output end Ipa1 of the reference current source circuit is connected with the grid of the MOS tube M18 of the temperature compensation circuit. The drain electrode of the MOS transistor M27 is connected with the source electrode of the MOS transistor M31. The drain electrode of the MOS transistor M29 is connected with the source electrode of the MOS transistor M33. The drain electrode of the MOS transistor M30 is connected with the source electrode of the MOS transistor M34. The gates of the MOS transistors M31-M34 are connected with the drains of the MOS transistors M32 and M36 to form IPTATaAnd the bias current output end Ipa2 of the reference current source circuit is connected to the gate of the MOS transistor M21 of the temperature compensation circuit. The gates of the MOS tubes M35-M38 are connected to the drains of the MOS tubes M31 and M35 and the drain of the MOS tube M3 of the starting circuit. The drains of the MOS tubes M33 and M37 are connected. The drains of the MOS tubes M34 and M38 are connected. The gates of the MOS tubes M39, M43 and M45 are connected and are connected to the source of the MOS tube M35 and the drain of the MOS tube M39. The sources of the MOS transistors M39-M40 are connected and are connected to the drain of the MOS transistor M43. The source electrode of the MOS transistor M36 is connected with the drain electrode of the MOS transistor M40. The gates of MOS transistors M40-M41 are connected to the source of MOS transistor M37 and the drain of MOS transistor M41. The sources of the MOS transistors M41-M42 are connected and are connected to the drain of the MOS transistor M44. The gates of the MOS transistors M42 and M44 are connected to the source of the MOS transistor M38 and the drain of the MOS transistor M42. The sources of the MOS transistors M43-M44 are connected and are connected to the drain of the MOS transistor M45. The source of the MOS transistor M45 is connected to ground GND.
IPTATbThe reference current source circuit is based on an Oguy current source, is a self-biased current source, adopts a MOS tube M16 working in a linear region to replace a passive resistor in a traditional band gap structure, and generates a bias current IPb(ii) a Meanwhile, a cascode current mirror is adopted to suppress power supply noise and provide current bias for the temperature compensation circuit. In the utility model, IPTATbThe reference current source circuit is composed of MOS tubes M6-M17. The sources of the MOS transistors M6-M8 are connected to a power supply VDD. The gates of MOS transistors M6-M8 are connected to the drain of MOS transistor M6 and the source of MOS transistor M9. The drain electrode of the MOS transistor M7 is connected with the source electrode of the MOS transistor M10. The drain electrode of the MOS transistor M8 is connected with the source electrode of the MOS transistor M11. The gates of the MOS transistors M9-M11 are connected and are connected to the drains of the MOS transistors M9 and M12.The gates of the MOS tubes M12-M13 are connected to the drains of the MOS tubes M10 and M13 and the drain of the MOS tube M4 of the starting circuit. The source electrode of the MOS transistor M12 is connected with the drain electrode of the MOS transistor M14. The gates of MOS transistors M14-M15 are connected to the source of MOS transistor M13 and the drain of MOS transistor M15. The source electrode of the MOS transistor M14 is connected with the drain electrode of the MOS transistor M16. The gates of the MOS transistors M16-M17 are connected with the drains of the MOS transistors M11 and M17 to form IPTATbThe bias current output terminal Ipb1 of the reference current source circuit is connected to the gate of the MOS transistor M26 of the temperature compensation circuit. The sources of the MOS transistors M15-M17 are connected to the ground GND.
The temperature compensation circuit adopts a PMOS tube cascode current mirror to compensate the temperature of the semiconductor devicePTATaReference current source circuit and IPTATbBias current I proportional to temperature generated by reference current source circuitPaAnd IPbAre respectively represented by k1And k2Multiplying to obtain a reference current I independent of temperatureREFAnd drives the MOS transistor M24 and the MOS transistor M25 in the temperature compensation circuit to obtain an output voltage which is not influenced by the power supply voltage and the temperature change. And a cascode current mirror is adopted to suppress power supply noise. The current difference is adopted, so that not only can temperature compensation be realized, but also the power consumption can be obviously reduced. In the present invention, the temperature compensation circuit is composed of a MOS transistor M18-M26 and a capacitor C2. The sources of the MOS transistors M18-M20 are connected to a power supply VDD. The gate of MOS transistor M18 forms the bias current input terminal Ipa1 of the temperature compensation circuit and is connected to IPTATaThe grid electrode of the MOS tube M27-M30, the drain electrode of the MOS tube M28 and the source electrode of the MOS tube M32 of the reference current source circuit. The drain electrode of the MOS transistor M18 is connected with the source electrode of the MOS transistor M21. The gates of MOS transistors M19-M20 are connected to the drain of MOS transistor M19 and the source of MOS transistor M22. The drain electrode of the MOS transistor M20 is connected with the source electrode of the MOS transistor M23. The gate of MOS transistor M21 forms the bias current input terminal Ipa2 of the temperature compensation circuit and is connected to IPTATaThe grid electrode of MOS tube M31-M34 and the drain electrode of MOS tube M32, M36 of the reference current source circuit. The gates of the MOS tubes M22-M23 are connected and are connected to the drains of the MOS tubes M21, M22 and M26. The gates of the MOS transistors M24-M25 are connected and are connected to the drains of the MOS transistors M23-M24. The source of MOS transistor M24 is connected to the drain of MOS transistor M25, and to the upper plate of capacitor C2,as a reference voltage output terminal. The gate of MOS transistor M26 forms the bias current input terminal Ipb1 and is connected to IPTATbThe grid electrode of MOS tube M16-M17 and the drain electrode of MOS tube M11, M17 of the reference current source circuit. The source of the MOS transistor M25-M26 and the lower plate of the capacitor C2 are connected to the ground GND.
Referring to fig. 2, the core circuit module of the present invention includes IPTATaReference current source circuit, IPTATbA reference current source circuit and a temperature compensation circuit. 2 reference current source circuits respectively generating I proportional to temperaturePaAnd IPbAnd each is represented by k1And k2And the multiples are subjected to difference to obtain a reference current independent of the temperature, and the reference current is supplied to a temperature compensation circuit.
IPTATaMOS tubes M39-M42 of the reference current source circuit work in a subthreshold region, and MOS tubes M43-M44 work in a saturation region.
The drain current of the MOS transistor operating in the saturation region can be expressed as:
wherein u (═ u)0(T0/T)m) Is the electron mobility of the MOS transistor; t is0Is a reference temperature; t is the absolute temperature; u. of0Is the reference temperature T0Electron mobility of (a); m is a temperature index; cOXIs a gate oxide capacitance; k is W/L is the width-length ratio of the MOS tube; vGSIs the gate-source voltage of the MOS transistor; vTHIs the threshold voltage of the MOS transistor.
The difference between the gate-source voltages of MOS transistor M43 and MOS transistor M44 can be expressed as:
the drain current of the MOS tube working in the subthreshold region is as follows:
in the formula,VT(＝kBt/q) is a thermal voltage; k is a radical ofBIs the boltzmann constant, q is the electronic charge, η is the subthreshold region slope factor △ VpCan also be expressed as:
from (2) and (4), IpaCan be expressed as:
wherein
When V isT0At room temperature T0Time VTThe value, equation (5), versus temperature can be expressed as:
since m is a process dependent temperature coefficient, which is about 1.5 for a common MOS transistor, I ispaHas a positive temperature coefficient.
IPTATbThe MOS transistor M16 of the reference current source circuit works in a linear region, the MOS transistor M17 works in a saturation region, and the MOS transistors M6-M15 work in a sub-threshold region.
Reference current IPbThe gate-source voltage V of the MOS transistor M16GS16And drain-source voltage VDS16And (4) generating. A MOS transistor M17 is added in the circuit to provide bias voltage for the MOS transistor M16.
The leakage current of the MOS transistor M16 is:
the drain-source voltage of the MOS transistor M16 is:
the leakage current of the MOS transistor M17 is:
in addition, the method can be used for producing a composite material
In the formula, k2The leakage current ratio of the MOS transistor M17 and the MOS transistor M16 is shown.
From (8), (9), (10) and (11) it can be derived the I generated by the reference current sourcePbComprises the following steps:
wherein,
the relationship between equation (12) and temperature can be expressed as:
thus, IPbHas a positive temperature coefficient.
The MOS tube M24-M25 of the temperature compensation circuit works in a subthreshold region, the MOS tube M24 is a MOS tube with the standard voltage of 1.8V, and the MOS tube M25 is a MOS tube with the standard voltage of 3.3V. Obtaining a reference current I independent of temperature by using two currents with the same temperature coefficient to make differenceREFThe reference current I is provided for the MOS transistor M24 and the MOS transistor M25 in the temperature compensation circuitREF。
Obtaining the difference value I of two positive temperature coefficient currents by using a current mirrorREFReference current IREFThe expression of (a) is:
IREF＝k2IPb-k1IPa(15)
the relationship between equation (15) and temperature can be expressed as:
as can be seen from (7), (14) and (16), by adjusting k1、k2The ratio of the width-to-length ratios of the MOS transistors M39-M44 and the MOS transistors M14-M17 can obtain the reference current independent of the temperature.
Reference voltage VREFCan be obtained by making difference between different gate-source voltages of MOS transistor M24 and MOS transistor M25, and reference voltage V is obtained according to I-V characteristic of MOS transistor in subthreshold regionREFCan be expressed as:
wherein, tOX，24And tOX，25Is the thickness of the oxide layer of MOS transistor M24 and MOS transistor M25.
The threshold voltage of the NMOS tube has a negative temperature coefficient, and the expression is as follows:
VTH＝VTH0-κT (18)
in the formula, VTH0Denotes the threshold voltage at an absolute temperature of 0K, and κ is VTHTemperature coefficient of (k ═ dV) TC (k ═ dV)THdT), therefore △ VTH△ V with negative temperature coefficientTHAnd V having a positive temperature coefficientTThe output reference voltage V independent of temperature can be obtained through regulationREF。
The threshold voltage can further be expressed as:
in the formula,Sidenotes the relative dielectric constant, N, of the silicon substrateADoping the substrate with a concentration of niIs the intrinsic carrier concentration, EgIs a band gap, psiBIs the difference between the Fermi level potential and the intrinsic level potential, VTHTemperature coefficient of (k ═ dV)TH/dT) can be expressed as:
in the formula, NcIs the effective density of states of the conduction band, NvNeglecting the bulk effect, the effective density of states in the valence band can be expressed as the relation between the output reference voltage and the temperature
Let the temperature coefficient of the reference voltage be zero, the width-to-length ratio of the MOS transistor can be determined:
it can be seen that by pairing K24/K25Carefully adjusting to obtain a reference voltage with zero temperature coefficient, and adding a capacitor C2To improve the power supply voltage rejection ratio.
The utility model discloses do not use passive resistance, diode or triode, with CMOS technology compatibility, reduced the territory area greatly, reduced manufacturing cost, the low power dissipation has high power suppression ratio and low-voltage adjustment rate simultaneously. Under the SMIC 0.18-umCMOS process standard, a Cadence spectrum simulator is adopted for design simulation, and simulation results show that under the power supply voltage of 1.8V, the power supply voltage suppression ratio of the reference voltage source is-61.8 dB at low frequency, is-62.5 dB at high frequency, has a temperature coefficient of 17.5 ppm/DEG C within the temperature range of-45-150 ℃, and has the power consumption of 133.8 nW; the simulation results verify the effectiveness of the above measures with a supply voltage regulation rate of 0.23% in the range of 0.7V to 3.3V supply voltages.
Claims (6)
1. A low-voltage nano-watt full CMOS current mode reference voltage source is characterized by comprising a starting circuit and an IPTATaReference current source circuit, IPTATbA reference current source circuit and a temperature compensation circuit;
the starting circuit is connected toPTATaReference current source circuit and IPTATbThe reference current source circuit provides current when the reference voltage source is started, so that the reference voltage source gets rid of a degenerated bias point and enters a normal working state;
IPTATathe reference current source circuit generates oneBias current IPaProviding a current bias for the temperature compensation circuit;
IPTATbthe reference current source circuit generates a bias current IPbProviding a current bias for the temperature compensation circuit;
temperature compensation circuit IPTATaReference current source circuit and IPTATbBias current I proportional to temperature generated by reference current source circuitPaAnd IPbRespectively making difference according to different multiples to obtain a reference current I independent of temperatureREFAnd driving the MOS tube in the temperature compensation circuit to obtain an output voltage which is not influenced by the power supply voltage and the temperature change.
2. The low-voltage nanowatt-level full CMOS current-mode reference voltage source of claim 1, wherein: the starting circuit consists of MOS transistors M1-M5 and a capacitor C1;
the source electrodes of the MOS transistor M1 and the MOS transistor M2 are connected with a power supply VDD; the grid electrode of the MOS tube M1-M5, the drain electrode of the MOS tube M2 and the upper electrode plate of the capacitor C1 are connected; the MOS transistor M1 is connected with the drain electrode of the MOS transistor M5 and is connected with the source electrodes of the MOS transistor M3 and the MOS transistor M4; the drain of the MOS transistor M3 forms the start output terminal set _ Ipa of the start circuit and is connected to IPTATaA reference current source circuit; the drain of the MOS transistor M4 forms the start output terminal set _ Ipb of the start circuit and is connected to IPTATbA reference current source circuit; the source of the MOS transistor M5 and the lower plate of the capacitor C1 are connected to the ground GND.
3. The low-voltage nanowatt-level full CMOS current-mode reference voltage source of claim 1, wherein: i isPTATaThe reference current source circuit consists of MOS tubes M27-M45;
the sources of the MOS transistors M27-M30 are connected to a power supply VDD; the gate of MOS transistor M27-M30 is connected with the drain of MOS transistor M28 and the source of MOS transistor M32, and forms IPTATaThe bias current output end Ipa1 of the reference current source circuit is connected with the grid electrode of the MOS tube M18 of the temperature compensation circuit; the drain electrode of the MOS transistor M27 is connected with the source electrode of the MOS transistor M31; the drain electrode of the MOS transistor M29 and the source electrode of the MOS transistor M33 are in phaseConnecting; the drain electrode of the MOS transistor M30 is connected with the source electrode of the MOS transistor M34; the gates of the MOS transistors M31-M34 are connected with the drains of the MOS transistors M32 and M36 to form IPTATaThe bias current output end Ipa2 of the reference current source circuit is connected to the grid of the MOS tube M21 of the temperature compensation circuit; the gates of MOS transistors M35-M38 are connected to the drains of MOS transistors M31 and M35 to form IPTATaThe starting input end set _ Ipa of the reference current source circuit is connected to the starting circuit; the drains of the MOS tubes M33 and M37 are connected; the drains of the MOS tubes M34 and M38 are connected; the gates of the MOS tubes M39, M43 and M45 are connected and are connected to the source electrode of the MOS tube M35 and the drain electrode of the MOS tube M39; the sources of the MOS transistors M39-M40 are connected and are connected to the drain of the MOS transistor M43; the source electrode of the MOS transistor M36 is connected with the drain electrode of the MOS transistor M40; the gates of the MOS transistors M40-M41 are connected and are connected to the source electrode of the MOS transistor M37 and the drain electrode of the MOS transistor M41; the sources of the MOS transistors M41-M42 are connected and are connected to the drain of the MOS transistor M44; the gates of the MOS transistors M42 and M44 are connected, and are connected to the source of the MOS transistor M38 and the drain of the MOS transistor M42; the sources of the MOS transistors M43-M44 are connected and are connected to the drain of the MOS transistor M45; the source of the MOS transistor M45 is connected to ground GND.
4. The low-voltage nanowatt-level full CMOS current-mode reference voltage source of claim 1, wherein: i isPTATbThe reference current source circuit consists of MOS tubes M6-M17;
the sources of the MOS transistors M6-M8 are connected to a power supply VDD; the gates of the MOS transistors M6-M8 are connected and are connected to the drain of the MOS transistor M6 and the source of the MOS transistor M9; the drain electrode of the MOS transistor M7 is connected with the source electrode of the MOS transistor M10; the drain electrode of the MOS transistor M8 is connected with the source electrode of the MOS transistor M11; the gates of the MOS tubes M9-M11 are connected and are connected to the drains of the MOS tubes M9 and M12; the gates of the MOS transistors M12-M13 are connected and are connected to the drains of the MOS transistors M10 and M13 to form IPTATbThe reference current source circuit starting input end set _ Ipb is connected to the starting circuit; the source electrode of the MOS transistor M12 is connected with the drain electrode of the MOS transistor M14; the gates of the MOS transistors M14-M15 are connected and are connected to the source electrode of the MOS transistor M13 and the drain electrode of the MOS transistor M15; the source electrode of the MOS transistor M14 is connected with the drain electrode of the MOS transistor M16; the gates of the MOS transistors M16-M17 are connected with the drains of the MOS transistors M11 and M17 to form IPTATbOf reference current source circuitsA bias current output terminal Ipb1 coupled to the temperature compensation circuit; the sources of the MOS transistors M15-M17 are connected to the ground GND.
5. The low-voltage nanowatt-level full CMOS current-mode reference voltage source of claim 1, wherein: the temperature compensation circuit consists of MOS tubes M18-M26 and a capacitor C2;
the sources of the MOS transistors M18-M20 are connected to a power supply VDD; the gate of MOS transistor M18 forms the bias current input terminal Ipa1 of the temperature compensation circuit and is connected to IPTATaA reference current source circuit; the drain electrode of the MOS transistor M18 is connected with the source electrode of the MOS transistor M21; the gates of the MOS transistors M19-M20 are connected and are connected to the drain of the MOS transistor M19 and the source of the MOS transistor M22; the drain electrode of the MOS transistor M20 is connected with the source electrode of the MOS transistor M23; the gate of MOS transistor M21 forms the bias current input terminal Ipa2 of the temperature compensation circuit and is connected to IPTATaA reference current source circuit; the gates of the MOS tubes M22-M23 are connected and are connected with the drains of the MOS tubes M21, M22 and M26; the gates of the MOS transistors M24-M25 are connected and are connected to the drains of the MOS transistors M23-M24; the source electrode of the MOS transistor M24 is connected with the drain electrode of the MOS transistor M25, and is connected to the upper plate of the capacitor C2 to be used as the output end of the temperature compensation circuit, namely the whole reference voltage source; the gate of MOS transistor M26 forms the bias current input terminal Ipb1 and is connected to IPTATbA reference current source circuit; the source of the MOS transistor M25-M26 and the lower plate of the capacitor C2 are connected to the ground GND.
6. The low-voltage nanowatt-level full CMOS current-mode reference voltage source of claim 5, wherein: the MOS transistor M24 is a MOS transistor with a standard voltage of 1.8V, and the MOS transistor M25 is a MOS transistor with a standard voltage of 3.3V.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106527559A (en) * | 2016-12-28 | 2017-03-22 | 桂林电子科技大学 | Low-voltage nanowatt-scale full CMOS current mode reference voltage source |
| CN109164867A (en) * | 2018-11-16 | 2019-01-08 | 西安电子科技大学 | Full MOS reference current generating circuit |
| CN109388172A (en) * | 2018-11-23 | 2019-02-26 | 西安电子科技大学 | A kind of low-voltage and low-power dissipation cmos voltage reference circuit |
| CN114721459A (en) * | 2022-04-06 | 2022-07-08 | 深圳市中芯同创科技有限公司 | High-stability low-power-consumption linear voltage-stabilizing integrated circuit composed of multiple MOS (metal oxide semiconductor) tubes |
-
2016
- 2016-12-28 CN CN201621454868.XU patent/CN206292654U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106527559A (en) * | 2016-12-28 | 2017-03-22 | 桂林电子科技大学 | Low-voltage nanowatt-scale full CMOS current mode reference voltage source |
| CN109164867A (en) * | 2018-11-16 | 2019-01-08 | 西安电子科技大学 | Full MOS reference current generating circuit |
| CN109388172A (en) * | 2018-11-23 | 2019-02-26 | 西安电子科技大学 | A kind of low-voltage and low-power dissipation cmos voltage reference circuit |
| CN114721459A (en) * | 2022-04-06 | 2022-07-08 | 深圳市中芯同创科技有限公司 | High-stability low-power-consumption linear voltage-stabilizing integrated circuit composed of multiple MOS (metal oxide semiconductor) tubes |
| CN114721459B (en) * | 2022-04-06 | 2023-09-01 | 深圳市中芯同创科技有限公司 | High-stability low-power-consumption linear voltage-stabilizing integrated circuit composed of multiple MOS (metal oxide semiconductor) tubes |
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