CN206259356U - Packaging of photoelectric device structure based on metal bonding - Google Patents
Packaging of photoelectric device structure based on metal bonding Download PDFInfo
- Publication number
- CN206259356U CN206259356U CN201621341212.7U CN201621341212U CN206259356U CN 206259356 U CN206259356 U CN 206259356U CN 201621341212 U CN201621341212 U CN 201621341212U CN 206259356 U CN206259356 U CN 206259356U
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- Prior art keywords
- package substrates
- photoelectric device
- photoelectric
- packaging
- substrate
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 16
- 239000002184 metal Substances 0.000 title abstract description 8
- 229910052751 metal Inorganic materials 0.000 title abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 238000001465 metallisation Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000005388 borosilicate glass Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 14
- 239000004020 conductor Substances 0.000 description 7
- 238000005538 encapsulation Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000011162 core material Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000005622 photoelectricity Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 238000010312 secondary melting process Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Light Receiving Elements (AREA)
Abstract
Disclose a kind of packaging of photoelectric device structure based on metal bonding.According to embodiment, a kind of packaging of photoelectric device structure can include photoelectric chip and package substrates.Photoelectric chip includes：Substrate, with each other relative first surface and second surface；The photoelectric device formed on substrate；And the electrode for photoelectric device for being formed on the first surface.Package substrates have each other relative first surface and second surface, and including extending to the conductive channel of second surface from first surface.By its first surface towards being stacked together with package substrates in the way of package substrates, and the electrode formed on the first surface of photoelectric chip is bonded together photoelectric chip to the corresponding conductive channel in package substrates.
Description
Technical field
The utility model is related to packaging of photoelectric device, in particular it relates to be based on the packaging of photoelectric device structure of metal bonding.
Background technology
In the conventional back of the body enters formula packaging of photoelectric device, tin ball is planted generally on the electrode of naked core, be thus welded to encapsulation
On printed circuit board (PCB) (PCB).In order to increase reliability, filler can be filled between naked core and encapsulation pcb board.Due to conventional envelope
Dress PCB material and naked core material (Si) thermal coefficient of expansion differ greatly, it is easy to ftractureed in temperature change.
In addition, from for its follow-up use, generally require the back of the body after encapsulation is entered into formula photoelectric device to be welded on again accordingly
Circuit board on.That is, there is secondary welding.Using conventional scolding tin, plant ball and there is secondary melting process.And as using low
Warm scolding tin, it is very high to welding procedure and solder requirement, it is easy to Welding Problems occur.
Need to provide new encapsulation technology to solve the above problems at least in part.
The content of the invention
In view of this, the purpose of this utility model is at least in part to provide a kind of photoelectric device based on metal bonding
Encapsulating structure and its manufacture method.
According to one side of the present utility model, there is provided a kind of packaging of photoelectric device structure, including photoelectric chip and envelope
Dress substrate.Photoelectric chip includes：Substrate, with each other relative first surface and second surface；The photoelectricity formed on substrate
Device；And the electrode for photoelectric device for being formed on the first surface.Package substrates have each other relative first surface
And second surface, and including extending to the conductive channel of second surface from first surface.Photoelectric chip with its first surface towards
The mode of package substrates stacks together with package substrates, and on the first surface of photoelectric chip formed electrode and package substrates
In corresponding conductive channel be bonded together.
According to embodiment of the present utility model, can not only reduce packaging technology and use difficulty, can also effectively improve
The reliability and electricity conversion of device.
Brief description of the drawings
By description referring to the drawings to the utility model embodiment, of the present utility model above-mentioned and other mesh
, feature and advantage will be apparent from, in the accompanying drawings：
Fig. 1 shows the schematic section of the photoelectric chip according to the utility model embodiment；
Fig. 2 shows the schematic section of the package substrates according to the utility model embodiment；
Fig. 3 shows the signal being bonded to photoelectric chip and package substrates according to the utility model embodiment
Figure；
Fig. 4 shows the schematic section of the packaging of photoelectric device structure according to the utility model embodiment.
Through accompanying drawing, same or analogous reference represents same or analogous part.
Specific embodiment
Hereinafter, will be described with reference to the accompanying drawings embodiment of the present utility model.However, it should be understood that these descriptions are example
Property, and it is not intended to limit scope of the present utility model.Additionally, in the following description, eliminate to known features and technology
Description, to avoid unnecessarily obscuring concept of the present utility model.
The various structural representations according to the utility model embodiment are shown in the drawings.These figures are not in proportion
Draw, wherein for the purpose of clear expression, being exaggerated some details, and some details may be eliminated.Shown in figure
Various regions, the shape of layer and the relative size between them, the position relationship for going out only be it is exemplary, in practice may be by
In manufacturing tolerance or technology restriction and deviation, and those skilled in the art has according to actually required can design in addition
Different shapes and sizes, the regions/layers of relative position.
In context of the present utility model, when one layer/element is referred to as positioned at another layer/element " on " when, the layer/unit
Part can there may be intermediate layer/element on another layer/element, or between them.In addition, if in one kind
In one layer/element be located at another layer/element " on ", then when turn towards when, that layer/element may be located at this is another for this
Layer/element D score.
Fig. 1 shows the schematic section of the photoelectric chip according to the utility model embodiment.
As shown in figure 1, photoelectric chip 100 according to the embodiment is e.g. on the substrate 100 after manufacture photoelectric device
The naked core for not yet encapsulating.Substrate 100 can be Semiconductor substrate such as silicon substrate, and including each other relative first surface 101-1S
With second surface 101-2S.First surface 101-1S and second surface 101-2S can be with substantially parallel to one another.For example, can be in silicon
Photoelectric device is manufactured by semiconductor technology on wafer, and Silicon Wafer is cut into slices, the wafer segment after section forms substrate 100,
And include the photoelectric device (and peripheral components that may be present) of manufacture on substrate 100.These photoelectric devices can include phase
The electrode zone 103 answered, for example, in the case of photodiode, anode and negative electrode.These electrode zones 103 for example can be with
It is the doped region in substrate 101, such as p-type doped region or N-shaped doped region.
In the first surface 101-1S sides of substrate 101, electrode 107 is could be formed with, be used to the electrode of photoelectric device
Region 103 is drawn out to outside, to carry out appropriate electrical connection.According to semiconductor fabrication process, can be in first surface 101-
1S sides form metallization stack (metalization), and electrode 107 can be included in this metallization stack.For example, golden
Categoryization lamination can include one or more layers interlayer dielectric layer 105, and through hole or groove can be formed in interlayer dielectric layer 105,
And conductive material such as metal is filled wherein, so as to form conductive channel.These conductive channels can include via (via) and/
Or metal interconnection (interconnect).For example, metallization stack can be formed by Damascus technics.These conductions are logical
Road may be constructed electrode 107, and each electrode 107 can be electrically connected with corresponding electrode zone 103.According to implementation of the present utility model
Example, electrode 107 can include Au or Ti.
Additionally, formed metallization stack when, can retain between each electrode 107 some electrically conductive materials 109 (but with
Electrode 107 is separated, to avoid unnecessary electrical connection).The conductive material 109 of residual can be with electrode 107 in identical technique
Middle formation, so their upper surface can be substantially coplanar.These conductive materials 109 help to maintain photoelectricity in follow-up bonding
The distance between chip 100 and package substrates, so as to help to strengthen mechanical strength.
In this example, photoelectric chip 100 can be carried on the back into formula, i.e. incident light can be from second surface 101-2S mono-
Side is incident.So, various parts such as electrode for being formed in first surface 101-1S sides etc. does not interfere with the incidence of light.
Fig. 2 shows the schematic section of the package substrates according to the utility model embodiment.
As shown in Fig. 2 the package substrates 200 according to the embodiment can include dielectric base, such as substrate of glass, ceramics
Substrate etc..In order to ensure reliability, especially for reply temperature change, the thermal coefficient of expansion of package substrates 200 can be with lining
The thermal coefficient of expansion at bottom 101 is substantially consistent.For example, in the case where substrate 101 is silicon substrate, package substrates 200 can be wrapped
Include Pyrex.So, the possibility ftractureed between chip 100 and package substrates 200 in temperature change can be reduced.
Package substrates 200 can have each other relative first surface 201-1S and second surface 201-2S.First surface
201-1S and second surface 201-2S can be with substantially parallel to one another.In package substrates 200, can be formed from first surface 201-
1S extends to the conductive channel 203 of second surface 201-2S.For example, can be formed that from first surface 201-1S the second table is extended to
Face 201-2S and fills conductive material such as metal in through hole T and forms conductive channel through the through hole T of package substrates 200
203.According to embodiment of the present utility model, conductive channel 203 can include AuPbTi or AuTi.In the figure 2 example, it is conductive
Material is formed on the bottom of through hole T and side wall.But, the utility model not limited to this, for example, conductive material can fill up it is logical
Hole T.
In technology of the present utility model, package substrate 200 then will be with second surface 201-2S towards photoelectric chip 100
Mode be stacked on photoelectric chip 100.Therefore, second surface 201-2S sides preferably can be flat.That is, conductive
The bottom surface of passage 203 can be substantially coplanar with the second surface 201-2S of package substrate 200.In addition, in first surface 201-
1S sides, conductive channel 203 is extended on first surface 201-1S, to be then electrically connected, for example, is welded to electricity
Road plate.
Package substrates 200 can be directed to the special package substrates that photoelectric chip 100 is specially designed.For example, package substrates
The layout of conductive channel 203 can be substantially the same with the layout of the Top electrode 107 of photoelectric chip 100 on 200.Then, encapsulation is worked as
When substrate 200 is mutually stacked with photoelectric chip 100, conductive channel 203 can be corresponded with electrode 107, and toward each other.
Or, package substrates 200 can be generic encapsulation substrate.For example, can be according to certain spacing, in package substrates
The array of conductive channel 203 is formed on 200.When package substrates 200 are mutually stacked with photoelectric chip 100, in package substrates 200
At least a portion conductive channel 203 can be corresponding with the electrode 107 on photoelectric chip 100, and toward each other.Certainly, it is this
General package substrates 200 can be used for other chips of layout different from photoelectric chip 100.
Fig. 3 shows the signal being bonded to photoelectric chip and package substrates according to the utility model embodiment
Figure.
As shown in figure 3, in bonder (not shown), photoelectric chip 100 mutually can be stacked with package substrates 200.Tool
Body ground, can make the first surface 101-1S sides of photoelectric chip 100 towards the second surface 201-2S mono- of package substrates 200
Side.Furthermore it is possible to adjust the position of photoelectric chip 100 and/or package substrates 200 so that the electrode 107 on photoelectric chip 100
Can be with the corresponding conductive channel 203 in alignment package substrate 200.
It is then possible to apply certain temperature (for example, about 400-500 DEG C) and pressure in bonder (for example, about
2000-4000mBar) so that (for example, because metal material is molten together with electrode 107 can bond together with conductive channel 203
Melt and combine togather).
According to embodiment of the present utility model, after bonding, can also be from the second surface 101-2S of photoelectric chip 100
Side, thinning photoelectric chip.For example, as shown in figure 4, can be with organic semiconductor device 101.According to an example, machinery side can be first passed through
Formula so that photoelectric chip 100 is thinned to about 140-200 μm；It is then possible to by chemical mode or chemical machinery mode so that
Photoelectric chip 100 is thinned to about 50-140 μm.This thinning thickness is conducive to photo-generated carrier to collect, and can effectively improve light
Electric transformation efficiency.
Encapsulating structure 300 according to the utility model embodiment can restrain oneself temperature (up to more than about 400 DEG C) higher,
Follow-up welding difficulty is reduced, and firmness (bond strength) is significantly improved, and significantly improves device reliability.In addition, follow-up
Filler need not be filled.
Embodiment of the present utility model is described above.But, the mesh that these embodiments are merely to illustrate that
, and be not intended to limit scope of the present utility model.Scope of the present utility model is limited by appended claims and its equivalent
It is fixed.Scope of the present utility model is not departed from, those skilled in the art can make various alternatives and modifications, these alternatives and modifications
Should all fall within the scope of the utility model.
Claims (7)
1. a kind of packaging of photoelectric device structure, including：
Photoelectric chip, including：
Substrate, with each other relative first surface and second surface；
The photoelectric device formed on substrate；And
The electrode for photoelectric device for being formed on the first surface；And
Package substrates, with each other relative first surface and second surface, and including extending to second surface from first surface
Conductive channel,
Wherein, photoelectric chip by its first surface towards being stacked together with package substrates in the way of package substrates, and light battery core
The electrode formed on the first surface of piece is bonded together to the corresponding conductive channel in package substrates.
2. packaging of photoelectric device structure according to claim 1, wherein, the thickness of photoelectric chip is 50-140 μm.
3. packaging of photoelectric device structure according to claim 1, wherein, electrode is included in the metallization formed on substrate and folds
In layer.
4. the packaging of photoelectric device structure according to claim 1 or 3, wherein, electrode includes Au or Ti.
5. packaging of photoelectric device structure according to claim 1, wherein, the thermal coefficient of expansion of package substrates and the heat of substrate
The coefficient of expansion is substantially consistent.
6. packaging of photoelectric device structure according to claim 5, wherein, substrate includes silicon, and package substrates include borosilicate glass
Glass.
7. packaging of photoelectric device structure according to claim 1, wherein, conductive channel includes AuPbTi or AuTi.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621341212.7U CN206259356U (en) | 2016-12-07 | 2016-12-07 | Packaging of photoelectric device structure based on metal bonding |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621341212.7U CN206259356U (en) | 2016-12-07 | 2016-12-07 | Packaging of photoelectric device structure based on metal bonding |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206259356U true CN206259356U (en) | 2017-06-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621341212.7U Expired - Fee Related CN206259356U (en) | 2016-12-07 | 2016-12-07 | Packaging of photoelectric device structure based on metal bonding |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106847936A (en) * | 2016-12-07 | 2017-06-13 | 清华大学 | Packaging of photoelectric device structure and its manufacture method based on metal bonding |
-
2016
- 2016-12-07 CN CN201621341212.7U patent/CN206259356U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106847936A (en) * | 2016-12-07 | 2017-06-13 | 清华大学 | Packaging of photoelectric device structure and its manufacture method based on metal bonding |
| WO2018103397A1 (en) * | 2016-12-07 | 2018-06-14 | 清华大学 | Photoelectric device package structure based on metallic bonding and manufacturing method thereof |
| US10510683B2 (en) | 2016-12-07 | 2019-12-17 | Tsinghua University | Packaging structures for metallic bonding based opto-electronic device and manufacturing methods thereof |
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| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170616 Termination date: 20201207 |
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| CF01 | Termination of patent right due to non-payment of annual fee |