CN206195725U - Take oscillator circuit of spread spectrum function - Google Patents
Take oscillator circuit of spread spectrum function Download PDFInfo
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- CN206195725U CN206195725U CN201621306470.1U CN201621306470U CN206195725U CN 206195725 U CN206195725 U CN 206195725U CN 201621306470 U CN201621306470 U CN 201621306470U CN 206195725 U CN206195725 U CN 206195725U
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Abstract
The utility model provides a take oscillator circuit of spread spectrum function, it includes oscillator module and modulated circuit. The oscillator module includes first electric current source, second electric current source, first switch, second switch, electric capacity and logic circuit. Modulated circuit includes cycle modulation module and modulation module at random, cycle modulation module output cyclic variation's first modulation charging current, and/or from node ISN extraction cyclic variation's first modulation discharge current, in order to make oscillator circuit's spread spectrum point sexual periodicity distributes, charging current to node ISP is maked to the second of modulation module output random variation at random, and/or follows the second modulation discharge current of node ISN extraction random variation, with the modulation trembling frequently of every spread spectrum point of oscillator circuit. Compared with the prior art, the utility model discloses a modulation mode of cycle modulation and chopping phase combination at random to reduce the static noise that carrier frequency arouses because of making at random.
Description
【Technical field】
The utility model is related to circuit design field, oscillator electricity of more particularly to a kind of low static noise with spread spectrum function
Road.
【Background technology】
D class power amplifiers have the advantages that high efficiency, low-power consumption, are widely used in the electric equipments such as TV, mobile phone.But
That its unique switching characteristic can produce di/dt and dv/dt signals high, and with jamming bandwidth wider, these voltages and
Current impulse can introduce larger alternating current in the circuit element of physics and parasitism respectively, produce conduction and radiated noise.
Existing technology generally uses the oscillator circuit structure with spread spectrum function, and the circuit structure can cycle " random " change one by one
The frequency of sawtooth waveforms so that the sawtooth wave frequency rate, that oscillator is produced changes near centre frequency, fixed frequency is concentrated on by original
Energy spread at rate reduces the effect of EMI (electromagnetic interference) so as to reach to more side frequency points.But, " random "
The carrier frequency of modulation would generally bring the static noise in audiorange, cause D class power amplifiers quiescent noise to be lifted.
Therefore, it is necessary to provide a kind of improved technical scheme to solve the problems, such as above-mentioned static noise.
【Utility model content】
The purpose of this utility model is to provide a kind of pierce circuit with spread spectrum function, and it can reduce carrier frequency
The static noise caused because of Stochastic Modulation.
In order to solve the above problems, the utility model provides a kind of pierce circuit with spread spectrum function, and it includes vibration
Device module and modulation circuit.The oscillator module includes the first current source, the second current source, first switch, second switch, electricity
Hold and logic circuit, wherein, first current source is connected between power end and node ISP, the first current source output
Electric current on the basis of charging current, the benchmark charging current flows to node ISP from power end；First switch is connected to node
Between ISP and node O, second switch is connected between node O and node ISN；Second current source be connected to node ISN and
Between ground node, and discharge current on the basis of the electric current of second current source output, the reference discharge electric current is from node ISN
Flow direction ground node；Capacitance connection is between node O and ground node.The logic circuit is electric by the voltage of node O and the first benchmark
Pressure and the second reference voltage are compared, and when the voltage of node O is less than or equal to the second reference voltage, export the first logic level
Switch controlling signal and lock, to control first switch to turn on, second switch cut-off, be equal to or more than in the voltage of node O
The switch controlling signal of the second logic level is exported during the first reference voltage and is locked, to control second switch to turn on, first opens
Cut-off is closed, the voltage of the node O forms sawtooth oscillation signal.The modulation circuit includes periodic modulation module and random tune
Molding block, the periodic modulation module exports periodically variable first modulated charge current to node ISP, and/or from node
First modulation discharge current of ISN decimation periods change, to modulate the periodic distribution of the spread spectrum point of the pierce circuit,
Second modulated charge current of Stochastic Modulation module output change at random to node ISP, and/or from node ISN extract with
Machine change second modulation discharge current, with modulate the pierce circuit each spread spectrum point tremble frequency.
Further, the periodic modulation module includes cycle rate counter and multiple first modulating units, based on the saw
Tooth ripple oscillator signal or the switch controlling signal form the clock signal of the cycle rate counter, the cycle rate counter output
The binary number of periodically variable multidigit first, each first modulating unit can produce the first of predefined weight to modulate the branch that charges
First modulation electric discharge tributary of stream and predefined weight.The control end of each the first modulating unit and the binary number of the multidigit first
In corresponding one-bit digital signal be connected, each first modulating unit is based on its one-bit digital signal for terminating to of control, control
Whether it exports node ISP described in the first modulation charging Zhi Liuzhi；Control it whether to extract the first modulation from the node ISN to put
Electric tributary, the first modulation charging tributary of each first modulating unit output accumulates corresponding with the first binary number first and adjusts
Charging current processed；The first modulation electric discharge tributary that each first modulating unit is extracted accumulates corresponding with the first binary number the
One modulation discharge current, due to the first binary number cyclically-varying, the first modulated charge current and first modulates discharge current
Also can cyclically-varying therewith.
Further, each first modulating unit produces predefined weight with benchmark charging current described in estimated rate mirror image
The first modulation charging tributary, produce the first of predefined weight to modulate electric discharge with reference discharge electric current described in estimated rate mirror image
Tributary.
Further, first modulating unit includes metal-oxide-semiconductor M14, metal-oxide-semiconductor M15, switchs K1, switchs K2.Wherein, MOS
The source electrode of pipe M14 is connected with power end, and its drain electrode is connected through switching K1 with node ISP, and its grid is connected with node VISP, switch
The control end of K1 is connected with the control end of the first modulating unit；The drain electrode of metal-oxide-semiconductor M15 is connected through switching K2 with node ISN, its grid
Pole is connected with node VISN, and its source electrode is connected with ground node, switchs the control end of K2 and the control end of first modulating unit
It is connected.
Further, the Stochastic Modulation module includes random counter and multiple second modulating units, the random meter
Number devices export the binary number of multidigit second of each clock cycle change at random, based on the sawtooth oscillation signal or described open
The clock signal that control signal forms the random counter is closed, each second modulating unit can produce the second of predefined weight
Modulation charging tributary and the second modulation electric discharge tributary of predefined weight, the control end of each the second modulating unit and the multidigit the
Corresponding one-bit digital signal is connected in two binary numbers, and each second modulating unit is based on the one-bit digital that its control is terminated to
Signal, controls whether it exports the second modulation charging tributary to the node ISP；Control whether it extracts second from node ISN
Modulation electric discharge tributary, the second modulation charging tributary of each second modulating unit output accumulates the of the second binary number of correspondence
Two modulated charge currents, the second modulation electric discharge tributary that each second modulating unit is extracted accumulates the second binary number of correspondence
Second modulation discharge current, due to the second binary number change at random, the second modulated charge current and second modulates discharge current
Also can change at random therewith.
Further, each second modulating unit produces predefined weight with benchmark charging current described in estimated rate mirror image
The second modulation charging tributary, produce the second of predefined weight to modulate electric discharge with reference discharge electric current described in estimated rate mirror image
Tributary.
Further, second modulating unit includes metal-oxide-semiconductor M16, metal-oxide-semiconductor M17, switchs K3, switchs K4, wherein, MOS
The source electrode of pipe M16 is connected with power end, and its drain electrode is connected through switching K3 with node ISP, and its grid is connected with node VISP, switch
The control end of K3 is connected with the control end of the second modulating unit；The drain electrode of metal-oxide-semiconductor M17 is connected through switching K4 with node ISN, its grid
Pole is connected with node VISN, and its source electrode is connected with ground node, switchs the control end of K4 and the control end of second modulating unit
It is connected.
Further, the transformable minimum value of the first modulated charge current and the first modulation discharge current is adjusted more than second
The transformable minimum value of charging current processed and the second modulation discharge current, or, the first modulated charge current and first is modulated
The transformable minimum value of discharge current is more than the second modulated charge current and the transformable maximum of the second modulation discharge current
Value.
Further, first current source and the second current source include reference current source, metal-oxide-semiconductor M4, metal-oxide-semiconductor M7, MOS
Pipe M9, metal-oxide-semiconductor M10, metal-oxide-semiconductor M11.Wherein, the source electrode of metal-oxide-semiconductor M4, metal-oxide-semiconductor M7 and metal-oxide-semiconductor M9 is connected with power end, MOS
The grid of pipe M4 is connected with the drain electrode of metal-oxide-semiconductor M4；Reference current source is connected between the drain electrode of metal-oxide-semiconductor M4 and ground node, and base
The electric current of quasi- current source output is referred to as reference current, drain electrode flow direction ground node of the reference current from the metal-oxide-semiconductor M4；MOS
Pipe M4, metal-oxide-semiconductor M7, the grid of metal-oxide-semiconductor M9 are connected with node VISP, and the drain electrode of metal-oxide-semiconductor M7 is connected with the drain electrode of metal-oxide-semiconductor M10；
The grid of metal-oxide-semiconductor M10 and drain electrode are connected with node VISN, and its source electrode is connected with ground node；The drain electrode of metal-oxide-semiconductor M9 and node
ISP is connected；The drain electrode of metal-oxide-semiconductor M11 is connected with node ISN, and its source electrode is connected with ground node, and its grid is connected with node VISN.
Further, the oscillator module also includes reference voltage generating circuit, the reference voltage generating circuit bag
Include metal-oxide-semiconductor M5, resistance R5 and R6.Wherein, the source electrode of metal-oxide-semiconductor M5 is connected with power end, and its grid is connected with node VISP, its leakage
Pole is connected with node A；One end of resistance R5 is connected with node A, and its other end is connected with node B；One end of resistance R6 and node B
It is connected, its other end is connected with ground node.The voltage of the node A is first reference voltage, and the voltage of node B is described
Second reference voltage.
Further, the reference current source includes metal-oxide-semiconductor M3, resistance R1, R2, R3 and R4, and operational amplifier
OPA.Wherein, resistance R1, R2 and R3 is sequentially connected in series between power end and ground node；The positive input of the operational amplifier
It is connected with the connecting node between resistance R2 and R3, its negative input is connected through resistance R4 with ground node；The metal-oxide-semiconductor M3's
Drain electrode is connected with the drain electrode of metal-oxide-semiconductor M4, and the grid of the metal-oxide-semiconductor M3 is connected with the output end of operational amplifier OPA, the MOS
The source electrode of pipe M3 is connected with the negative input of operational amplifier OPA.
Further, the logic circuit include first comparator, the second comparator, the first NAND gate and second with it is non-
Door, the positive input of first comparator is connected with the first reference voltage, and its negative input is positive defeated with the second comparator
Enter end and node O is connected, the negative input of the second comparator is connected with the second reference voltage；The first of first NAND gate is defeated
Enter end to be connected with the output end of first comparator, its second input is connected with the output end of the second NAND gate；First NAND gate
Output end be connected with the output end of logic circuit；The output end phase of the first input end of the second NAND gate and the first NAND gate
Even, its second input is connected with the output end of the second comparator, wherein, the magnitude of voltage of the first reference voltage is more than the second benchmark
The magnitude of voltage of voltage.
Compared with prior art, the pierce circuit with spread spectrum function in the utility model, its use periodic modulation and
The modulation system that Stochastic Modulation is combined, so as to reduce the static noise that carrier frequency causes because of Stochastic Modulation.
【Brief description of the drawings】
In order to illustrate more clearly of the technical scheme of the utility model embodiment, below will be to being wanted needed for embodiment description
The accompanying drawing for using is briefly described, it should be apparent that, drawings in the following description are only some implementations of the present utility model
Example, for those of ordinary skill in the art, without having to pay creative labor, can also be according to these accompanying drawings
Obtain other accompanying drawings.Wherein：
Circuit diagrams of the Fig. 1 for the pierce circuit in the utility model in one embodiment；
Circuit diagrams of the Fig. 2 for the pierce circuit shown in Fig. 1 in a specific embodiment；
Circuit diagrams of the Fig. 3 for first modulating unit in Fig. 2 in one embodiment；With
Circuit diagrams of the Fig. 4 for second modulating unit in Fig. 2 in one embodiment.
【Specific embodiment】
To enable above-mentioned purpose of the present utility model, feature and advantage more obvious understandable, below in conjunction with the accompanying drawings and tool
Body implementation method is described in further detail to the utility model.
" one embodiment " or " embodiment " referred to herein refers to that may be included in the side of realization of the utility model at least one
Special characteristic, structure or characteristic in formula." in one embodiment " that different places occur in this manual not refers both to
Same embodiment, nor the single or selective embodiment mutually exclusive with other embodiment.Unless stated otherwise,
The word that connection herein, the expression for being connected, connecting are electrically connected with is represented and is directly or indirectly electrical connected.
Refer to shown in Fig. 1, it is pierce circuit in the utility model circuit diagram in one embodiment.
Pierce circuit shown in Fig. 1 includes oscillator module 100 and modulation circuit 200.
The oscillator module 100 includes the first current source 110, the second current source 120, first switch M12, second switch
M13, electric capacity C1 and logic circuit 130.Wherein, the first current source I1 is connected between power end VDDA and node ISP, institute
The electric current referred to as benchmark charging current I1, the benchmark charging current I1 for stating the first current source I1 outputs are flowed to from power end VDDA
Node ISP；First switch M12 is connected between node ISP and node O, second switch M13 be connected to node O and node ISN it
Between；Second current source 120 is connected between node ISN and ground node GNDA, and second current source 120 output electricity
Stream is referred to as reference discharge electric current I2, the reference discharge electric current I2 and flows to ground node GNDA from node ISN；Electric capacity C1 is connected to section
Between point O and ground node GNDA.
The first input end of the logic circuit 130 is connected with the first reference voltage V REFH, its second input and second
Reference voltage V REFL is connected, and its 3rd input is connected with node O, and its output end is connected with the control end of switch M12 and M13.
The logic circuit 130 is based on the voltage of node O and the comparing knot of the first reference voltage V REFH and the second reference voltage V REFL
Really, a switch controlling signal VOSC0 is exported by its output end, switch controlling signal VOSC0 is used to control first switch M12
With second switch M13 alternate conductions.
In the embodiment shown in fig. 1, the logic circuit 130 includes first comparator COMP1, the second comparator
COMP2, the first NAND gate NAND1 and the second NAND gate NAND2, wherein, the positive input of first comparator COMP1 and first
Reference voltage V REFH is connected, and its negative input is connected with the positive input and the node O of the second comparator COMP2,
The negative input of the second comparator COMP2 is connected with the second reference voltage V REFL；First input of the first NAND gate NAND1
End is connected with the output end of first comparator COMP1, and its second input is connected with the output end of the second NAND gate NAND2；The
The output end of one NAND gate NAND1 is connected with the output end VOSC0 of logic circuit 130；First input of the second NAND gate NAND2
End is connected with the output end of the first NAND gate NAND1, and its second input is connected with the output end of the second comparator COMP2, its
In, the magnitude of voltage of the magnitude of voltage more than the second reference voltage V REFL of the first reference voltage V REFH.
In Fig. 1, the voltage (i.e. the voltage of node O) of electric capacity C1 is raised and lowered under the influence of charging and discharging currents, with shape
Into sawtooth oscillation signal VSAW.Sawtooth oscillation signal VSAW is by becoming switch control letter after the treatment of logic circuit 130
Number VOSC0, switch controlling signal VOSC0 controlling switch M12 and M13 alternate conductions or shut-off, so as to change filling for electric capacity C1
Discharge condition.Specifically, when the voltage of node O is less than the second reference voltage V REFL, the output end output of logic circuit 130
The switch controlling signal VOSC0 of the first logic level (such as low level) is simultaneously locked, and now first switch M12 conductings, second open
M13 shut-offs are closed, so that electric capacity C1 enters charged state, the benchmark charging current I1 is by the first switch M12 to institute
Electric capacity C1 chargings are stated, the voltage of the node O can gradually rise；When the voltage of node O is more than the first reference voltage V REFH,
The output end of the logic circuit 130 exports the switch controlling signal VOSC0 of the second logic level (such as high level) and locks,
Now, first switch M12 shut-offs, the 2nd M13 conductings, so that electric capacity C1 enters discharge condition, the reference discharge electric current I2
Discharged to the electric capacity C1 by the second switch M13, the voltage of the node O can be reduced gradually.
In the embodiment shown in fig. 1, the first switch is metal-oxide-semiconductor M12, and the second switch is metal-oxide-semiconductor M13, its
In, the source electrode of the metal-oxide-semiconductor M12 is connected with node ISP, and its drain electrode is connected with node O, its grid and the logic circuit 130
Output end be connected；The drain electrode of the metal-oxide-semiconductor M13 is connected with node O, and its source electrode is connected with node ISN, and its grid is patrolled with described
The output end for collecting circuit 130 is connected.
Please continue to refer to shown in Fig. 1, the modulation circuit 200 includes periodic modulation module 210 and Stochastic Modulation module
220。
The periodic modulation module can be produced based on the sawtooth oscillation signal VSAW or switch controlling signal VOSC0
The 210 and clock signal VOSC of Stochastic Modulation module 220.Based on the clock signal VOSC, the periodic modulation module 210 is defeated
Go out periodically variable first modulated charge current IP1 node ISP, and/or adjusted from the first of the change of node ISN decimation periods
Discharge current IN1 processed, with the periodic distribution of the spread spectrum point of modulating oscillator circuit.It is described based on the clock signal VOSC
Second modulated charge current IP2 of the output change at random of Stochastic Modulation module 220 is extracted to node ISP, and/or from node ISN
Second modulation discharge current IN2 of change at random, frequency is trembled with each spread spectrum point of modulating oscillator circuit.
It should be noted that the switch that the output end that the clock signal VOSC can be the logic circuit 130 is exported
Control signal VOSC0, or the signal that the first input end of the first NAND gate NAND1 of logic circuit 130 is received
VOSC1, can also be the signal VOSC2 of the second input reception of the second NAND gate NAND2 of logic circuit 130.
Refer to shown in Fig. 2, it is pierce circuit shown in Fig. 1 circuit diagram in a specific embodiment.
Pierce circuit shown in Fig. 2 includes oscillator module 300 and modulation circuit 400.
Compared with the logic circuit 130 in Fig. 1, the logic circuit 330 in Fig. 2 also includes phase inverter INV1, INV2, INV3
And INV4.Wherein, the input of phase inverter INV1 is connected with the output end of first comparator COMP1, phase inverter INV1 output ends
Input with phase inverter INV2 is connected, and the output end of phase inverter INV2 is connected with the first input end of the first NAND gate NAND1；
The input of phase inverter INV3 is connected with the output end of the second comparator COMP2, the output end and phase inverter of phase inverter INV3
The input of INV4 is connected, and the output end of phase inverter INV4 is connected with second input of the second NAND gate NAND2.
Compared with the oscillator module 100 in Fig. 1, the first current source and the second electricity in oscillator module 300 in Fig. 2
Stream source includes reference current source 312, metal-oxide-semiconductor M4, M7, M8, M9, M10 and M11.Wherein, the source electrode of metal-oxide-semiconductor M4, M7 and M9 with
Power end VDDA is connected, and the grid of metal-oxide-semiconductor M4 is connected with the drain electrode of metal-oxide-semiconductor M4；Reference current source 312 is connected to metal-oxide-semiconductor M4's
Between drain electrode and ground node GNDA, and the output of reference current source 312 electric current be referred to as reference current I0, the reference current I0 from
The drain electrode flow direction ground node GNDA of the metal-oxide-semiconductor M4；The grid of metal-oxide-semiconductor M4, M7 and M9 is connected with node VISP, metal-oxide-semiconductor M7
Drain electrode be connected with the source electrode of metal-oxide-semiconductor M8, the grid of metal-oxide-semiconductor M8 is connected with signal EN is enabled, the drain electrode of metal-oxide-semiconductor M8 and metal-oxide-semiconductor
The drain electrode of M10 is connected；The grid of metal-oxide-semiconductor M10 and drain electrode are connected with node VISN, and its source electrode is connected with ground node GNDA；MOS
The drain electrode of pipe M9 is connected with node ISP；The drain electrode of metal-oxide-semiconductor M11 is connected with node ISN, and its source electrode is connected with ground node GNDA, its
Grid is connected with node VISN.Metal-oxide-semiconductor M4, M5, M7 and M9 constitute current mirror, and metal-oxide-semiconductor M10 and M11 also constitute current mirror.Its
In, the electric current of metal-oxide-semiconductor M9 mirror image metal-oxide-semiconductors M4, to obtain the benchmark charging current I1；The electricity of metal-oxide-semiconductor M11 mirror image metal-oxide-semiconductors M10
Stream, to obtain the reference discharge electric current I2.
In the embodiment shown in Figure 2, the reference current source 312 includes metal-oxide-semiconductor M1, M2 and M3, resistance R1, R2, R3
And R4, and operational amplifier OPA.Wherein, the source electrode of metal-oxide-semiconductor M1 is connected with power end VDDA, its grid with enable signal EN
It is connected, resistance R1, R2 and R3 are sequentially connected in series between the drain electrode of metal-oxide-semiconductor M1 and ground node GNDA；The grid and resistance of metal-oxide-semiconductor M2
Connecting node between R1 and R2 is connected, and the source electrode of metal-oxide-semiconductor and drain electrode are connected with ground node GNDA；The operational amplifier
Connecting node between the positive input of OPA and resistance R2 and R3 is connected, and its negative input is through resistance R4 and ground node
GNDA is connected；The drain electrode of the metal-oxide-semiconductor M3 is connected with the drain electrode of metal-oxide-semiconductor M4, the grid and operational amplifier of the metal-oxide-semiconductor M3
The output end of OPA is connected, and the source electrode of the metal-oxide-semiconductor M3 is connected with the negative input of operational amplifier OPA.
Compared with the oscillator module 100 in Fig. 1, the device module 300 of swinging shown in Fig. 2 also includes reference voltage generating circuit
340, the reference voltage generating circuit 340 includes metal-oxide-semiconductor M5, M6, resistance R5 and R6.Wherein, the source electrode and power supply of metal-oxide-semiconductor M5
End VDDA is connected, and its grid is connected with node VISP, and its drain electrode is connected with the source electrode of metal-oxide-semiconductor M6；The grid of metal-oxide-semiconductor M6 and enable
Signal EN is connected, and its drain electrode is connected with node A；One end of resistance R5 is connected with node A, and its other end is connected with node B；Resistance
One end of R6 is connected with node B, and its other end is connected with ground node GNDA.The voltage of the node A is first benchmark electricity
The voltage of pressure VREFH, node B is the second reference voltage V REFL.
In the embodiment shown in Figure 2, metal-oxide-semiconductor M1, M4, M5, M6, M7, M8, M9 and M12 is PMOS transistor；Metal-oxide-semiconductor
M2, M3, M10 and M11 are nmos pass transistor.
In the embodiment shown in Figure 2, metal-oxide-semiconductor M1, M6 and M8 is switched to enable, by enable signal EN controls metal-oxide-semiconductor M1,
M6 and M8 on or off, so as to control oscillator module 300 to work or do not work.In other embodiments, M1, M6 and M8 can
To be omitted.
Please continue to refer to shown in Fig. 2, the periodic modulation module 410 includes that cycle rate counter 412 and multiple first is modulated
Unit.
Based on the clock signal VOSC, the cycle rate counter 412 exports the binary system of periodically variable multidigit first
Number.The first of predefined weight can be produced to modulate charging tributary for each first modulating unit and the first tributary of predefined weight is modulated
Electric discharge tributary.The control end CON of each the first modulating unit one-bit digital letters corresponding with the binary number of the multidigit first
Number it is connected, each first modulating unit is based on the one-bit digital signals that are connected to of its control end CON, controls whether it exports the first tune
Node ISP described in charging Zhi Liuzhi processed；Control whether it extracts the first modulation electric discharge tributary from the node ISN.Each first
First modulation charging tributary of modulating unit output accumulates first modulated charge current IP1 corresponding with the first binary number；
The first modulation electric discharge tributary that each first modulating unit is extracted accumulates the first modulation electric discharge corresponding with the first binary number
Electric current IN1.Due to the first binary number cyclically-varying, the first modulated charge current and the first modulation discharge current also can be therewith
Cyclically-varying.Each first modulating unit produces the first of predefined weight with benchmark charging current described in estimated rate mirror image
Modulation charging tributary, produces the first of predefined weight to modulate electric discharge tributary with reference discharge electric current described in estimated rate mirror image.
In the embodiment shown in Figure 2, the cycle rate counter 412 includes some d type flip flops being sequentially connected in series, except last
Outside one d type flip flop, in two adjacent d type flip flops, the output end Q of previous d type flip flop and the latter input of d type flip flop
End D is connected, and the clock end CLK of each d type flip flop is connected with the clock end VOSC of the periodic modulation module 410；Last
The output end Q of individual d type flip flop is connected with the input D of first d type flip flop.So, selected from the cycle rate counter 412
The output end of multiple d type flip flops as the cycle rate counter 412 multidigit output end, it is periodically variable described many to export
The first binary number of position.
Please continue to refer to shown in Fig. 2, the Stochastic Modulation module 420 includes that random counter 422 and multiple second is modulated
Unit.
Based on the clock signal VOSC, the random counter 422 exports the binary number of multidigit second of change at random.
The second of predefined weight can be produced to modulate charging tributary for each second modulating unit and the second tributary modulation of predefined weight is put
Electric tributary.
The control end CON of each the second modulating unit and corresponding one-bit digital signal in the binary number of the multidigit second
It is connected.Each second modulating unit is based on the one-bit digital signal that its control end CON is connected to, and controls whether it exports the second modulation
The node ISP is given in charging tributary；Control whether it extracts the second modulation electric discharge tributary from node ISN.Each second modulation is single
Second modulation charging tributary of unit's output accumulates the second modulated charge current IP2 of the second binary number of correspondence；Each second
The second modulation electric discharge tributary that modulating unit is extracted accumulates the second modulation discharge current IN2 of the second binary number of correspondence.By
In the second binary number change at random, the second modulated charge current and the second modulation discharge current also can change at random therewith.Often
Individual second modulating unit produces the second of predefined weight to modulate charging tributary with benchmark charging current described in estimated rate mirror image,
The second of predefined weight is produced to modulate electric discharge tributary with reference discharge electric current described in estimated rate mirror image.
In the embodiment shown in Figure 2, the random counter 422 includes that feedback unit 4222 is some with what is be sequentially connected in series
In two adjacent d type flip flops of d type flip flop, the output end Q of previous d type flip flop and the latter input D phase of d type flip flop
Even, the clock end CLK of each d type flip flop is connected with the clock end VOSC of the Stochastic Modulation module 420, the first d type flip flop
Input D be connected with a feedback unit 500, the feedback unit 500 export change at random level signal give a D triggering
The input D of device.So, the output end of multiple d type flip flops is selected from the random counter 422 as the random counter
The multidigit output end of device 422, to export the binary number of the multidigit second.
In one embodiment, the transformable minimum value of the first modulated charge current and the first modulation discharge current is more than
The transformable minimum value of the second modulated charge current and the second modulation discharge current.Preferably, the first modulated charge current and
The transformable minimum value of the first modulation discharge current modulates the variable of discharge current more than the second modulated charge current and second
The maximum of change.So, it is possible to use the first modulated charge current of large change and the first modulation discharge current modulation are described
The periodic distribution of the spread spectrum point of pierce circuit, using the second modulated charge current of small change and the second modulation electric discharge electricity
Each of the stream modulation pierce circuit spreads trembling frequently for point.
Refer to shown in Fig. 3, it is first modulating unit in Fig. 2 circuit diagram in one embodiment.
The first modulating unit shown in Fig. 3 includes metal-oxide-semiconductor M14, M15, and the 3rd switchs K1, the 4th switch K2.Wherein, MOS
The source electrode of pipe M14 is connected with power end VDDA, and its drain electrode is connected through switching K1 with node ISP, and its grid is connected with node VISP,
The control end for switching K1 is connected with the control end CON of the first modulating unit.The drain electrode of metal-oxide-semiconductor M15 is through switching K2 and node ISN phases
Even, its grid is connected with node VISN, and its source electrode is connected with ground node, switchs the control end and first modulating unit of K2
Control end CON is connected.
Refer to shown in Fig. 4, it is second modulating unit in Fig. 2 circuit diagram in one embodiment.
The second modulating unit shown in Fig. 4 includes metal-oxide-semiconductor M16, M17, and the 5th switchs K3, the 6th switch K4.Wherein, MOS
The source electrode of pipe M16 is connected with power end VDDA, and its drain electrode is connected through switching K3 with node ISP, and its grid is connected with node VISP,
The control end for switching K3 is connected with the control end CON of the second modulating unit.The drain electrode of metal-oxide-semiconductor M17 is through switching K4 and node ISN phases
Even, its grid is connected with node VISN, and its source electrode is connected with ground node, switchs the control end and second modulating unit of K4
Control end CON is connected.
In sum, the pierce circuit in the utility model, is combined using a kind of periodic modulation and Stochastic Modulation
Modulation system, reduces the static noise that carrier frequency causes because of Stochastic Modulation.Key point of the present utility model is using week
The modulation setting spread spectrum point distribution of phase property, being modulated at each spread spectrum point using randomness carries out trembling frequency.By periodic modulation expansion
The corresponding frequency component of frequency modulation system is set in outside the audible audiorange of human ear.
In the utility model, " connection ", connected, " company ", " connecing " etc. represent the word being electrical connected, and such as nothing is especially said
It is bright, then it represents that direct or indirect electric connection.
It is pointed out that one skilled in the art specific embodiment of the present utility model is done it is any
Change the scope all without departing from claims of the present utility model.Correspondingly, the scope of claim of the present utility model
It is not limited only to previous embodiment.
Claims (12)
1. a kind of pierce circuit with spread spectrum function, it is characterised in that it includes oscillator module and modulation circuit,
The oscillator module includes the first current source, the second current source, first switch, second switch, electric capacity and logic circuit,
Wherein, first current source is connected between power end and node ISP, is filled on the basis of the electric current of the first current source output
Electric current, the benchmark charging current flows to node ISP from power end；First switch is connected between node ISP and node O,
Second switch is connected between node O and node ISN；Second current source is connected between node ISN and ground node, and institute
Discharge current on the basis of the electric current of the second current source output is stated, the reference discharge electric current flows to ground node from node ISN；Electric capacity
It is connected between node O and ground node,
With the first reference voltage and the second reference voltage be compared the voltage of node O by the logic circuit, in the electricity of node O
When pressure is less than or equal to the second reference voltage, exports the switch controlling signal of the first logic level and lock, to control first switch
Conducting, second switch cut-off, the switch of the second logic level is exported when the voltage of node O is equal to or more than the first reference voltage
Control signal is simultaneously locked, and to control second switch to turn on, first switch cut-off, the voltage of the node O forms sawtooth oscillation
Signal,
The modulation circuit includes periodic modulation module and Stochastic Modulation module, and the periodic modulation module exports cyclically-varying
The first modulated charge current to node ISP, and/or from node ISN decimation periods change first modulation discharge current, with
Modulate the periodic distribution of the spread spectrum point of the pierce circuit, the second modulation of the Stochastic Modulation module output change at random
Charging current modulates discharge current to node ISP, and/or from the second of node ISN extraction change at random, to modulate the vibration
Each of device circuit spreads trembling frequently for point.
2. pierce circuit according to claim 1, it is characterised in that
The periodic modulation module includes cycle rate counter and multiple first modulating units,
The clock signal of the cycle rate counter is formed based on the sawtooth oscillation signal or the switch controlling signal, it is described
Cycle rate counter exports the periodically variable binary number of multidigit first, and each first modulating unit can produce predefined weight
First modulation charging tributary and the first modulation electric discharge tributary of predefined weight,
The control end of each the first modulating unit is connected with corresponding one-bit digital signal in the binary number of the multidigit first, often
Individual first modulating unit is based on the one-bit digital signal that its control is terminated to, and controls whether it exports the first modulation charging Zhi Liuzhi
The node ISP；Control whether it extracts the first modulation electric discharge tributary, the output of each first modulating unit from the node ISN
The first modulation charging tributary accumulate the first modulated charge current corresponding with the first binary number；Each first modulating unit
The the first modulation electric discharge tributary extracted accumulates the first modulation discharge current corresponding with the first binary number, enters due to the one or two
Property one number time change processed, the first modulated charge current and the first modulation discharge current also can cyclically-varyings therewith.
3. pierce circuit according to claim 2, it is characterised in that
Each first modulating unit produces the first modulation of predefined weight to fill with benchmark charging current described in estimated rate mirror image
Electric tributary, produces the first of predefined weight to modulate electric discharge tributary with reference discharge electric current described in estimated rate mirror image.
4. pierce circuit according to claim 2, it is characterised in that
First modulating unit includes metal-oxide-semiconductor M14, metal-oxide-semiconductor M15, switchs K1, switchs K2,
Wherein, the source electrode of metal-oxide-semiconductor M14 is connected with power end, and its drain electrode is connected through switching K1 with node ISP, its grid and node
VISP is connected, and the control end for switching K1 is connected with the control end of the first modulating unit；The drain electrode of metal-oxide-semiconductor M15 is through switching K2 with section
Point ISN is connected, and its grid is connected with node VISN, and its source electrode is connected with ground node, and the control end and described first for switching K2 are adjusted
The control end of unit processed is connected.
5. pierce circuit according to claim 1, it is characterised in that
The Stochastic Modulation module includes random counter and multiple second modulating units,
The random counter exports the binary number of multidigit second of each clock cycle change at random,
The clock signal of the random counter is formed based on the sawtooth oscillation signal or the switch controlling signal, each
Second modulating unit can produce the second of predefined weight the second modulation electric discharge tributary for modulating charging tributary and predefined weight, often
The control end of individual second modulating unit is connected with corresponding one-bit digital signal in the binary number of the multidigit second, and each second
Modulating unit is based on the one-bit digital signal that its control is terminated to, and controls whether it exports the second modulation charging tributary to the section
Point ISP；Control whether it extracts the second modulation electric discharge tributary, the second modulation of each second modulating unit output from node ISN
Charging tributary accumulates the second modulated charge current of the second binary number of correspondence, the second tune that each second modulating unit is extracted
System electric discharge tributary accumulates the second modulation discharge current of the second binary number of correspondence, due to the second binary number change at random,
Second modulated charge current and the second modulation discharge current also can change at random therewith.
6. pierce circuit according to claim 5, it is characterised in that
Each second modulating unit produces the second modulation of predefined weight to fill with benchmark charging current described in estimated rate mirror image
Electric tributary, produces the second of predefined weight to modulate electric discharge tributary with reference discharge electric current described in estimated rate mirror image.
7. pierce circuit according to claim 5, it is characterised in that second modulating unit include metal-oxide-semiconductor M16,
Metal-oxide-semiconductor M17, switchs K3, switchs K4,
Wherein, the source electrode of metal-oxide-semiconductor M16 is connected with power end, and its drain electrode is connected through switching K3 with node ISP, its grid and node
VISP is connected, and the control end for switching K3 is connected with the control end of the second modulating unit；The drain electrode of metal-oxide-semiconductor M17 is through switching K4 with section
Point ISN is connected, and its grid is connected with node VISN, and its source electrode is connected with ground node, and the control end and described second for switching K4 are adjusted
The control end of unit processed is connected.
8. pierce circuit according to claim 1, it is characterised in that
The transformable minimum value of the first modulated charge current and the first modulation discharge current more than the second modulated charge current and
The transformable minimum value of the second modulation discharge current, or,
The transformable minimum value of the first modulated charge current and the first modulation discharge current more than the second modulated charge current and
The transformable maximum of the second modulation discharge current.
9. pierce circuit according to claim 1, it is characterised in that first current source and the second current source include
Reference current source, metal-oxide-semiconductor M4, metal-oxide-semiconductor M7, metal-oxide-semiconductor M9, metal-oxide-semiconductor M10, metal-oxide-semiconductor M11,
Wherein, the source electrode of metal-oxide-semiconductor M4, metal-oxide-semiconductor M7 and metal-oxide-semiconductor M9 is connected with power end, grid and the metal-oxide-semiconductor M4 of metal-oxide-semiconductor M4
Drain electrode be connected；Reference current source is connected between the drain electrode of metal-oxide-semiconductor M4 and ground node, and the electric current of reference current source output claims
On the basis of electric current, the reference current is from the drain electrode of metal-oxide-semiconductor M4 flow direction ground node；Metal-oxide-semiconductor M4, metal-oxide-semiconductor M7, metal-oxide-semiconductor M9
Grid be connected with node VISP, the drain electrode of metal-oxide-semiconductor M7 is connected with the drain electrode of metal-oxide-semiconductor M10；The grid of metal-oxide-semiconductor M10 and drain electrode
It is connected with node VISN, its source electrode is connected with ground node；The drain electrode of metal-oxide-semiconductor M9 is connected with node ISP；The drain electrode of metal-oxide-semiconductor M11
It is connected with node ISN, its source electrode is connected with ground node, and its grid is connected with node VISN.
10. pierce circuit according to claim 9, it is characterised in that the oscillator module also includes reference voltage
Producing circuit, the reference voltage generating circuit includes metal-oxide-semiconductor M5, resistance R5 and R6,
Wherein, the source electrode of metal-oxide-semiconductor M5 is connected with power end, and its grid is connected with node VISP, and its drain electrode is connected with node A；Electricity
The one end for hindering R5 is connected with node A, and its other end is connected with node B；One end of resistance R6 is connected with node B, its other end with
Ground node is connected；The voltage of the node A is first reference voltage, and the voltage of node B is second reference voltage.
11. pierce circuits according to claim 9, it is characterised in that
The reference current source includes metal-oxide-semiconductor M3, resistance R1, resistance R2, resistance R3 and resistance R4, and operational amplifier OPA,
Wherein, resistance R1, resistance R2 and resistance R3 are sequentially connected in series between power end and ground node；The operational amplifier is just
It is connected to the connecting node between input and resistance R2 and resistance R3, its negative input is connected through resistance R4 with ground node；
The drain electrode of the metal-oxide-semiconductor M3 is connected with the drain electrode of metal-oxide-semiconductor M4, the grid of the metal-oxide-semiconductor M3 and the output end of operational amplifier OPA
It is connected, the source electrode of the metal-oxide-semiconductor M3 is connected with the negative input of operational amplifier OPA.
12. pierce circuits according to claim 1, it is characterised in that the logic circuit includes first comparator, the
Two comparators, the first NAND gate and the second NAND gate,
The positive input of first comparator is connected with the first reference voltage, and its negative input is positive defeated with the second comparator
Enter end and node O is connected, the negative input of the second comparator is connected with the second reference voltage；The first of first NAND gate is defeated
Enter end to be connected with the output end of first comparator, its second input is connected with the output end of the second NAND gate；First NAND gate
Output end be connected with the output end of logic circuit；The output end phase of the first input end of the second NAND gate and the first NAND gate
Even, its second input is connected with the output end of the second comparator, wherein, the magnitude of voltage of the first reference voltage is more than the second benchmark
The magnitude of voltage of voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621306470.1U CN206195725U (en) | 2016-11-30 | 2016-11-30 | Take oscillator circuit of spread spectrum function |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621306470.1U CN206195725U (en) | 2016-11-30 | 2016-11-30 | Take oscillator circuit of spread spectrum function |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108123687A (en) * | 2016-11-30 | 2018-06-05 | 无锡华润矽科微电子有限公司 | Pierce circuit with spread spectrum function |
| CN114740936A (en) * | 2022-06-10 | 2022-07-12 | 南京浣轩半导体有限公司 | Band-gap reference circuit with offset elimination |
-
2016
- 2016-11-30 CN CN201621306470.1U patent/CN206195725U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108123687A (en) * | 2016-11-30 | 2018-06-05 | 无锡华润矽科微电子有限公司 | Pierce circuit with spread spectrum function |
| CN114740936A (en) * | 2022-06-10 | 2022-07-12 | 南京浣轩半导体有限公司 | Band-gap reference circuit with offset elimination |
| CN114740936B (en) * | 2022-06-10 | 2022-09-16 | 南京浣轩半导体有限公司 | Band-gap reference circuit for eliminating offset |
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Address after: 214135 -6, Linghu Avenue, Wuxi Taihu international science and Technology Park, Wuxi, Jiangsu, China, 180 Patentee after: China Resources micro integrated circuit (Wuxi) Co., Ltd Address before: No. 180-22, Linghu Avenue, Taihu International Science and Technology Park, New District, Wuxi City, Jiangsu Province, 214135 Patentee before: WUXI CHINA RESOURCES SEMICO Co.,Ltd. |
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