CN206181454U - Bleeder circuit and LED control circuit - Google Patents
Bleeder circuit and LED control circuit Download PDFInfo
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- CN206181454U CN206181454U CN201621252478.4U CN201621252478U CN206181454U CN 206181454 U CN206181454 U CN 206181454U CN 201621252478 U CN201621252478 U CN 201621252478U CN 206181454 U CN206181454 U CN 206181454U
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Abstract
The utility model discloses a bleeder circuit and LED control circuit, wherein the bleeder circuit includes: the module of releasing, NULL obtains input voltage through triac dimmer and rectifier bridge and supplies power to the load through drive circuit, the both ends of the module of releasing are connected with input voltage's high cold end respectively, the discharge control circuit, with the control end of the module of releasing is connected, directness or indirectly detecting input voltage zero crossing, at input voltage zero crossing time delay second after the time, control the module of releasing produces the bleeder current, drive circuit's arrival current reach the predetermined value constantly then the controlled discharge electric current for zero, triac dimmer switch on constantly with it is the very first time that drive circuit's arrival current reaches the time of predetermined value between the moment, wherein, work as very first time when being greater than reference time, then prolong the second time, when the very first time is less than reference time, then shorten the second time for very first time convergence is in reference time.
Description
Technical field
This utility model is related to electric and electronic technical field, and in particular to a kind of leadage circuit and LED control circuit.
Background technology
LED due to its environmental protection more more energy efficient than traditional fluorescent lamp and electric filament lamp, so LED is slowly replacing existing
Fluorescent lamp and electric filament lamp.In the electric filament lamp with controllable silicon dimmer, similarly wish to be replaced using LED, thus
LED needs compatible silicon controlled dimmer.But, by LED come replace electric filament lamp application in, due in controlled silicon conducting,
Its output end voltage has larger voltage change ratio (dv/dt), causes to produce larger surge current in input.This surge
Current oscillation amplitude is big, and the persistent period is short, easily causes silicon controlled to turn off by mistake, affects the steady operation of LED drive circuit, makes
LED produces flicker；In addition, the input current of silicon-controlled device need to be more than its maintenance electric current, when input current is less than maintenance electricity
During stream, easily cause silicon controlled to turn off, also result in the flicker of LED.In order to solve above-mentioned technical problem, in prior art
Using following scheme, but still suffer from certain technological deficiency.
Circuit theory diagrams as shown in Figure 1, illustrate the leadage circuit of prior art, i.e. current source I10 and adjustment pipe M00
Leadage circuit is composed in series, current source I10 can be replaced with resistance.When controllable silicon dimmer is turned on, linear LED drive circuit
When electric current is difficult to the maintenance electric current for reaching controllable silicon dimmer, the adjustment pipe M00 conductings of leadage circuit, leadage circuit is produced and released
Electric current iblr so that input current can reach maintenance electric current.As shown in Fig. 2 illustrating input voltage vin and input current
The waveform of iin, dash area is the electric current that leadage circuit is produced, and this part leakage current can bring extra power consumption.And can
Control silicon dimmer conduction angle is bigger, and the time t1 that leadage circuit produces leakage current iblr is longer, and bigger, conversion efficiency is lost
It is lower.
Utility model content
In view of this, the purpose of this utility model is to provide a kind of small power consumption, the leadage circuit of efficiency high and LED control
Circuit, to the technical problem for solving prior art presence.
Technical solution of the present utility model is to provide a kind of leadage circuit of following structure, including：
Release module, exchange input Jing controllable silicon dimmers and rectifier bridge obtain input voltage Jing drive circuits and load is supplied
Electricity, the two ends of the module of releasing are connected respectively with the high cold end of input voltage；
Release control circuit, be connected with the control end of the module of releasing；Input voltage zero crossing is directly or indirectly detected,
After input voltage zero crossing the second time of time delay, the control module generation leakage current of releasing, the drive circuit it is defeated
Enter electric current to reach the predetermined value moment then to control leakage current be zero；Controllable silicon dimmer turn-on instant is defeated with the drive circuit
It is the very first time to enter the time that electric current reached between the predetermined value moment；
Wherein, when the described very first time reference time is more than, then extended for the second time；When the very first time is less than reference
During the time, then shortened for the second time so that the very first time levels off to the reference time.
Preferably, described control circuit of releasing is including input voltage detection circuit, drive circuit input electric cur- rent measure
Circuit and logic circuit, described logic circuit is connected with the control end of module of releasing, and described input voltage detection circuit is adopted
Sample input voltage, when input voltage sampled signal reaches threshold voltage, then after the time of time delay second, the control of Jing logic circuits
The module of releasing produces leakage current；Described drive circuit input electric cur- rent measure electric circuit inspection drive circuit input current,
When sample rate current reaches the threshold current for characterizing predetermined value, then it is zero that Jing logic circuits control leakage current；By described first
Time is compared with the reference time, and according to comparative result second time is correspondingly adjusted.
Preferably, described control circuit of releasing also includes time delay module and time comparison module, described time delay mould
Block outfan respectively with input voltage detection circuit, logic circuit and time comparison module are connected, and described time delay module exists
Enter the time of line delay second when input voltage sampled signal reaches threshold voltage, after time delay terminates, by logic circuit control
Leakage current is produced, the comparison of the very first time and the reference time is carried out in the time comparison module, and knot will be compared
Fruit feeds back to the time delay module to adjust second time.
Preferably, described logic circuit includes the first trigger and the second trigger, described time delay module output
The status signal whether time delay terminates is characterized, the set end of first trigger receives the shape whether sign time delay terminates
State signal, the outfan of input voltage detection circuit and the outfan of time delay module are respectively connected to NAND gate, the NAND gate
Outfan is connected with the replacement end of first trigger；The outfan of first trigger is triggered after negating with described second
The set end connection of device, the outfan of drive circuit input electric cur- rent measure circuit negate after replacement end with second trigger
The outfan of connection, the outfan of second trigger and the drive circuit input electric cur- rent measure circuit connects respectively and door
Two inputs, the outfan of the outfan with door and the first trigger is connected respectively two inputs of OR gate, institute
State OR gate output and characterize the signal for whether enabling to the module of releasing, it is described to export for characterizing when first with door outfan
Between timing signal.
Preferably, described control circuit of releasing is detected including drive circuit input electric cur- rent measure circuit, leakage current
Circuit and logic circuit, described logic circuit is connected with the control end of module of releasing, described drive circuit input current inspection
Slowdown monitoring circuit sampling drive circuit input current, and be compared with threshold current；Described vent discharge current detection circuit is in input
During voltage zero-cross is detected, module of releasing described in the logic circuit control produces leakage current, the leakage current of sampling, and
Threshold value is compared with releasing；When the drive circuit input current is less than the threshold current, start timing, let out until described
Discharge stream is reached when releasing threshold value, and timing terminates, and the timing time is used as the 3rd time.
When the drive circuit input current is less than the threshold current, judge that input voltage reaches Jing after the 3rd time
To zero crossing；And can timing or variable interval the 3rd time of renewal.
Preferably, when judging that input voltage reaches zero crossing, after the time of time delay second, the control of Jing logic circuits is described
Module of releasing produces leakage current；Described drive circuit input electric cur- rent measure electric circuit inspection drive circuit input current, when adopting
When sample electric current reaches the threshold current for characterizing predetermined value, then it is zero that Jing logic circuits control leakage current；By the very first time
It is compared with the reference time, second time is correspondingly adjusted according to comparative result.
Preferably, described control circuit of releasing also includes time delay module, time comparison module and zero passage judge module,
Described time delay module outfan respectively with zero passage judge module, logic circuit and time comparison module are connected, the zero passage
Judge module is connected respectively with the outfan of vent discharge current detection circuit and the outfan of drive circuit input electric cur- rent measure circuit；
Timing is carried out to the 3rd time by the zero passage judge module, and judge the zero crossing moment of input voltage, described time delay mould
Block receives the signal at the sign zero crossing moment of the zero passage judge module output, and the time of time delay second, after time delay terminates, leads to
Cross logic circuit control and produce leakage current, the ratio of the very first time and the reference time is carried out in the time comparison module
Compared with, and comparative result is fed back to into the time delay module to adjust second time.
Preferably, described logic circuit includes the 3rd trigger and the 4th trigger, described time delay module output
The status signal whether time delay terminates is characterized, the set end of the 3rd trigger receives the shape whether sign time delay terminates
State signal, the outfan of zero passage judge module and the outfan of time delay module are respectively connected to NAND gate, the output of the NAND gate
End is connected with the replacement end of the 3rd trigger；The outfan of the 3rd trigger negate after with the 4th trigger
Set end connects, and the outfan of drive circuit input electric cur- rent measure circuit connects after negating with the replacement end of the 4th trigger
Connect, the outfan of the 4th trigger and the outfan of the drive circuit input electric cur- rent measure circuit connect respectively first with
Two inputs of door, the outfan of drive circuit input electric cur- rent measure circuit and characterize the letter whether zero passage judge module enables
Number it is respectively connected to two inputs of second and door；Described first touches with the outfan of door, second with the outfan and the 3rd of door
The outfan for sending out device connects respectively three inputs of OR gate, and the OR gate output characterizes the signal for whether enabling and releases to described
Module, described first exports the timing signal for characterizing the very first time with the outfan of door.
Another technical solution of the present utility model is to provide a kind of LED control circuit of following structure, including：With
Upper any one leadage circuit and LED drive circuit, described LED drive circuit is linear drive circuit or on-off circuit.
Using circuit structure of the present utility model and method, compared with prior art, with advantages below：This utility model
The LED control circuit of controllable silicon light modulation is applied to, directly or indirectly detection input voltage zero crossing, at input voltage zero crossing
After the time of time delay second, to produce leakage current, controllable silicon dimmer turn-on instant is input into drive circuit for module of releasing work
Electric current reaches time of the predetermined value (the maintenance electric current of controllable silicon dimmer) between the moment for the very first time.In time first
Interior, leadage circuit produces loss, when the very first time predetermined value is more than, extends for the second time；When the very first time is less than predetermined
During value, shortened for the second time so that very first time time is close or equal to predetermined value.Using this utility model, being capable of self adaptation
Ground adjusts the second time as time delay according to the size of the very first time and predetermined value, reduces power consumption of releasing, and carries
System effectiveness is risen.
Description of the drawings
Fig. 1 is the structural representation of the controllable silicon LED control circuit of the application leadage circuit of prior art；
Fig. 2 is the working waveform figure of prior art Fig. 1；
Fig. 3 is the working waveform figure of this utility model leadage circuit；
Fig. 4 is FB(flow block) of the present utility model；
Fig. 5 is the circuit structure diagram of this utility model leadage circuit embodiment one；
Fig. 6 is the FB(flow block) of the logic circuit of this utility model leadage circuit embodiment one；
Fig. 7 is the structural representation of logic circuit in this utility model leadage circuit embodiment one；
Fig. 8 is the structural representation of time comparison module in this utility model leadage circuit embodiment one；
Fig. 9 is the structural representation of time delay module in this utility model leadage circuit embodiment one；
Figure 10 is the working waveform figure of this utility model leadage circuit embodiment one；
Figure 11 is the circuit structure diagram of this utility model leadage circuit embodiment two；
Figure 12 is the FB(flow block) of the logic circuit of this utility model leadage circuit embodiment two；
Figure 13 is the structural representation of logic circuit in this utility model leadage circuit embodiment two；
Figure 14 is the FB(flow block) of zero passage judge module in this utility model leadage circuit embodiment two；
Figure 15 is the working waveform figure of this utility model leadage circuit embodiment two.
Specific embodiment
Preferred embodiment of the present utility model is described in detail below in conjunction with accompanying drawing, but this utility model is not merely
It is limited to these embodiments.This utility model covers any replacement made in spirit and scope of the present utility model, modification, equivalent
Method and scheme.
In order that the public has to this utility model thoroughly understand, in following this utility model preferred embodiment specifically
Clear concrete details, and for a person skilled in the art description without these details can also completely understand that this practicality is new
Type.
Referring to the drawings this utility model more particularly described below by way of example in the following passage.It should be noted that, accompanying drawing
In the form of more simplifying and using non-accurately ratio, only conveniently, lucidly to aid in illustrating this utility model
The purpose of embodiment.
With reference to shown in Fig. 3, the work wave of this utility model leadage circuit is illustrated.Illustrate in figure input voltage vin,
The waveform of input current iin and leakage current iblr.By directly or indirectly detection input voltage vin zero crossing, in input electricity
When pressure reaches zero crossing then after the second time of time delay t2, control leadage circuit produces leakage current iblr, and controllable silicon dimmer is led
Logical moment and drive circuit input current iin2 reach predetermined value (the generally maintenance electric current of controllable silicon dimmer) between the moment
Time be very first time t1.In very first time t1, leadage circuit produces loss, when t1 is more than predetermined value T, increase second
Time t2；When t1 is less than predetermined value T, reduce the second time t2 so that very first time time t1 is close or equal to predetermined value T.
In figure ,+VF and-VF is equal to the conduction threshold of diode.
With reference to shown in Fig. 4, the FB(flow block) of this utility model leadage circuit is illustrated.First whether judge input voltage vin
Zero passage, is positioned proximate to be compared with sampled voltage in zero threshold voltage, it is also possible to obtain input electricity indirectly by other amounts
The moment of pressure Vin zero passages.Described input voltage vin is the input voltage vin obtained by exchange input Jing controllable silicon dimmers.
After input voltage zero crossing the second time of time delay t2, module of releasing described in control is enabled to produce leakage current iblr.When defeated
After entering voltage Vin zero passages, start timing, the input current iin2 of the drive circuit reaches predetermined value (typically using controllable silicon
The maintenance size of current of dimmer) moment, then leadage circuit do not enable, leakage current is zero, and now timing terminates；Above-mentioned timing
Time is the time that the input current of controllable silicon dimmer turn-on instant and the drive circuit was reached between the predetermined value moment,
For very first time t1.When described very first time t1 is more than reference time T, then extend the second time t2；As very first time t1
During less than reference time T, then shorten the second time t2 so that the very first time levels off to reference time T.The method is shortened releases
Time, reduce power consumption of releasing, lift system efficiency.
With reference to shown in Fig. 5, the circuit structure of this utility model leadage circuit embodiment one is illustrated, be applied to thyristor regulating
In the LED control circuit of light.LED control circuit includes leadage circuit and LED drive circuit, and described leadage circuit includes releasing
Module and control circuit of releasing, described leadage circuit be used to solve being made by input current is too small under controllable silicon dimmer
Into flicker problem, and overcome the technological deficiency existing for prior art.Its input power is exchange input, the exchange input
The input voltage vrec of direct current is exported Jing after controllable silicon dimmer U02 and rectifier bridge U01, i.e., as the input voltage of LED load.
Exchange input is connected to rectifier bridge U01, the positive output end of rectifier bridge and the anode of diode D00 through controllable silicon dimmer U02
Connection, LED drive circuit anode is connected with the negative electrode of the diode D00.Generally LED drive circuit can be presented certain capacitive,
Therefore, diode D00 is added between vrec and LED drive circuit；When the absolute value of exchange input is reduced, LED drives electricity
It route in capacitive, its voltage can reduce relatively slow, adds the sampling electricity of diode D00 and input voltage vrec detection circuits
Vrec voltage follows can be exchanged the absolute value of input for resistance, so as to ensure the accuracy to input voltage sampling.
Described leadage circuit includes releasing and module and releases control circuit, described module of releasing include adjustment pipe and with
The current source or resistance of the adjustment pipe series connection.It is of the present utility model to be mainly improved by release control circuit and corresponding control
Method processed.It is described release control circuit including input voltage vrec detection circuits, drive circuit input electric cur- rent measure circuit and
Logic circuit U12, described logic circuit U12 is connected with the control end of module U03 of releasing, described input voltage vrec detections
Circuit sampling input voltage, (is compared when input voltage sampled signal reaches threshold voltage VREF1 in comparator U10
Compared with), then after the second time of time delay t2, module U03 of releasing described in Jing logic circuits U12 controls produces leakage current iblr；Institute
The drive circuit input electric cur- rent measure electric circuit inspection drive circuit input current iin2 for stating, when sample rate current reaches sign predetermined value
Threshold current VREF4 when (be compared in comparator U40), then it is zero that Jing logic circuits U12 controls leakage current iblr；
The very first time t1 is compared with the reference time T, the second time t2 is correspondingly adjusted according to comparative result.
When described drive circuit is linear drive circuit, the electric current of the adjustment pipe M30 of the linear drive circuit of sample streams, you can use
In the input current in2 for characterizing the drive circuit.
Described control circuit of releasing also includes time delay module U13 and time comparison module U14, the time delay module U13
For detecting that input voltage crossover point signal ZVD that circuit is produced enters line delay to input voltage vrec, and after time delay terminates,
Logic circuit U12 is given by signal transmission, so that module U03 enable of releasing.When the time comparison module U14 is used for first
Between the t1 and reference time T be compared, to realize feedback regulation to the second time t2.Described time delay module U13 point
Do not detect that the outfan of circuit, logic circuit U12 and time comparison module U13 are connected with input voltage vrec, described time delay
Module U13 is entering the second time of line delay t2 when input voltage sampled signal reaches threshold voltage VREF1, after time delay terminates,
Leakage current iblr is produced by logic circuit U12 controls, very first time t1 and institute are carried out in the time comparison module U14
The comparison of reference time T is stated, and comparative result is fed back to into the time delay module to adjust the second time t2.
With reference to shown in Fig. 6, the FB(flow block) of the logic circuit U12 of this utility model leadage circuit embodiment one is illustrated.This
Accompanying drawing combines Fig. 5, and the specific implementation step for obtaining embodiment one is：The initial value of t2 is 0.Alternating current power supply Jing controllable silicon dimmer
After U02, rectifier bridge U01, the voltage vrec after rectification is obtained.Resistance R10, R11 carry out partial pressure to vrec, when on resistance R11
When voltage is less than reference voltage VREF1, the output ZVD upsets of comparator U10, as the starting point of input voltage vrec zero crossings
Signal.With the negative input end that R11 is connected to comparator U10, reference voltage is connected to as a example by the positive input terminal of comparator U10.When
During input voltage zero passage, voltage is less than VREF1 on resistance R11, then the output ZVD of comparator U10 is changed into high level from low level.
Jing after delay circuit U13 time delay t2, delay circuit output signal ZVDLY overturns the high level signal of ZVD, and is input to logic electricity
Leadage circuit enabler flags position EN is put 1 by road U12, logic circuit U12, and leadage circuit is enabled, and busbar voltage vrec is pulled down to
Close 0V.When the output ZVD of comparator U10 is low, i.e. at the t01 moment in Fig. 3, logic circuit U12 starts timing, timing signal
BLT is uprised from low.Drive circuit input electric cur- rent measure electric circuit inspection iin2 electric current, when voltage RS is low on current sampling resistor R40
When reference voltage VREF4, i.e., between t01-t02, leadage circuit U03 continues to enable.When voltage RS is higher than reference voltage VREF4
When, the output signal ZC upset of comparator U40, logic circuit U12 timing terminates timing signal BLT by high step-down, while releasing
Circuit U 03 is not enabled, i.e., leadage circuit does not produce leakage current.T01-t02 is the time t1 that leadage circuit produces power consumption, i.e.,
BLT is output as height between t01-t02.Timing signal BLT is connected to the input of time comparison circuitry U14, when t1 is more than T
When, time comparison circuitry U14 output time delay direction flag BLDIR are high level；Conversely, time delay direction flag BLDIR is
Low level.When delay circuit U13 adjusts the time delay after input voltage crossover point signal ZVD according to time delay direction flag BLDIR
Between t2, t1 is adjusted to T or close T.Wherein time delay t2 minima is 0, is half power frequency period or more to the maximum.
With reference to shown in Fig. 7, the circuit structure of logic circuit in this utility model leadage circuit embodiment one is illustrated.It is described
Logic circuit include the first trigger U12_1 and the second trigger U12_5, whether described time delay module output characterizes time delay
The status signal ZVDLY of end, set end S of first trigger receives the status signal whether sign time delay terminates
ZVDLY, the outfan of input voltage detection circuit and the outfan of time delay module U13 are respectively connected to NAND gate U12_2, it is described with
The outfan of not gate U12_2 is connected with the replacement end R of the first trigger U12_1；The output of the first trigger U12_1
End be connected after negating with the set end of second trigger, after the outfan of drive circuit input electric cur- rent measure circuit is negated and
The replacement end R connections of the second trigger U12_5, the outfan and the drive circuit of the second trigger U12_5 is defeated
The outfan for entering current detection circuit connects respectively two inputs with door U12_4, the outfan with door U12_4 and the
The outfan of one trigger U12_1 connects respectively two inputs of OR gate U12_3, and whether the OR gate U12_3 outputs sign
The signal EN of enable is to module U03 of releasing, the timing exported with door U12_4 outfan for characterizing the very first time
Signal BLT.Can be that it is replaced although giving the structure of a specific logic circuit above, and be not limited to
Said structure.
With reference to shown in Fig. 8, the circuit structure of time comparison module in this utility model leadage circuit embodiment one is illustrated.
Time signal B LT controlling switches S14_1, S14_2 of effectively releasing that logic circuit U12 is produced, the S14_1 conductings when BLT is high,
Current source I14 charges to electric capacity C14, and when electric capacity C14 voltages are more than reference voltage V REF14 high level signal is exported, and time delay adds
It is height to subtract marking signal BLDIR, while enumerator U14_6 is reset, illustrates that delay time needs to lengthen；When BLT is low
S14_2 conducting C14 electric discharges.
T=C14*Vref14/I14；
When the BLT times T is shorter than, the persistent period, enumerator U14_6 added counting to produce carry, and U14_5 resets more than T5,
BLDIR is low, illustrates that delay time needs to shorten.
T5=TCLK14*2N1
Wherein N1 is the digit of enumerator U14_6.
With reference to shown in Fig. 9, the circuit structure of time delay module in this utility model leadage circuit embodiment one is illustrated.Time delay
Plus-minus flag bit enables signal as the plus-minus counting of enumerator U13_1, U13_2；Clocks of the CLK13 as enumerator U13_2
Signal, its cycle is the minimum step of time delay；When input voltage zero passage, ZVD signals are high level, and R/S trigger U13-5 are defeated
Go out high level, until when drive circuit input current flag bit ZC sets to 0, R/S triggers U13-5 outputs reset, produce ZVDC letters
Number, as the clock signal of enumerator U13-1.When time delay plus-minus flag signal BLDDIR is 1, enumerator U13_1, U13_
2 add counting；When time delay plus-minus flag signal BLDDIR is 0, enumerator U13_1 subtracts counting, enumerator U13_2 and adds counting.
When enumerator U13_1, U13_2 count value is identical, biconditional gate U13_3 output high level exports high level with door U13_4,
ZVDLY export high level, as the zero cross signal after ZVD time delays, after Jing logic circuits U12 produce leadage circuit enable letter
Number.
With reference to shown in Figure 10, the work wave of this utility model leadage circuit embodiment one is illustrated.Illustrate input electricity
The corresponding concrete waveform of pressure Vin, input current iin, leakage current iblr, enable signal EN and sampled signal RS.By scheming
In as can be seen that the leakage current iblr working times are longer in initial power-on, Jing after delay process, the iblr times are increasingly
It is short, until maintain minimum releasing within time T, it is ensured that leadage circuit has relatively low power consumption.
With reference to shown in Figure 11, the circuit structure of this utility model leadage circuit embodiment two is illustrated.This scheme can nothing
Need input voltage vrec to detect circuit, can also reach the effect of above scheme, to simplify peripheral element, i.e., by other means
The zero crossing of detection input voltage vrec, but need to increase leakage current iblr detection circuits.
In the present embodiment, described control circuit of releasing is examined including drive circuit input electric cur- rent measure circuit, leakage current
Slowdown monitoring circuit and logic circuit U11, described logic circuit U11 is connected with the control end of module U03 of releasing, described drive circuit
Input electric cur- rent measure circuit sampling drive circuit input current, and be compared with threshold current, described leakage current detection
When input voltage zero passage detection is enabled, module of releasing described in the logic circuit control produces leakage current to circuit, and samples
The leakage current, is sampled by resistance R50, and is compared with threshold value of releasing (being characterized with VREF4)；The drive circuit
Input current less than the threshold current VREF4 (reference signal characterize be close to zero Low threshold) when, that is, drive electricity
Road input current starts timing close to zero or zero passage, when the leakage current iblr reaches releases threshold value, timing knot
Beam, the timing time reaches after the threshold current Jing again as the 3rd time T3 by the drive circuit input current
The moment of three time T3 judges that input voltage reaches zero crossing.
When judging that input voltage reaches zero crossing, after the second time of time delay t2, release described in Jing logic circuits U11 controls
Module produces leakage current iblr；Described drive circuit input electric cur- rent measure electric circuit inspection drive circuit input current, when adopting
When sample electric current reaches the threshold current for characterizing predetermined value, then it is zero that Jing logic circuits U11 controls leakage current iblr；By described
One time t1 is compared with the reference time T, and according to comparative result the second time t2 is correspondingly adjusted.
Described control circuit of releasing also includes time delay module U13, time comparison module U14 and zero passage judge module U15,
Described time delay module U13 outfan, logic circuit U11 and time comparison module U14 companies respectively with zero passage judge module U15
Connect, the zero passage judge module U15 is electric with the outfan and drive circuit input electric cur- rent measure of vent discharge current detection circuit respectively
The outfan connection on road；Timing is carried out to the 3rd time T3 by the zero passage judge module, and judges the zero crossing of input voltage
Moment, described time delay module receives the signal at the sign zero crossing moment of the zero passage judge module output, and time delay second
Time t2, after time delay terminates, produces leakage current iblr, in the time comparison module U14 by logic circuit U11 controls
The comparison of very first time t1 and the reference time T is carried out, and it is described to adjust that comparative result is fed back to into the time delay module
Second time t2.
With reference to shown in Figure 12, the FB(flow block) of the logic circuit U11 of this utility model leadage circuit embodiment two is illustrated.This
Accompanying drawing combines Figure 11, and the specific implementation step for obtaining embodiment two is：
The initial value of the second time t2 is 0.Alternating current power supply obtains rectification Jing after controllable silicon dimmer U02, rectifier bridge U01
Voltage vrec afterwards.Input voltage zero passage detection enables signal CTL is used for the detection of the time of input voltage zero-crossing timing the 3rd, and
And in order to simultaneously the accuracy for ensureing for the 3rd time reduces power consumption of releasing, CTL can be the square-wave signal far below work frequency.
During first upper electricity, it is high level that input voltage zero passage detection enables signal CTL, as long as now drive circuit input current sampling electricity
Resistance R40 voltages RS is less than reference voltage Vref 4, and comparator U40 outfans are high level, and leadage circuit U03 is in enable work
State.When input voltage is higher, LED current is big, and drive circuit sampling resistor R40 voltages are higher than VREF4, and comparator U40 is exported
Low level, input voltage zero cross signal ZVD is now low level；When input voltage is by high reduction, drive circuit input current is adopted
Sample resistance R40 voltages are reduced, and when drive circuit input current sampling resistor R40 voltages RS is less than VREF4, comparator U40 is defeated
Go out upset, leadage circuit U03 is enabled, and input voltage zero-crossing detection circuit U15 starts timing；Leakage current iblr sampling resistors
R50 voltages are higher than reference voltage V REF5, and comparator U50 exports low level；Input voltage continues to reduce, and as close 0V, releases
Electric current iblr is decreased to close 0, and leakage current iblr sampling resistor R50 voltages are less than reference voltage V REF5, and comparator U50 is defeated
Go out high level, input voltage crossover point signal ZVD is changed into high level, while input voltage zero-crossing detection circuit U15 counts knot
Beam, timing time is T3, as between drive circuit input current iin2 trailing edges zero crossing and input voltage zero crossing when
Between T3.
When it is low level that input voltage zero passage detection enables signal CTL, each power frequency period afterwards works as drive circuit
Input current sampling resistor R40 voltages higher than reference voltage VREF4 by when becoming less than reference voltage VREF4 (on comparator U40
Rise edge) time delay T3 generation input voltage crossover point signals ZVD.The high level signal of ZVD Jing after time delay process U13 time delay t2, Jing
Logic circuit U11 is crossed, leadage circuit working mark position EN is put 1 by logic circuit U11, and leadage circuit is enabled, busbar voltage vrec
It is pulled down to close 0V.When the output ZCBLD of leakage current detection comparator U50 is low, i.e. the t01 moment in Figure 15, the time
Comparison circuit U14 starts working.Drive circuit input electric cur- rent measure electric circuit inspection iin2 electric current, when on current sampling resistor R40
When voltage RS is less than reference voltage VREF4, i.e., between t01-t02, leadage circuit U03 continues to enable.When voltage RS is higher than reference
During voltage VREF4, the output signal ZC upset of comparator U40, time comparison circuitry U14 end-of-jobs, while leadage circuit U03
Do not enable, i.e., leadage circuit does not produce leakage current.From t01-t02 be leadage circuit produce power consumption time t1, when t1 it is big
When T, time comparison circuitry output time delay direction flag BLDIR is high level；Conversely, time delay direction flag BLDIR is
Low level.When delay circuit U13 adjusts the time delay after input voltage crossover point signal ZVD according to time delay direction flag BLDIR
Between t2, t1 is adjusted to T or close T.Wherein time delay t2 minima is 0, is half power frequency period or more to the maximum.With reference to Figure 13
It is shown, illustrate the circuit structure of logic circuit in this utility model leadage circuit embodiment two.When the inspection of input voltage zero crossing
When survey enable signal CTL is high level, as long as drive circuit input current iin2 is high level less than setting value, i.e. ZC, with
Door U11_6 is output as high level, and three input OR gate U11_3 output high level, leadage circuit is enabled, input voltage zero-crossing examination
Circuit U 15 detects input voltage zero crossing, 0-t07 in such as Figure 15, and holding time T3.When input voltage zero-crossing examination is enabled
When signal CTL is low level, with door U11_6 low level is output as.When drive circuit input current iin2 detects circuit ZC by low
When level upset is high level (t03), delay time T3, ZVD signals are changed into high level from low level, even if now ZC is high electricity
It is flat, but R/S trigger U11_1 (the t01 moment resets), U11_5 (the t02 moment resets) output low level, it is output as with door U11_4
Low level, leadage circuit is not enabled.When delay circuit U13 output signals ZVDLY put 1, R/S trigger U11_1 are output as
High level, it is high level that leadage circuit enables signal EN, and leadage circuit is enabled, and input voltage vrec is 0, until controllable silicon light modulation
Device is turned on, and ZVD is low, R/S triggers U11_1 output low levels, and U11_5 exports high level, if now ZC is height, with door
U11_4 exports high level, and leadage circuit enables signal EN and continues as high level, to maintain input current to ensure that silicon controlled is steady
Fixed conducting；Until when ZC is low, U11_4, U11_5 output resets, leadage circuit enables signal EN for low, leadage circuit stopping work
Make.The time signal B LT (t01~t02) that leadage circuit produces power consumption is with door U11_4 outputs.
With reference to shown in Figure 14, zero passage judge module U15 work in this utility model leadage circuit embodiment two is illustrated
FB(flow block).Drive circuit input current iin2 zero crossings and leakage current are detected and preserved by zero passage judge module U15
The iblr zero crossing times.In the case where zero passage judge module U15 is enabled, judge drive circuit input current whether less than threshold value
Electric current, when it is less than threshold current, then module of releasing is enabled and produces leakage current.When leakage current is less than respective threshold,
The moment is then preserved, the 3rd time T3 is updated.The 3rd time T3 be from ZC by high step-down to ZCBLD by high step-down when
Between.
With reference to shown in Figure 15, the work wave of this utility model leadage circuit embodiment two is illustrated.Illustrate input electricity
The corresponding concrete waveform of pressure Vin, input current iin, leakage current iblr, enable signal EN, CTL and sampled signal RS.
As can be seen from Figure, similar to embodiment one, in initial power-on, the leakage current iblr working times are longer, Jing delay process
Afterwards, the iblr times are shorter and shorter, until maintain minimum releasing within time T, it is ensured that leadage circuit has relatively low power consumption.
In addition, although above embodiment is separately illustrated and is illustrated, but it is related to the common technology in part, in this area
Those of ordinary skill apparently, can between the embodiments be replaced and integrate, and be related to one of embodiment and be not expressly recited
Content, then refer to another embodiment on the books.
Embodiments described above, does not constitute the restriction to the technical scheme protection domain.It is any in above-mentioned enforcement
Modification, equivalent and improvement made within the spirit and principle of mode etc., should be included in the protection model of the technical scheme
Within enclosing.
Claims (10)
1. a kind of leadage circuit, it is characterised in that：Including：
Release module, exchange input Jing controllable silicon dimmers and rectifier bridge obtain input voltage Jing drive circuits to load supplying,
The two ends of the module of releasing are connected respectively with the high cold end of input voltage；
Release control circuit, be connected with the control end of the module of releasing；Input voltage zero crossing is directly or indirectly detected, defeated
After entering the time of voltage over zero time delay second, module of releasing described in control produces leakage current, the input of the drive circuit
Electric current reaches the predetermined value moment, and then to control leakage current be zero；The input of controllable silicon dimmer turn-on instant and the drive circuit
It is the very first time that electric current reaches time between the predetermined value moment；
Wherein, when the described very first time reference time is more than, then extended for the second time；The reference time is less than when the very first time
When, then shortened for the second time so that the very first time levels off to the reference time.
2. leadage circuit according to claim 1, it is characterised in that：Described control circuit of releasing is examined including input voltage
Slowdown monitoring circuit, drive circuit input electric cur- rent measure circuit and logic circuit, described logic circuit connects with the control end of module of releasing
Connect, described input voltage detection circuit sampled input voltage when input voltage sampled signal reaches threshold voltage, is then prolonging
When the second time after, the Jing logic circuits control module generation leakage current of releasing；Described drive circuit input current inspection
Slowdown monitoring circuit detects drive circuit input current, when sample rate current reaches the threshold current for characterizing predetermined value, then Jing logic circuits
It is zero to control leakage current；The very first time is compared with the reference time, is correspondingly adjusted according to comparative result
Second time.
3. leadage circuit according to claim 2, it is characterised in that：Described control circuit of releasing also includes time delay module
With time comparison module, described time delay module outfan respectively with input voltage detection circuit, logic circuit and time ratio
Compared with module connection, described time delay module entering the time of line delay second when input voltage sampled signal reaches threshold voltage,
After time delay terminates, leakage current is produced by logic circuit control, the very first time and institute are carried out in the time comparison module
The comparison of reference time is stated, and comparative result is fed back to into the time delay module to adjust second time.
4. leadage circuit according to claim 3, it is characterised in that：Described logic circuit includes the first trigger and the
Two triggers, described time delay module output characterizes the status signal whether time delay terminates, the set end of first trigger
Receive the status signal whether sign time delay terminates, the outfan of input voltage detection circuit and the outfan of time delay module
NAND gate is respectively connected to, the outfan of the NAND gate is connected with the replacement end of first trigger；First trigger
Outfan negate after be connected with the set end of second trigger, the outfan of drive circuit input electric cur- rent measure circuit takes
It is connected with the replacement end of second trigger after anti-, the outfan of second trigger and the drive circuit input current
The outfan of detection circuit connects respectively two inputs with door, the outfan and the outfan of the first trigger with door
Connect two inputs of OR gate respectively, OR gate output characterizes the signal that whether enables to the module of releasing, it is described with
The outfan of door exports the timing signal for characterizing the very first time.
5. leadage circuit according to claim 1, it is characterised in that：Described control circuit of releasing is defeated including drive circuit
Enter current detection circuit, vent discharge current detection circuit and logic circuit, described logic circuit connects with the control end of module of releasing
Connect, described drive circuit input electric cur- rent measure circuit sampling drive circuit input current, and be compared with threshold current；Institute
During input voltage zero passage detection, module of releasing described in the logic circuit control is produced lets out the vent discharge current detection circuit stated
Discharge stream, the leakage current of sampling, and be compared with threshold value of releasing；The drive circuit input current is less than the threshold value
During electric current, start timing, when the leakage current reaches releases threshold value, timing terminates, when the timing time is as the 3rd
Between.
6. leadage circuit according to claim 5, it is characterised in that：The threshold is less than in the drive circuit input current
During value electric current, judge that input voltage reaches zero crossing Jing after the 3rd time；And timing or variable interval updated for the 3rd time.
7. leadage circuit according to claim 5, it is characterised in that：When judging that input voltage reaches zero crossing, time delay
After second time, module of releasing described in the control of Jing logic circuits produces leakage current；Described drive circuit input electric cur- rent measure
Electric circuit inspection drive circuit input current, when sample rate current reaches the threshold current for characterizing predetermined value, then Jing logic circuits control
Leakage current processed is zero；The very first time is compared with the reference time, institute is correspondingly adjusted according to comparative result
Stated for the second time.
8. leadage circuit according to claim 7, it is characterised in that：Described control circuit of releasing also includes time delay mould
Block, time comparison module and zero passage judge module, described time delay module outfan, logic electricity respectively with zero passage judge module
Road and time comparison module connect, the zero passage judge module respectively with the outfan and drive circuit of vent discharge current detection circuit
The outfan connection of input electric cur- rent measure circuit；Timing is carried out to the 3rd time by the zero passage judge module, and judges input
The zero crossing moment of voltage, described time delay module receives the letter at the sign zero crossing moment of the zero passage judge module output
Number, and the time of time delay second, after time delay terminates, leakage current is produced by logic circuit control, in the time comparison module
In carry out the comparison of the very first time and the reference time, and comparative result is fed back to into the time delay module to adjust described
Two times.
9. leadage circuit according to claim 8, it is characterised in that：Described logic circuit includes the 3rd trigger and the
Four triggers, described time delay module output characterizes the status signal whether time delay terminates, the set end of the 3rd trigger
Receive the status signal whether sign time delay terminates, the outfan of zero passage judge module and the outfan difference of time delay module
NAND gate is accessed, the outfan of the NAND gate is connected with the replacement end of the 3rd trigger；3rd trigger it is defeated
Go out after end negates and be connected with the set end of the 4th trigger, after the outfan of drive circuit input electric cur- rent measure circuit is negated
It is connected with the replacement end of the 4th trigger, the outfan and the drive circuit input electric cur- rent measure of the 4th trigger
The outfan of circuit connects respectively two inputs of first and door, the outfan and table of drive circuit input electric cur- rent measure circuit
The signal whether zero judge module of going on a punitive expedition enables is respectively connected to two inputs of second and door；Described first with the output of door
End, second are connected respectively three inputs of OR gate with the outfan of door and the outfan of the 3rd trigger, and the OR gate is exported
To the module of releasing, described first exports based on characterizing the very first time signal whether sign enables with the outfan of door
When signal.
10. a kind of LED control circuit, it is characterised in that：Drive including any one leadage circuit of above claim 1-8 and LED
Galvanic electricity road, described LED drive circuit is linear drive circuit or on-off circuit.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621252478.4U CN206181454U (en) | 2016-11-16 | 2016-11-16 | Bleeder circuit and LED control circuit |
| US15/490,002 US10143051B2 (en) | 2016-11-16 | 2017-04-18 | Bleeder circuit and control method thereof, and LED control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621252478.4U CN206181454U (en) | 2016-11-16 | 2016-11-16 | Bleeder circuit and LED control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206181454U true CN206181454U (en) | 2017-05-17 |
Family
ID=58686719
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621252478.4U Withdrawn - After Issue CN206181454U (en) | 2016-11-16 | 2016-11-16 | Bleeder circuit and LED control circuit |
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| Country | Link |
|---|---|
| CN (1) | CN206181454U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106793246A (en) * | 2016-11-16 | 2017-05-31 | 杰华特微电子（杭州）有限公司 | Leadage circuit and its control method and LED control circuit |
| CN107864532A (en) * | 2017-11-03 | 2018-03-30 | 杰华特微电子（杭州）有限公司 | LED light adjusting circuits and method and LED control circuit |
| CN107979888A (en) * | 2017-11-03 | 2018-05-01 | 杰华特微电子（杭州）有限公司 | LED light adjusting circuits and method |
| CN110113841A (en) * | 2018-05-25 | 2019-08-09 | 矽力杰半导体技术(杭州)有限公司 | LED drive circuit, circuit module and control method with controllable silicon dimmer |
-
2016
- 2016-11-16 CN CN201621252478.4U patent/CN206181454U/en not_active Withdrawn - After Issue
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106793246A (en) * | 2016-11-16 | 2017-05-31 | 杰华特微电子（杭州）有限公司 | Leadage circuit and its control method and LED control circuit |
| CN106793246B (en) * | 2016-11-16 | 2019-04-02 | 杰华特微电子（杭州）有限公司 | Leadage circuit and its control method and LED control circuit |
| CN107864532A (en) * | 2017-11-03 | 2018-03-30 | 杰华特微电子（杭州）有限公司 | LED light adjusting circuits and method and LED control circuit |
| CN107979888A (en) * | 2017-11-03 | 2018-05-01 | 杰华特微电子（杭州）有限公司 | LED light adjusting circuits and method |
| CN107864532B (en) * | 2017-11-03 | 2023-09-26 | 杰华特微电子股份有限公司 | LED dimming circuit and method and LED control circuit |
| CN107979888B (en) * | 2017-11-03 | 2023-11-17 | 杰华特微电子股份有限公司 | LED dimming circuit and method |
| CN110113841A (en) * | 2018-05-25 | 2019-08-09 | 矽力杰半导体技术(杭州)有限公司 | LED drive circuit, circuit module and control method with controllable silicon dimmer |
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