CN206114295U

CN206114295U - Portable bearing state monitoring system based on FPGA

Info

Publication number: CN206114295U
Application number: CN201621071058.6U
Authority: CN
Inventors: 柯磊; 吴继忠; 李永桃; 李塘
Original assignee: Panzhihua University
Current assignee: Panzhihua University
Priority date: 2016-09-22
Filing date: 2016-09-22
Publication date: 2017-04-19
Anticipated expiration: 2026-09-22

Abstract

The utility model relates to a mechanical breakdown detection technique provides portable bearing state monitoring system based on FPGA, monitors the running state of bearing to a prevention, prediction for equipment trouble. Including acceleration sensor, signal conditioning module, AD converter, FPGA chip, power management module and instrument panel, acceleration sensor locates on the bearing, acceleration sensor with signal conditioning module connects, signal conditioning module with the AD converter is connected, the AD converter with main control chip connects, the FPGA chip with the instrument panel is connected. The utility model is suitable for a portable bearing state monitor.

Description

Portable bearing condition monitoring system based on FPGA

Technical field

The utility model is related to mechanical fault detection technology, more particularly to the portable bearing condition monitoring system based on FPGA System.

Background technology

At present most-often used in fault detection technique is Vibration Technique, i.e., by detecting the acceleration of vibration signal The information such as degree, speed, displacement, phase place are diagnosing the running status of rotary machine.However, bearing fault is but difficult from above-mentioned letter Obtain in breath.At present, the method for bearing failure diagnosis mainly has the envelope based on Hilbert transform and based on wavelet transformation to examine Wave analysis method, but its calculating complicated and time consumption is long, and be not suitable for being realized on the inspection device based on embedded system.

Calculate complicated for current envelope detection algorithm and be not suitable for carrying out bearing condition monitoring on portable devices examining Disconnected problem, FPGA is electric by hardware such as amplifying circuit of analog signal, filter circuit and envelope detection circuits as main control chip Road realize envelope signal extract, detection function and the bearing condition monitoring technology that grows up, the system can monitor the fortune of bearing Row state, the early stage for grasping failure occurs, develops, and accurately judges the equipment fault order of severity.

Utility model content

The technical problems to be solved in the utility model is：A kind of portable bearing condition monitoring system based on FPGA is provided System, monitors the running status of bearing, so as to be used for prevention, the prediction of equipment fault.

To solve the above problems, the technical solution adopted in the utility model is：Portable bearing state based on FPGA is supervised Examining system, including acceleration transducer, Signal-regulated kinase, A/D converter, fpga chip, power management module and instrument Panel, on bearing, the acceleration transducer is connected the acceleration transducer with the Signal-regulated kinase, the letter Number conditioning module is connected with the A/D converter, and A/D converter is connected with the fpga chip, the fpga chip with it is described Instrument panel connects.

Further, the Signal-regulated kinase includes filtering and amplifying circuit, bandpass filter and envelope detection circuit, institute State filtering and amplifying circuit to be connected with the acceleration transducer, bandpass filter, the bandpass filter and the envelope detection Circuit connects, and the envelope detection circuit is connected with the A/D converter.

Specifically, the sign-changing amplifier reality that the filtering and amplifying circuit is consisted of internal two groups of track to track operational amplifiers The amplification of existing signal.

Specifically, the bandpass filter is high with two second order Butterworths by two second order Butterworth LPFs Bandpass filter is in series.

Further, the power management module includes battery and electric power management circuit.

Further, the instrument panel includes display screen and keyboard.

Further, the utility model also includes external communication interface and communication equipment, and communication equipment is by external communication Interface is connected with the fpga chip.

The beneficial effects of the utility model are：The utility model analyzes the method pair of envelope rectified signal by fpga chip The monitoring of bearing running status, the early stage that not only can grasp failure occurs, develops, and accurately judges the equipment fault order of severity, Realize prevention, the prediction of equipment fault；And embedded architecture of the utility model based on FPGA, with fast operation, just The property taken is strong, low-power consumption, high performance advantage.

Description of the drawings

Fig. 1 is structural representation of the present utility model；

Fig. 2 is the structural representation of the utility model signal condition part；

Fig. 3 is the filtering and amplifying circuit figure of embodiment；

Fig. 4 is the envelope detection circuit figure of embodiment；

Fig. 5 is the oscillogram of the input signal of envelope detection circuit；

Fig. 6 is the positive axis oscillogram of the input signal of envelope detection circuit；

Fig. 7 is the negative semiaxis oscillogram of the input signal of envelope detection circuit；

Fig. 8 is the oscillogram of the output signal of envelope detection circuit

Number in figure：U1A, U1B, U41,42, U43 are respectively the first to the 5th amplification chip, and R3 is 3rd resistor, and R4 is 4th resistance, R32 be the three or two resistance, the electric capacity of C2 second, the electric capacity of C3 the 3rd, the electric capacity of C34 the three or four, the electric capacity of C35 the three or five, D For diode group.

Specific embodiment

As shown in figure 1, including acceleration transducer, Signal-regulated kinase, A/D converter, fpga chip, power management mould Block, instrument panel, external communication interface and communication equipment, on bearing, the acceleration is passed the acceleration transducer Sensor is connected with the Signal-regulated kinase, and the Signal-regulated kinase is connected with the A/D converter, A/D converter and institute Fpga chip connection is stated, the fpga chip is connected with the instrument panel, external communication interface；The external communication interface with The communication equipment connection.

Specifically, the Signal-regulated kinase includes filtering and amplifying circuit, bandpass filter and envelope detection circuit, described Filtering and amplifying circuit is connected with the acceleration transducer, bandpass filter, and the bandpass filter and the envelope detection are electric Road connects, and the envelope detection circuit is connected with the A/D converter.The power management module includes battery and power management Circuit.The instrument panel includes display screen and keyboard.

Bearing breaks down and produces recurrent pulses impact (vibration signal), and Signal-regulated kinase is completed to the vibration signal Noise reduction, amplification and filtering process, carry out envelope detection, A/D converter converts the electrical signal to data signal and transmits To fpga chip, FPGA completes the calculating to data signal and processes, and keyboard display shows bearing running status, meanwhile, power supply Power supply needed for the work of management module feed system.

Specifically, fpga chip realizes that function can be subdivided into following functions module：Collection memory module, data calculate mould Block, main control module and each outer communication interface modules.Main control module is responsible for receiving and sending control instruction, and collection drive module is responsible for Drive, A/D converter is simulated signal to the conversion of data signal；Data processing module is responsible for entering the data that A/D is gathered Row goes direct current, peaking and DFT to calculate.Display module is responsible for driving display screen in real time to include result of calculation on instrument, to lead to Letter module is responsible for driving external communication interface to carry out data transmission with the external world.

Signal condition process of the present utility model is as shown in Fig. 2 the periodically pulsing impact of element damage generation, evokes axle Hold system high-frequency intrinsic vibration, form the vibration signal with characteristic fault frequency as fundamental frequency, acceleration transducer is by vibration signal It is transformed into electric signal, filtering and amplifying circuit is simultaneously amplified its amplitude, and by bandpass filter low frequency signal, envelope detection are filtered Circuit carries out envelope detection to high-frequency signal, and A/D converter converts the electrical signal to data signal, by fpga chip to envelope number Word signal carries out time and frequency domain characteristics analysis.Therefore, the utility model obtains envelope by envelope detection method, and carries out time-frequency domain Signature analysis can reach the requirement of fault diagnosis.

Embodiment：

Filtering and amplifying circuit structure in this example is as shown in figure 3, sensor output signal first passes around two-stage RC low pass filtered Wave circuit：3rd resistor R3 → the second electric capacity C2 and the 4th resistance R4 → the 3rd electric capacity C3, removes high-frequency noise interference；Then, Through the sign-changing amplifier that two groups of low noise track to track amplifiers are constituted：First amplification chip U1A and the second amplification chip U1B, it is real The noise reduction of existing signal and amplification.Wherein, the first amplification chip U1A and the second amplification chip U1B is 8606A chips.

Bandpass filter：Two second order Butterworth LPFs and two second order butterworth high pass filter strings Connection, realizes removing noise frequency, selects purpose signal.This instrument choose acceleration signal frequency range be 500Hz～ 10kHz.Filter cutoff frequency can be calculated with following formula：

Envelope detection circuit structure in this example is as shown in figure 4, the high-frequency signal after filter amplification circuit is examined into envelope Wave circuit carries out envelope detection.First order circuit carries out stopping direct current operation with the three or five electric capacity C35, removes bias voltage；Two poles Pipe group D：The positive and negative semiaxis of signal is separated using one-way flow effect；Fig. 5 represents the sinusoidal signal of input, and Fig. 6,7 are respectively Positive and negative half axis signal of signal of this grade of circuit output.Second level circuit is with the 3rd amplification chip U41, the 4th amplification chip U42 two Individual transport and placing device makees follower, and anti-stop signal is changed due to load effect.Tertiary circuit with the 5th amplification chip U43, The low pass filtering and amplifying circuit of three or two resistance R32, the three or four electric capacity C34 composition is turned to the signal that semiaxis is born in output waveform Positive axis, is reduced, so being put to output signal by resistance configuration due to carrying out peak-to-peak value after absolute value operation to signal Greatly, multiplication factor is 1.5～2 times.Output waveform is as shown in Figure 8.It is above-mentioned, the 3rd amplification chip U41, the 4th amplification chip U42, 5th amplification chip U43 is LTC2652 chips.

It is pointed out that some principles of the present invention that simply explains through diagrams described above, due to constructed neck It is easy to carry out some modifications on this basis for the those of ordinary skill in domain and changes.Therefore, this specification is not Be by the present invention be confined to shown in and described concrete structure and the scope of application in, therefore it is every be possible to be utilized it is corresponding Modification and equivalent, belong to apllied the scope of the claims of the invention.

Claims

1. the portable bearing condition monitoring system of FPGA is based on, it is characterised in that including acceleration transducer, signal condition mould Block, A/D converter, fpga chip, power management module and instrument panel, the acceleration transducer is located on bearing, institute State acceleration transducer to be connected with the Signal-regulated kinase, the Signal-regulated kinase is connected with the A/D converter, A/D Converter is connected with the fpga chip, and the fpga chip is connected with the instrument panel.

2. the portable bearing condition monitoring system of FPGA is based on as claimed in claim 1, it is characterised in that the signal is adjusted Reason module includes filtering and amplifying circuit, bandpass filter and envelope detection circuit, the filtering and amplifying circuit and the acceleration Sensor, bandpass filter connection, the bandpass filter be connected with the envelope detection circuit, the envelope detection circuit and The A/D converter connection.

3. the portable bearing condition monitoring system of FPGA is based on as claimed in claim 2, it is characterised in that the amplification filter Wave circuit realizes the amplification of signal by the sign-changing amplifier that internal two groups of track to track operational amplifiers are constituted.

4. the portable bearing condition monitoring system of FPGA is based on as claimed in claim 2, it is characterised in that the band logical filter Ripple device is in series by two second order Butterworth LPFs with two second order butterworth high pass filters.

5. the portable bearing condition monitoring system of FPGA is based on as claimed in claim 1, it is characterised in that the power supply pipe Reason module includes battery and electric power management circuit.

6. the portable bearing condition monitoring system of FPGA is based on as claimed in claim 1, it is characterised in that the tool face Plate includes display screen and keyboard.

7. the portable bearing condition monitoring system of FPGA is based on as claimed in claim 1, it is characterised in that also including external Communication interface and communication equipment, communication equipment is connected by external communication interface with the fpga chip.