CN205992725U - A kind of electrical network overvoltage/undervoltage testing circuit based on FPGA - Google Patents
A kind of electrical network overvoltage/undervoltage testing circuit based on FPGA Download PDFInfo
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- CN205992725U CN205992725U CN201620639588.XU CN201620639588U CN205992725U CN 205992725 U CN205992725 U CN 205992725U CN 201620639588 U CN201620639588 U CN 201620639588U CN 205992725 U CN205992725 U CN 205992725U
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Abstract
This utility model provides a kind of electrical network overvoltage/undervoltage testing circuit based on FPGA, while realizing electrical network overvoltage and under-voltage protection, is not take up the MCU resource of preciousness, and the hidden danger that the resistance that there is not adjustable potentiometer easily changes.Including the absolute value circuit being sequentially connected, comparison circuit and FPGA control module；The line voltage collecting is carried out absolute value conversion by described absolute value circuit；It is compared with the reference voltage that fixed resistance sets in the absolute value voltage signal that described absolute value circuit is converted to by described comparison circuit and comparison circuit and obtain pulse train signal；The described pulse signal receiving is processed by FPGA control module, over-pressed to electrical network or under-voltage report to the police.
Description
Technical field
This utility model is related to power supply unit input protection field, particularly to a kind of inspection of electrical network overvoltage/undervoltage based on FPGA
Slowdown monitoring circuit.
Background technology
At present in the detection over-pressed or under-voltage for electrical network using there being two methods, one kind is using AD, line voltage to be entered
Row collection, but the method will take considerable MCU resource, and also algorithm is complicated, and reliability is low；Another method is to adopt
Use hardware relative method, this method needs to be adjusted using adjustable potentiometer, not only adjust inconvenience, and there is adjustable potential
The hidden danger of the test point easily drift that device is brought due to poor contact of contacts, and need for AC signal to be converted into direct current signal response
Speed is slow.
Utility model content
This utility model provides a kind of electrical network overvoltage/undervoltage testing circuit based on FPGA, over-pressed and under-voltage realizing electrical network
While protection, it is not take up the MCU resource of preciousness, and the hidden danger that the resistance that there is not adjustable potentiometer easily changes, response speed
Degree is fast.
For achieving the above object, technical solutions of the utility model are：
A kind of electrical network overvoltage/undervoltage testing circuit based on FPGA, including the absolute value circuit being sequentially connected, comparison circuit with
And FPGA control module；
The line voltage collecting is carried out absolute value conversion by described absolute value circuit；
With solid in the absolute value voltage signal that described absolute value circuit is converted to by described comparison circuit and comparison circuit
The reference voltage determining resistance setting is compared and obtains pulse train signal；
The described pulse signal receiving is processed by FPGA control module, over-pressed to electrical network or under-voltage report
Alert.
Further, described absolute value circuit includes transformator T1, amplifier U1A, amplifier U1B, diode D1, two poles
Pipe D2, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5 and resistance R6；The input of described transformator T1 accesses and treats
Survey electrical network, outfan one end ground connection of described transformator T1, the other end is divided into two-way after being connected with described resistance R1, a road and institute
State resistance R2 one end to connect, another road is connected with the input cathode of described amplifier U1A；The other end of described resistance R2 and institute
State diode D1 negative pole connect connect with described resistance R4 again after access the input cathode of described amplifier U1B；Described put
The input anode ground connection of big device U1A, outfan is divided into two-way, and a road is connected with the positive pole of described diode D1, a road and institute
The negative pole stating diode D2 connects；The positive pole of described diode D2 is divided into two-way, and institute is accessed after connecting with described resistance R3 in a road
State the input cathode of amplifier U1A, described amplifier U1B is accessed on another road with described resistance R5 input after connecting is born
Pole；The input cathode of described amplifier U1B is connected with its outfan after being connected with described resistance R6；Described amplifier U1B's
Outfan accesses the input of described comparison circuit.
Further, described comparison circuit includes overvoltage comparison circuit and under-voltage comparison circuit.
Further, described overvoltage comparison circuit includes comparator U2A, resistance R8, resistance R9, resistance R10 and resistance
R11；The input anode of described comparator U2A is connected with the outfan of described amplifier U1B；Described resistance R9 one end accesses the
One DC source, the other end is grounded after being connected with described resistance R8；The input cathode of described comparator U2A accesses described resistance
R8 and the link node of described resistance R9；The outfan of described comparator U2A is divided into two-way, and a road is connected with described resistance R10
After access the second DC source, the other end accesses the input of described FPGA module with described resistance R11 after connecting.
Further, described under-voltage comparison circuit includes comparator U2B, resistance R12, resistance R13, resistance R14 and electricity
Resistance R15；The input anode of described comparator U2B is connected with the outfan of described amplifier U1B；Described resistance R13 mono- terminates
Enter the first DC source, the other end is grounded after being connected with described resistance R12；The input cathode of described comparator U2B accesses institute
State resistance R12 and the link node of described resistance R13；The outfan of described comparator U2B is divided into two-way, a road and described resistance
R14 accesses the second DC source after connecting, and the other end accesses the input of described FPGA module with described resistance R15 after connecting.
Further, the voltage of described first DC source is 12V, and the voltage of described second DC source is 3.3V.
Further, the frequency of described pulse signal is 100Hz.
Further, described FPGA control module is configured to the pulsewidth of pulse signal described in receiving record and by described pulse
The pwm value of signal is compared with given pulse width threshold, exceeds described given pulsewidth threshold in the pwm value of described pulse signal
Alarm signal is sent during value.
From above-mentioned to description of the present utility model, compared to the prior art, this utility model has the advantage that：
First, this utility model is detected to the overvoltage/undervoltage of electrical network using FPGA control module, and circuit is simple, without using
, therefore there is not the hidden danger that the resistance of adjustable potentiometer easily changes, improve the reliability of detection in adjustable potentiometer, and need not be by
AC signal is judged after being converted into direct current signal again, and response speed is faster.
2nd, this utility model adopts FPGA control module, and algorithm is simple, and no longer takies MCU resource and the AD mouth of preciousness,
Ensure that the execution of network system main task.
3rd, by the digital regulated regulation that can achieve overvoltage point and under-voltage point within FPGA in this utility model, make
Pressure point must be crossed and the regulation of under-voltage point is more flexible and convenient.
Brief description
Accompanying drawing described herein is used for providing further understanding to of the present utility model, constitutes one of the present utility model
Point, schematic description and description of the present utility model is used for explaining this utility model, does not constitute to of the present utility model
Improper restriction.In the accompanying drawings：
Fig. 1 is system block diagram of the present utility model；
Fig. 2 is circuit diagram of the present utility model；
The waveform variation diagram that Fig. 3 changes through system for this utility model electric current；
Fig. 4 is the workflow diagram one of this utility model FPGA；
Fig. 5 is the workflow diagram two of this utility model FPGA.
Specific embodiment
In order that technical problem to be solved in the utility model, technical scheme and beneficial effect are clearer, clear, with
Under in conjunction with the accompanying drawings and embodiments, this utility model is further elaborated.It should be appreciated that concrete reality described herein
Apply example only in order to explain this utility model, be not used to limit this utility model.
Referring to figs. 1 to Fig. 5, a kind of electrical network overvoltage/undervoltage testing circuit based on FPGA, including the absolute value electricity being sequentially connected
Road, comparison circuit and FPGA control module；
The line voltage collecting is carried out absolute value conversion by described absolute value circuit；
With solid in the absolute value voltage signal that described absolute value circuit is converted to by described comparison circuit and comparison circuit
The reference voltage determining resistance setting is compared and obtains pulse train signal；The frequency of described pulse signal is 100Hz.
The described pulse signal receiving is processed by FPGA control module, over-pressed to electrical network or under-voltage report
Alert.
Described absolute value circuit includes transformator T1, amplifier U1A, amplifier U1B, diode D1, diode D2, resistance
R1, resistance R2, resistance R3, resistance R4, resistance R5 and resistance R6；The input of described transformator T1 accesses electrical network to be measured, institute
State outfan one end ground connection of transformator T1, the other end is divided into two-way after being connected with described resistance R1, a road and described resistance R2
One end connects, and another road is connected with the input cathode of described amplifier U1A；The other end of described resistance R2 and described diode
The negative pole connection of D1 accesses the input cathode of described amplifier U1B with described resistance R4 after connecting again；Described amplifier U1A's
Input anode is grounded, and outfan is divided into two-way, and a road is connected with the positive pole of described diode D1, a road and described diode D2
Negative pole connect；The positive pole of described diode D2 is divided into two-way, and described amplifier U1A is accessed on a road with described resistance R3 after connecting
Input cathode, the input cathode of described amplifier U1B is accessed on another road with described resistance R5 after connecting；Described amplifier
The input cathode of U1B is connected with its outfan after being connected with described resistance R6；The outfan of described amplifier U1B accesses described
The input of comparison circuit.
Described comparison circuit includes overvoltage comparison circuit and under-voltage comparison circuit.Described overvoltage comparison circuit includes comparator
U2A, resistance R8, resistance R9, resistance R10 and resistance R11；The input anode of described comparator U2A and described amplifier U1B
Outfan connect；The first DC source is accessed in described resistance R9 one end, and the other end is grounded after being connected with described resistance R8；Described
The input cathode of comparator U2A accesses the link node of described resistance R8 and described resistance R9；The output of described comparator U2A
End is divided into two-way, and the second DC source is accessed on a road with described resistance R10 after being connected, after the other end is connected with described resistance R11
Access the input of described FPGA module.
Described under-voltage comparison circuit includes comparator U2B, resistance R12, resistance R13, resistance R14 and resistance R15；Described
The input anode of comparator U2B is connected with the outfan of described amplifier U1B；The first direct current is accessed in described resistance R13 one end
Power supply, the other end is grounded after being connected with described resistance R12；The input cathode of described comparator U2B access described resistance R12 and
The link node of described resistance R13；The outfan of described comparator U2B is divided into two-way, and a road is connected with described resistance R14 and is followed by
Enter the second DC source, the other end accesses the input of described FPGA module with described resistance R15 after connecting.First DC source
Voltage be 12V, the voltage of described second DC source is 3.3V.
Described FPGA control module is configured to pulsewidth the arteries and veins by described pulse signal of pulse signal described in receiving record
Width values are compared with given pulse width threshold, send when the pwm value of described pulse signal exceeds described given pulse width threshold
Alarm signal.
With reference to Fig. 3 to Fig. 5, wherein, in step (2) to step (5), the waveform of voltage changes with reference to Fig. 3,
Its detecting step is as follows：
(1), line voltage is converted to low-voltage ac signal through transformator；
(2), described low-voltage ac signal is carried out absolute value conversion through absolute value circuit, obtain positive voltage signal；
(3), described positive voltage signal is inputted to comparison circuit；
(4), described comparison circuit includes overvoltage comparison circuit and under-voltage comparison circuit, described overvoltage comparison circuit and described
Described positive voltage signal and respective reference voltage are compared and obtain pulse train signal by under-voltage comparison circuit respectively, and will
Comparative result inputs to FPGA control module；
(5), the pulsewidth of the pulse signal of described FPGA control module record input, if described overvoltage pwm value is more than etc.
In given over-pressed pulse width threshold, then FPGA sends alarm signal, such as less than given over-pressed pulse width threshold, then by described overvoltage
The clearing of pulsewidth recording value again start recording pulsewidth next time；If described under-voltage pwm value is less than or equal to given under-voltage arteries and veins
Wide threshold value, then FPGA send alarm signal, such as larger than given under-voltage pulse width threshold, then will described under-voltage pulsewidth recording value clearing
And start recording pulsewidth next time again.
When positive voltage signal described in its step (4) is more than the reference voltage of described overvoltage comparison circuit, described pressure ratio excessively
Compared with circuit output high level, on the contrary output low level；When described positive voltage signal is more than the benchmark electricity of described under-voltage comparison circuit
During pressure, described under-voltage comparison circuit exports high level, on the contrary output low level.
Circuit diagram of the present utility model as shown in Fig. 2 wherein FPGA control module adopt model EP4CE6, this model
The above-mentioned functions of module be well known to a person skilled in the art, therefore use when only need to by programming just can realize above-mentioned
Function.
Circuit diagram in this utility model is one-way circuit figure, if using in three-phase circuit in figure, thus three unidirectional
Circuit constitute.
Described above illustrate and describes preferred embodiment of the present utility model, as previously mentioned it should be understood that this practicality is new
Type is not limited to form disclosed herein, is not to be taken as the exclusion to other embodiment, and can be used for various other groups
Close, change and environment, and can be in utility model contemplated scope described herein, by the technology of above-mentioned teaching or association area
Or knowledge is modified.And the change that those skilled in the art are carried out and change be without departing from spirit and scope of the present utility model, then
All should be in the protection domain of this utility model claims.
Claims (7)
1. a kind of electrical network overvoltage/undervoltage testing circuit based on FPGA it is characterised in that：Including the absolute value circuit being sequentially connected, ratio
Compared with circuit and FPGA control module；
The line voltage collecting is carried out absolute value conversion by described absolute value circuit；
With fixing electricity in the absolute value voltage signal that described absolute value circuit is converted to by described comparison circuit and comparison circuit
The reference voltage that resistance sets is compared and obtains pulse train signal；
The described pulse signal receiving is processed by FPGA control module, over-pressed to electrical network or under-voltage report to the police.
2. as claimed in claim 1 a kind of electrical network overvoltage/undervoltage testing circuit based on FPGA it is characterised in that：Described absolute value
Circuit include transformator T1, amplifier U1A, amplifier U1B, diode D1, diode D2, resistance R1, resistance R2, resistance R3,
Resistance R4, resistance R5 and resistance R6；The input of described transformator T1 accesses electrical network to be measured, the outfan of described transformator T1
One end is grounded, and the other end is divided into two-way after being connected with described resistance R1, and a road is connected with described resistance R2 one end, another road and institute
The input cathode stating amplifier U1A connects；The other end of described resistance R2 be connected with the negative pole of described diode D1 again with institute
The input cathode of described amplifier U1B is accessed after stating resistance R4 series connection；The input anode ground connection of described amplifier U1A is defeated
Go out end and be divided into two-way, a road is connected with the positive pole of described diode D1, and a road is connected with the negative pole of described diode D2；Described two
The positive pole of pole pipe D2 is divided into two-way, and the input cathode of described amplifier U1A is accessed on a road with described resistance R3 after connecting, another
The input cathode of described amplifier U1B is accessed on road with described resistance R5 after connecting；The input cathode of described amplifier U1B with
Described resistance R6 is connected with its outfan after connecting；The outfan of described amplifier U1B accesses the input of described comparison circuit.
3. as claimed in claim 2 a kind of electrical network overvoltage/undervoltage testing circuit based on FPGA it is characterised in that：Described comparison is electric
Road includes overvoltage comparison circuit and under-voltage comparison circuit.
4. as claimed in claim 3 a kind of electrical network overvoltage/undervoltage testing circuit based on FPGA it is characterised in that：Described pressure ratio excessively
Include comparator U2A, resistance R8, resistance R9, resistance R10 and resistance R11 compared with circuit；The input of described comparator U2A is rectified
Pole is connected with the outfan of described amplifier U1B；The first DC source, the other end and described resistance are accessed in described resistance R9 one end
It is grounded after R8 series connection；The input cathode of described comparator U2A accesses the link node of described resistance R8 and described resistance R9；Institute
The outfan stating comparator U2A is divided into two-way, and the second DC source is accessed on a road with described resistance R10 after being connected, the other end with
The input of described FPGA module is accessed after described resistance R11 series connection.
5. as claimed in claim 3 a kind of electrical network overvoltage/undervoltage testing circuit based on FPGA it is characterised in that：Described under-voltage ratio
Include comparator U2B, resistance R12, resistance R13, resistance R14 and resistance R15 compared with circuit；The input of described comparator U2B
Positive pole is connected with the outfan of described amplifier U1B；The first DC source is accessed in described resistance R13 one end, the other end with described
It is grounded after resistance R12 series connection；The input cathode of described comparator U2B accesses the connection of described resistance R12 and described resistance R13
Node；The outfan of described comparator U2B is divided into two-way, and the second DC source is accessed after being connected with described resistance R14 in a road, separately
One end accesses the input of described FPGA module with described resistance R15 after connecting.
6. a kind of electrical network overvoltage/undervoltage testing circuit based on FPGA as described in claim 4 or claim 5, its feature exists
In：The voltage of described first DC source is 12V, and the voltage of described second DC source is 3.3V.
7. as claimed in claim 1 a kind of electrical network overvoltage/undervoltage testing circuit based on FPGA it is characterised in that：Described pulse letter
Number frequency be 100Hz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620639588.XU CN205992725U (en) | 2016-06-24 | 2016-06-24 | A kind of electrical network overvoltage/undervoltage testing circuit based on FPGA |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620639588.XU CN205992725U (en) | 2016-06-24 | 2016-06-24 | A kind of electrical network overvoltage/undervoltage testing circuit based on FPGA |
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| CN205992725U true CN205992725U (en) | 2017-03-01 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105958435A (en) * | 2016-06-24 | 2016-09-21 | 中航太克（厦门）电力技术股份有限公司 | FPGA-based power grid overvoltage and undervoltage detection circuit and method |
| CN109066573A (en) * | 2018-09-30 | 2018-12-21 | 张健 | A kind of new-energy automobile apparatus for protecting power supply |
| CN109560535A (en) * | 2018-11-09 | 2019-04-02 | 天津航空机电有限公司 | A kind of AC overvoltage fast protection circuit |
-
2016
- 2016-06-24 CN CN201620639588.XU patent/CN205992725U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105958435A (en) * | 2016-06-24 | 2016-09-21 | 中航太克（厦门）电力技术股份有限公司 | FPGA-based power grid overvoltage and undervoltage detection circuit and method |
| CN109066573A (en) * | 2018-09-30 | 2018-12-21 | 张健 | A kind of new-energy automobile apparatus for protecting power supply |
| CN109560535A (en) * | 2018-11-09 | 2019-04-02 | 天津航空机电有限公司 | A kind of AC overvoltage fast protection circuit |
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