CN205666812U - Timer circuit - Google Patents

Timer circuit Download PDF

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Publication number
CN205666812U
CN205666812U CN201620082715.0U CN201620082715U CN205666812U CN 205666812 U CN205666812 U CN 205666812U CN 201620082715 U CN201620082715 U CN 201620082715U CN 205666812 U CN205666812 U CN 205666812U
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CN
China
Prior art keywords
resistance
gate
diode
electric capacity
connects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201620082715.0U
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Chinese (zh)
Inventor
王淳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tianjin Jin Pu Technology Co Ltd Godiva
Original Assignee
Tianjin Jin Pu Technology Co Ltd Godiva
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tianjin Jin Pu Technology Co Ltd Godiva filed Critical Tianjin Jin Pu Technology Co Ltd Godiva
Priority to CN201620082715.0U priority Critical patent/CN205666812U/en
Application granted granted Critical
Publication of CN205666812U publication Critical patent/CN205666812U/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Abstract

The utility model discloses a timer circuit, including not gate F1, NAND gate F2, resistance R1, electric capacity C1, diode D1, emitting diode LED and triode VT1, anodal and the power VCC of emitting diode LED is connected respectively to triode VT1 projecting pole, diode D2 negative pole and relay J coil are connected respectively to triode VT1 collecting electrode, triode VT1 base connecting resistance R4, NAND gate F2 output and electric capacity C2 are connected respectively to the resistance R4 other end, emitting diode LED negative pole and key switch S are connected respectively to the electric capacity C2 other end, the key switch S other end is connecting resistance R1 and diode D1 positive pole respectively, the resistance R1 other end is connecting resistance R2 and not gate F1 input respectively, input of NAND gate F2 is connected to not gate F1 output. The utility model discloses timer circuit adopts not gate and AND gate cooperation triode as controlling element, and circuit structure is simple, and is with low costs, small, and owing to not adopting chip element to control, the interference killing feature is strong moreover.

Description

A kind of timer circuit
Technical field
This utility model relates to a kind of intervalometer, specifically a kind of timer circuit.
Background technology
Relay is a kind of electric control device, is when the change of input quantity (energizing quantity) reaches regulation requirement, the most defeated Go out circuit makes controlled volume that a kind of electrical equipment of predetermined Spline smoothing occurs.It has control system (also known as input circuit) and By the interactive relationship between control system (also known as output loop).Being commonly used in the control circuit of automatization, it is actual On be the one " switch automatically " going to control the running of big electric current with small area analysis.Therefore play in circuit be automatically adjusted, safety protect Protect, change-over circuit etc. acts on.
Existing intervalometer uses time base circuit NE555 and relay to jointly control mostly, but NE555 chip controls exists The problem that capacity of resisting disturbance is weak.
Utility model content
The purpose of this utility model is to provide a kind of timer circuit, with the problem solving to propose in above-mentioned background technology.
For achieving the above object, the following technical scheme of this utility model offer:
A kind of timer circuit, including not gate F1, NAND gate F2, resistance R1, electric capacity C1, diode D1, light-emitting diodes Pipe LED and audion VT1, described audion VT1 emitter stage connecting luminous diode LED positive pole and power supply VCC respectively, Audion VT1 colelctor electrode connects diode D2 negative pole and relay J coil respectively, and audion VT1 base stage connects resistance R4, The resistance R4 other end connects NAND gate F2 outfan and electric capacity C2 respectively, electric capacity C2 other end connecting luminous diode respectively LED negative pole and key switch S, the key switch S other end connects resistance R1 and diode D1 positive pole respectively, and resistance R1 is another One end connects resistance R2 and not gate F1 input respectively, and not gate F1 outfan connects mono-input of NAND gate F2, with non- Door another input of F2 connects diode D1 negative pole, resistance R3 and electric capacity C1 respectively, and the resistance R3 other end connects current potential Device RP1 one end, the potentiometer RP1 other end is just connecting the resistance R2 other end, potentiometer RP1 slide plate, diode D2 respectively Pole and the relay J coil other end ground connection.
As this utility model further scheme: described power supply VCC voltage is 9V.
Compared with prior art, the beneficial effects of the utility model are: this utility model timer circuit use not gate and with door Coordinating audion as controlling element, circuit structure is simple, low cost, and volume is little, and owing to not using chip component Controlling, capacity of resisting disturbance is strong.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of timer circuit.
Detailed description of the invention
Below in conjunction with the accompanying drawing in this utility model embodiment, the technical scheme in this utility model embodiment is carried out clearly Chu, it is fully described by, it is clear that described embodiment is only a part of embodiment of this utility model rather than whole Embodiment.Based on the embodiment in this utility model, those of ordinary skill in the art are not under making creative work premise The every other embodiment obtained, broadly falls into the scope of this utility model protection.
Referring to Fig. 1, in this utility model embodiment, a kind of timer circuit, including not gate F1, NAND gate F2, resistance R1, electric capacity C1, diode D1, LED and audion VT1, described audion VT1 emitter stage connects respectively LED positive pole and power supply VCC, audion VT1 colelctor electrode connects diode D2 negative pole and relay J line respectively Circle, audion VT1 base stage connects resistance R4, and the resistance R4 other end connects NAND gate F2 outfan and electric capacity C2 respectively, The electric capacity C2 other end connecting luminous diode LED negative pole and key switch S respectively, the key switch S other end connects electricity respectively Resistance R1 and diode D1 positive pole, the resistance R1 other end connects resistance R2 and not gate F1 input respectively, and not gate F1 exports End connects mono-input of NAND gate F2, and another input of NAND gate F2 connects diode D1 negative pole, resistance R3 respectively With electric capacity C1, the resistance R3 other end connect potentiometer RP1 one end, the potentiometer RP1 other end connect respectively resistance R2 another End, potentiometer RP1 slide plate, diode D2 positive pole and the relay J coil other end ground connection;Described power supply VCC voltage For 9V.
Operation principle of the present utility model is: refer to Fig. 1, and when S closes, C1 is charged rapidly, F1 output low level, F2 exports high level, and then, transistor VT1 ends, and relay J discharges, and after switch S opens, F1 and F2 overturns, Relay J adhesive, timing starts, and C1 starts extremely to discharge to R3, RP1, when on C1, voltage is down to F2 input threshold values electricity When pressure is following, F2 output becomes high level, and J discharges, and then timing terminates, and regulator potentiometer RP1 can regulate timing Time.
It is obvious to a person skilled in the art that this utility model is not limited to the details of above-mentioned one exemplary embodiment, Er Qie In the case of spirit or essential attributes of the present utility model, it is possible to realize this utility model in other specific forms. Therefore, no matter from the point of view of which point, all should regard embodiment as exemplary, and be nonrestrictive, this practicality is new The scope of type is limited by claims rather than described above, it is intended that by the containing of equivalency in claim that fall All changes in justice and scope are included in this utility model.Should not be considered as any reference in claim limiting Involved claim.
Although moreover, it will be appreciated that this specification is been described by according to embodiment, but the most each embodiment only comprises One independent technical scheme, this narrating mode of description is only the most for clarity sake, and those skilled in the art should be by Description is as an entirety, and the technical scheme in each embodiment can also be through appropriately combined, and forming those skilled in the art can With other embodiments understood.

Claims (2)

1. a timer circuit, including not gate F1, NAND gate F2, resistance R1, electric capacity C1, diode D1, luminescence two Pole pipe LED and audion VT1, it is characterised in that described audion VT1 emitter stage connecting luminous diode LED respectively is just Pole and power supply VCC, audion VT1 colelctor electrode connects diode D2 negative pole and relay J coil, audion VT1 base respectively Pole connects resistance R4, and the resistance R4 other end connects NAND gate F2 outfan and electric capacity C2 respectively, and the electric capacity C2 other end is respectively Connecting luminous diode LED negative pole and key switch S, the key switch S other end connects resistance R1 and diode D1 respectively Positive pole, the resistance R1 other end connects resistance R2 and not gate F1 input respectively, and not gate F1 outfan connects NAND gate F2 One input, another input of NAND gate F2 connects diode D1 negative pole, resistance R3 and electric capacity C1, resistance respectively The R3 other end connects potentiometer RP1 one end, and the potentiometer RP1 other end connects the resistance R2 other end, potentiometer RP1 respectively Slide plate, diode D2 positive pole and the relay J coil other end ground connection.
Timer circuit the most according to claim 1, it is characterised in that described power supply VCC voltage is 9V.
CN201620082715.0U 2016-01-27 2016-01-27 Timer circuit Expired - Fee Related CN205666812U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201620082715.0U CN205666812U (en) 2016-01-27 2016-01-27 Timer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201620082715.0U CN205666812U (en) 2016-01-27 2016-01-27 Timer circuit

Publications (1)

Publication Number Publication Date
CN205666812U true CN205666812U (en) 2016-10-26

Family

ID=57164113

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201620082715.0U Expired - Fee Related CN205666812U (en) 2016-01-27 2016-01-27 Timer circuit

Country Status (1)

Country Link
CN (1) CN205666812U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108199343A (en) * 2017-12-29 2018-06-22 河南北瑞电子科技有限公司 A kind of apparatus for protecting power supply

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108199343A (en) * 2017-12-29 2018-06-22 河南北瑞电子科技有限公司 A kind of apparatus for protecting power supply

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Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20161026

Termination date: 20170127