CN205666230U - Semiconductor structure - Google Patents

Abstract

The utility model provides a semiconductor structure, include: semiconductor substrate, semiconductor substrate has the device region and centers on the isolation region outside the device region, the isolation region surface has the first metal layer, first dielectric layer, first dielectric layer covers semiconductor substrate, and first dielectric layer has at least one first connector of being connected with the first metal layer, first connector is located the isolation region, first connector extend in the top of first dielectric layer, the contact mat, the contact mat covers the first dielectric layer of device region top, the second dielectric layer, second dielectric layer overlay contact pad and first connector, the protection rete, the protection rete covers the second dielectric layer and the part of device region the second dielectric layer of isolation region. The utility model discloses in, first connector makes the area of contact between second dielectric layer and the protection rete increase, and the second dielectric layer splits when avoiding the wafer test, improves the performance of wafer.

Description

Semiconductor structure

Technical field

This utility model relates to ic manufacturing technology field, particularly relates to a kind of semiconductor structure.

Background technology

During wafer is packaged, with reference to shown in Fig. 1, Semiconductor substrate 11 forms engagement pad 12, contact Pad 12 is as the exit of the device architecture in Semiconductor substrate 11.Then, engagement pad 12 formed dielectric layer 13 and have Machine film layer 14, for protecting the device architecture in wafer.

Generally after wafer level packaging completes, need wafer is detected, determine the yield of the product of encapsulation.Carry out The detection of wafer time, for example, it is desired to wafer to be repeated liter an operation for gentle cooling, one by one each performance of wafer is entered Row detection.However, it is found by the inventors that, easily there is fracture in the organic film 14 of the crystal column surface after test, thus affects The performance of wafer.

Utility model content

The purpose of this utility model is, it is provided that a kind of semiconductor structure, after solving wafer level packaging of the prior art The problem producing fracture.

For solving above-mentioned technical problem, this utility model provides a kind of semiconductor structure, including:

Semiconductor substrate, described Semiconductor substrate has device region and is centered around the isolation area outside described device region, institute State surface, isolation area and there is the first metal layer；

First medium layer, described first medium layer covers described Semiconductor substrate, and described first medium layer has and institute Stating at least one first connector that the first metal layer connects, described first connector is positioned on described isolation area, described first connector Extend the top of described first medium layer；

Engagement pad, described engagement pad covers the first medium layer above described device region；

Second dielectric layer, described second dielectric layer covers described engagement pad and described first connector；

Protecting film layer, described protecting film layer covers the of the second dielectric layer of described device region and the described isolation area of part Second medium layer.

Optionally, the height of described first connector above described first medium layer and the thickness phase of described engagement pad it are positioned at With.

Optionally, the thickness of described engagement pad is 1 μm～3 μm.

Optionally, the width of described first connector is 1 μm～2 μm.

Optionally, described first medium layer includes 2～5 described first connectors.

Optionally, the thickness of described first medium layer is 0.5 μm～1 μm.

Optionally, described Semiconductor substrate also includes the protection ring being centered around outside described isolation area, described the first metal layer Extend in described protection ring.

Optionally, also having the second connector in described first medium layer, described second connector is positioned on described protection ring, and And described second connector is connected with described the first metal layer, described second connector extends to the top of described first medium layer.

Optionally, the height of described second connector being positioned on described first medium layer and the thickness phase of described engagement pad With.

Optionally, the width of described second connector is 1 μm～2 μm.

Optionally, the thickness of described second dielectric layer is 0.5 μm～1 μm.

Optionally, thickness 10 μm of described protecting film layer～20 μm.

Compared with prior art, the semiconductor structure that this utility model provides, outside device region, form isolation area, isolation area First medium layer and second dielectric layer between form the first connector, the first connector is supported by the first metal layer, and extends The top of one dielectric layer, adds the height of second dielectric layer above the first connector so that the second dielectric layer of formation and guarantor Contact area between cuticular layer increases, thus is carrying out wafer sort, and stress is difficult to discharge, and second dielectric layer will not be formed disconnected Split.Semiconductor structure in this utility model, it can be avoided that form fracture after Feng Zhuan, improves the performance of wafer.

Accompanying drawing explanation

Fig. 1 is the cross-sectional view of wafer level packaging in prior art；

Fig. 2 is the top view forming the first connector in this utility model one embodiment；

Fig. 3 is the cross-sectional view of semiconductor structure in this utility model one embodiment；

Fig. 4 is the top view forming protecting film layer in this utility model one embodiment.

Detailed description of the invention

Below in conjunction with schematic diagram, semiconductor structure of the present utility model is described in more detail, which show this The preferred embodiment of utility model, it should be appreciated that those skilled in the art can revise this utility model described here, and still So realize advantageous effects of the present utility model.Therefore, what description below was appreciated that for those skilled in the art is extensive Know, and be not intended as restriction of the present utility model.

In the introduction it has been already mentioned that the organic film 14 of rear surface that wafer after Feng Zhuan carries out testing occurs disconnected Split.With reference to shown in Fig. 1, inventor is through constantly test and analyzes, and finds dielectric layer 13 (figure at the step of engagement pad 12 Middle S region) easily rupture, the fracture of dielectric layer 13 thus cause the fracture of organic film 14, and then affect the performance of wafer.

To this end, this utility model provides a kind of semiconductor structure, outside device region, form isolation area, first Jie of isolation area Forming the first connector between matter layer and second dielectric layer, the first connector extends the top of first medium layer, adds first and inserts The height of the second dielectric layer of side beyond the Great Wall so that the contact area between second dielectric layer and the protecting film layer of formation increases, from And carrying out wafer sort, stress is difficult to discharge, and second dielectric layer will not form fracture.Semiconductor structure in this utility model It can be avoided that form fracture after Feng Zhuan, improve the performance of wafer.

Below in conjunction with Fig. 2～Fig. 4, semiconductor structure of the present utility model is specifically described.Should be appreciated that, although Term " first ", " second " and " the 3rd " etc. can be used herein to describe each technological parameter or element, such as, metal level, insert Plug etc., but these technological parameters or element should not be limited by these terms.These terms are only used for distinguishing a technological parameter Or element and other technological parameter or element.Therefore, in the case of the enlightenment of the disclosure, can be by discussed below Second metal level, the second connector are referred to as the first metal layer, the first connector.

Shown in Fig. 2 and Fig. 3, Fig. 2 is the top view that semiconductor structure of the present utility model forms the first connector, Fig. 2 Cross-sectional view for semiconductor structure.The semiconductor structure that this utility model provides includes Semiconductor substrate 100, described Semiconductor substrate 100 has device region 10, be centered around outside described device region 10 isolation area 20 (device region 10 and dotted line frame in figure Corresponding region) and the protection ring 30 (region outside dotted line frame in figure) that is centered around outside described isolation area 20.In the present embodiment, Surface, described isolation area 20 has the first metal layer 110, and described the first metal layer 110 also extends in described protection ring 30, institute State the first metal layer 110 and be positioned at isolation area 20 and protection ring 30 simultaneously, for follow-up support the first connector and the second connector.This Outward, described device region 10 surface has the second metal level 120, between described second metal level 120 and described the first metal layer 110 Insulation.

Afterwards, forming first medium layer 200 on a semiconductor substrate 100, described first medium layer 200 includes being formed at institute State first silicon nitride layer the 210, the oneth TEOS layer the 220, second silicon nitride layer 230 and the 2nd TEOS in Semiconductor substrate 100 Layer 240, wherein, the thickness of the first silicon nitride layer 210 is 50nm～100nm, the thickness of a TEOS layer 220 be 200nm～ 500nm, the thickness of the second silicon nitride layer 230 is 50nm～100nm, and the thickness of the 2nd TEOS layer 240 is 200nm～500nm.? In the present embodiment, described first medium layer 200 has multiple first connectors 310 being connected with described the first metal layer 110, institute Stating the first connector 310 to be positioned on described isolation area, described first connector 310 extends the top of described first medium layer 200, and On described first medium layer 200 above described device region 10, there is engagement pad 300.Wherein, the width of described first connector 310 It is 1 μm～2 μm.The thickness of described first medium layer 200 is 0.5 μm～1 μm.With shape in first medium layer 200 in the present embodiment Illustrate as a example by becoming two the first connectors 310, in other embodiments of the present utility model, described first connector 310 Number can also be 1,3,4 etc., this is not limited by this utility model.

It should be noted that the height being positioned at described first connector 310 above described first medium layer 200 connects with described The thickness of touch pad 300 is identical.The thickness of described engagement pad 300 is 1 μm～3 μm, thus the first connector 310 is positioned at first medium layer Height above in the of 200 is 1 μm～3 μm, for increasing the contact area of follow-up second dielectric layer and protecting film layer.Certainly, first The thickness depending highly on first medium layer 200 of connector 310, the first connector 310 is positioned at the height above first medium layer 200 Fixed with the variable thickness of engagement pad 300 identical, this is not limited by this utility model.

Be positioned in described protection ring 30 additionally, described first medium layer 200 also has, and with described the first metal layer 110 the second connectors 320 connected, same, described second connector 320 extends to the top of described first medium layer 200.Its In, the width of described second connector 320 is 1 μm～2 μm, and, described second connector being positioned on described first medium layer 200 The height of 320 is identical with the thickness of described engagement pad 300.Certainly, the second connector 320 depend highly on first medium layer 200 Thickness, it is fixed with the variable thickness of engagement pad 300 the most identical that the second connector 320 is positioned at height above first medium layer 200, this reality With novel, this is not limited.

Shown in Fig. 3 and Fig. 4, Fig. 4 is the schematic diagram forming the semiconductor structure after protecting film layer.Described partly lead Body structure also includes that second dielectric layer 400, described second dielectric layer 400 cover described engagement pad 300, described first connector 310 And described second connector 320.In the present embodiment, the thickness of described second dielectric layer 400 is 0.5 μm～1 μm, wherein, institute State second dielectric layer 400 and include being sequentially located at the 3rd TEOS layer in described engagement pad 300 and the 3rd silicon nitride layer (in figure the most not Illustrate), the thickness of the 3rd TEOS layer is 200nm～500nm, and the thickness of the 3rd silicon nitride layer is 500～1000nm.

Further, described semiconductor structure also includes that protecting film layer 500, described protecting film layer 500 cover described device The second dielectric layer 400 in district 10 and the second dielectric layer 400 of the described isolation area of part 20.Described protecting film layer 500 is polyamides Imines film or other organic films, thickness 10 μm of described protecting film layer 500～20 μm.It should be noted that the first connector 310 Extend the top of first medium layer 200, add the height of second dielectric layer 400 above the first connector 310 so that formed Second dielectric layer 400 and protecting film layer 500 between contact area increase, thus carrying out wafer sort, second dielectric layer Stress in 400 is difficult to discharge, and second dielectric layer 400 will not form fracture, and protecting film layer 500 also would not produce fracture, from And improve the performance of wafer.

In sum, the semiconductor structure that this utility model provides, outside device region, form isolation area, the first of isolation area Forming the first connector between dielectric layer and second dielectric layer, the first connector extends the top of first medium layer, adds first The height of the second dielectric layer above connector so that the contact area between second dielectric layer and the protecting film layer of formation increases, Thus carrying out wafer sort, stress is difficult to discharge, and second dielectric layer will not form fracture.Semiconductor junction in this utility model Structure, it can be avoided that form fracture after Feng Zhuan, improves the performance of wafer.

Obviously, those skilled in the art can carry out various change and modification without deviating from this practicality to this utility model Novel spirit and scope.So, if of the present utility model these amendment and modification belong to this utility model claim and Within the scope of its equivalent technologies, then this utility model is also intended to comprise these change and modification.

Claims (12)

1. a semiconductor structure, it is characterised in that including:

Semiconductor substrate, described Semiconductor substrate has device region and is centered around the isolation area outside described device region, described every From surface, district, there is the first metal layer；

First medium layer, described first medium layer cover described Semiconductor substrate, and described first medium layer have and described the At least one first connector that one metal level connects, described first connector is positioned on described isolation area, and described first connector extends Top in described first medium layer；

Engagement pad, described engagement pad covers the first medium layer above described device region；

Second dielectric layer, described second dielectric layer covers described engagement pad and described first connector；

Protecting film layer, described protecting film layer covers the second dielectric layer of described device region and second Jie of the described isolation area of part Matter layer.

2. semiconductor structure as claimed in claim 1, it is characterised in that be positioned at described first above described first medium layer The height of connector is identical with the thickness of described engagement pad.

3. semiconductor structure as claimed in claim 2, it is characterised in that the thickness of described engagement pad is 1 μm～3 μm.

4. semiconductor structure as claimed in claim 1, it is characterised in that the width of described first connector is 1 μm～2 μm.

5. semiconductor structure as claimed in claim 1, it is characterised in that described first medium layer includes 2～5 described the One connector.

6. semiconductor structure as claimed in claim 1, it is characterised in that the thickness of described first medium layer is 0.5 μm～1 μ m。

7. semiconductor structure as claimed in claim 1, it is characterised in that described Semiconductor substrate also include being centered around described every Protection ring outside district, described the first metal layer extends in described protection ring.

8. semiconductor structure as claimed in claim 7, it is characterised in that in described first medium layer, also there is the second connector, Described second connector is positioned on described protection ring, and described second connector is connected with described the first metal layer, and described second inserts Plug extends to the top of described first medium layer.

9. semiconductor structure as claimed in claim 8, it is characterised in that be positioned at described second on described first medium layer and insert The height of plug is identical with the thickness of described engagement pad.

10. semiconductor structure as claimed in claim 8, it is characterised in that the width of described second connector is 1 μm～2 μm.

11. semiconductor structures as claimed in claim 1, it is characterised in that the thickness of described second dielectric layer is 0.5 μm～1 μ m。

12. semiconductor structures as claimed in claim 1, it is characterised in that thickness 10 μm of described protecting film layer～20 μm.