CN205647440U - Edge combination formula digital frequency multiplier based on transformer on piece - Google Patents
Edge combination formula digital frequency multiplier based on transformer on piece Download PDFInfo
- Publication number
- CN205647440U CN205647440U CN201620364588.3U CN201620364588U CN205647440U CN 205647440 U CN205647440 U CN 205647440U CN 201620364588 U CN201620364588 U CN 201620364588U CN 205647440 U CN205647440 U CN 205647440U
- Authority
- CN
- China
- Prior art keywords
- transistor
- edge
- signal
- transformer
- chip transformer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
Links
Landscapes
- Amplifiers (AREA)
Abstract
The utility model provides an edge combination formula digital frequency multiplier based on transformer on piece, relates to the digital frequency multiplier. Be equipped with first, the marginal combiner of second and go up the duopole laod network of transformer based on the piece, it is first, the incoming signal of two marginal combiners is 360/2n's signal make -up by a 2n phase difference, the primary one end and the input capacitance top crown of transformer on the first marginal combiner output connection piece, the primary other end and the input capacitance bottom crown of transformer on the second edge combiner output connection piece, the primary intermediate node of transformer meets the power supply voltage of the first and second marginal combiners or whole edge combination formula digital frequency multiplier based on transformer on piece's power supply voltage on the piece, output capacitance's top crown is connected as output signal's positive pole to the secondary coil one end of transformer on the piece, and the secondary coil other end connection output capacitance's of transformer bottom crown is as output signal's negative pole on the piece, the secondary coil intermediate node ground connection of transformer on the piece.
Description
Technical field
This utility model relates to digital frequency multiplier, especially relates to a kind of edge based on on-chip transformer combined type digital doubler.
Background technology
Along with modern semiconductors industry high speed development, the digital CMOS process of deep-submicron constantly to less size evolution,
From 90nm to 65nm, it is followed by 40nm, 28nm ..., the processing cost of cellar area silicon chip still can be maintained at when volume production
About 0.1~0.2 U.S. dollar/mm2;And for integrated circuit, the most adjoint is less chip size, work faster
Speed and lower power consumption.Hence benefit from developing rapidly of modern advanced semiconductor technology, be no matter consumer electronics product,
Mobile phone, bluetooth module, or radar detection, satellite communication, industrial department and consumer can obtain with lower cost
Obtain more preferably functional experience.
But, in the tide that the digital CMOS process of deep-submicron develops rapidly, RF/Microwave based on traditional analog technology/
Millimetre integrated circuit still depends on SiGe BiCMOS, RF CMOS or GaAs technique, i.e. for substrate, transistor and
Metal thickness etc. propose higher requirement, and therefore for digital circuit, the with high costs of radio-frequency front-end transceiver is permitted
Many;Simultaneously as radio-frequency front-end and digital baseband are both needed to use the result of different semiconductor technology, cause radio frequency/simulation/number
Word circuit SOC (SOC(system on a chip)) system level chip slower development.Therefore, digital technology is used to design RF/Microwave/millimeter
Ripple integrated circuit is to reduce one of radio-frequency front-end transceiver cost and the effective way improving on-chip system chip integrated level.
The structured flowchart of traditional edge combination type (Edge Combining) digital frequency multiplier is as it is shown in figure 1, this circuit is by limit
Edge combiner (EC1, EC2) and load (Z1, Z2) composition, 2n input signal is 360 °/2n by 2n phase contrast
Cyclical signal composition (n is even number natural number).Fig. 2 is an example of conventional edge combined type digital doubler, at this
In doubler input signal be n group phase contrast be the Difference signal pair (altogether 2n phase place) of 180 °/n, wherein n be even number oneself
So number.For statement convenient be 0 °, 180 ° × 1/n, 180 ° × 2/n phase place the most here ..., 180 ° × (2n-1)/n, 360
° signal in order be referred to as p0、p1、…、p2n-1, wherein pn+iWith pi(i=1,2 ...) phase contrast is 180 °.Such as Fig. 2 institute
Showing, edge combiner modules (can also be PMOS, Bipolar etc. by 2n group cascade (Cascode) nmos pass transistor
The transistor of type) N1cs,0~N1cs,n-1、N2cs,0~N2cs,n-1And N1cg,0~N1cg,n-1、N2cg,0~N2cg,n-1Composition, inductance L1
And L2For circuit load.Only when connecting two signals of nmos pass transistor of series connection and being high level simultaneously, this branch road just has electricity
Stream, and outfan is pulled down to low level.Therefore, it is connected to EC doubler by 2n signal is carried out regular arrangement
In, allow each Tin/n(TinCycle for input signal) time period in only one of which branch road conducting and drop-down for outfan current potential
To low level, concrete waveform diagram is as shown in Figure 3.As a result, can obtain the cycle at outfan is TinThe signal of/n, the most defeated
Going out signal frequency is n times of frequency input signal, the circuit realiration effect of n frequency multiplication ([1] Hong-Yi Huang and
Jian-Hong Shen,"A DLL-based programmable clock generator using threshold-trigger
delay element and circular edge combiner,"IEEE Asia-Pacific Conference on Advanced
System Integrated Circuits(AP-ASIC2004),pp.76-79,Aug.2004;[2]M.Gholami,M.
Sharifkhani and M.Hashemi,"a novel parallel architecture for low voltage-low power
dll-based frequency multiplier,"IEEE 6th International Conference on Design&
Technology of Integrated Systems in Nanoscale Era(DTIS),2011)。
Assuming that input signal is square wave, and do not have noise, the electric current now flowing through each load in EC doubler can be decomposed into
N current pulse signal, as shown in Figure 4.Owing to each signal is periodically pulsing signal, the most each signal can be by Fu
Vertical leaf-size class number represents.For the sake of to simplify the analysis, it will be assumed that the level conversion of the input/output signal of EC doubler is all preferable
, i.e. rise/fall time is 0.First signal I after decomposing with outfanout,0As a example by, the coefficient of its fourier series
It is represented by ([3] F.-R.Liao, S.-S.Lu, " A waveform-dependent phase-noise analysis for
edge-combining DLL frequency multipliers,"IEEE Trans.on Microwave Theory and
Techniques, vol.60, no.4, pp.1086-1096, Apr.2012):
Wherein, I0For the current amplitude of output signal flow overload impedance, ωinFor input signal angular frequency, k is harmonic number.So Iec,1(t)
It is represented by
Similarly, other components of output current signal can also obtain in the same way.As can be seen here, output current signal
Can be expressed as:
Wherein, AkFor:
The load impedance assuming EC doubler is Z0(L1=L2=Z0), then the amplitude of output voltage signal is:
Lose without phase error, Duty Cycle Distortion (Duty Cycle Distortion, DCD) and signal rise/fall time
Joining, formula (4) can be reduced to:
Wherein l is integer.Formula (6) represents that the EC output signal frequency after synthesizing is N times of frequency input signal, and not input
The h order harmonic components of signal, wherein h is the natural number being not equal to l × N (l is integer), and output desired voltage amplitude is 2
(I0/2π)×Z0。
But, when between input n group differential signal, there is phase error and signal itself exist Duty Cycle Distortion, signal rising/
When there is mismatch in fall time, A in formula (4)kIt is no longer equal to zero when k ≠ l × N, therefore introduces each harmonic at outfan
Component, and Duty Cycle Distortion degree and the rise/fall time mismatch of its size and phase error size and signal itself have
Close.Due to the existence of harmonic component, the performance of radio frequency/microwave/millimeter wave front end transceiver system is caused the most severe shadow
Ringing, as in narrow-band receiver, harmonic component will increase the noise level of adjacency channel, reduces the sensitivity of transceiver;Micro-
In ripple/millimeter wave transceiver system, harmonic component is crossed senior general and is destroyed in international norm the requirement to harmonic component peak power output.
There is the load of filter function to suppress the harmonic component that some are unnecessary, such as ([4] O. such as inductive loads it is then desired to use
Casha,et.al,"Analysis of the spur characteristics of edge-combining DLL-based
frequency multiplier,"IEEE Trans.on Circuits and Systems II,vol.56,no.2,pp.
132-136,Feb.2009;[5]A.Ojani,et.al,"Modeling and analysis of harmonic spurs
in DLL-based frequency multiplier,"IEEE Trans.on Circuits and Systems I,vol.61,
no.11,pp.3075-3084,Nov.2014)。
Planar integration inductance based on silicon substrate is due to the characteristic of itself, and quality factor is the highest, thus when as circuit load its
Filter capacity is limited, is used especially in edge combined type digital doubler, and single inductance or simple inductance capacitance network are very
Difficult effectively suppression is harmonic signal produced by the imperfection of input signal and the transistor mismatch of EC circuit own.
Summary of the invention
The purpose of this utility model is the problems referred to above existed for existing edge combined type digital doubler, it is provided that one is adopted
There is with on-chip transformer laod network composition the loaded impedance network of two pairs of conjugate poles, conventional edge combined type digital can be improved
The filtering performance of doubler and bandwidth performance, have edge based on the on-chip transformer combination type of broadband, higher harmonics suppression function
Digital frequency multiplier.
This utility model is provided with the first edge combiner, the second edge combiner, duopole laod network based on on-chip transformer;
The input signal of described first edge combiner and the second edge combiner is by the signal that 2n phase contrast is 360 °/2n
Composition, primary coil one end of the outfan connection on-chip transformer of the first edge combiner and the top crown of input capacitance, second
The outfan of edge combiner connects the other end and the bottom crown of input capacitance, the on-chip transformer of the primary coil of on-chip transformer
Primary coil intermediate node connect the first edge combiner and the supply voltage of the second edge combiner or whole based on on-chip transformer
The supply voltage of edge combined type digital doubler;Secondary coil one end of on-chip transformer connects the top crown of output capacitance and makees
For the positive pole of output signal, the secondary coil other end of on-chip transformer connects bottom crown the bearing as output signal of output capacitance
Pole;The secondary coil intermediate node ground connection of on-chip transformer or connect the bias voltage of next stage circuit module or unsettled.
Described edge combiner can be made up of 2n group transistor, and circuit load part is by differential transformers on sheet, input capacitance and defeated
Going out electric capacity composition, n is even number natural number, and described transistor uses cascade nmos pass transistor, cascade PMOS crystal
One in pipe, cascade Bipolar transistor;Differential transformers primary coil intermediate node connects supply voltage, in order to give
Whole edge based on on-chip transformer combined type digital doubler is powered, secondary coil intermediate node ground connection or connect next stage circuit
Bias voltage or unsettled;In the first edge combiner, transistor N1cs,iSource ground, i=0,1 ... (n-1), crystal
Pipe N1cs,iDrain electrode connect transistor N1cg,iSource electrode, i=0,1 ... (n-1), transistor N1cs,iGrid connect signal pn+1+2 ×i, wherein i=0,1 ... (n/2-1);When i is more than (n/2-1), transistor N1cs,iGrid connect signal p1+2×i-n, wherein
I=n/2, (n/2+1) ... (n-1);Transistor N1cg,iGrid [i=0,1 ... (n-1)] connect signal p respectively2×i, wherein i=0,
1…(n-1);Transistor N1cg,iDrain electrode [i=0,1 ... (n-1)] jointly connect on-chip transformer primary coil one end and
The top crown of input capacitance;In the second edge combiner, transistor N2cs,iSource ground [i=0,1 ... (n-1)], brilliant
Body pipe N2cs,iDrain electrode connect transistor N2cg,iSource electrode [i=0,1 ... (n-1)], transistor N2cs,iGrid connect signal
pn+2+2×i, wherein i=0,1 ... (n/2-2);When i is more than n/2-2, transistor N2cs,iGrid connect signal p2×i-n+2, its
Middle i=n/2-1, n/2+1 ... (n-1);Transistor N2cg,iGrid [i=0,1 ... (n-1)] connect signal p respectively2×i+1, wherein
I=0,1 ... (n-1);Transistor N2cg,iDrain electrode [i=0,1 ... (n-1)] jointly connect primary coil another of on-chip transformer
One end and the bottom crown of input capacitance;The supply voltage or whole of the primary coil intermediate node edge fit edge combiner of on-chip transformer
The supply voltage of doubler;One end of the secondary coil of on-chip transformer as output signal is just connecting the top crown of output capacitance
Pole, the other end of the secondary coil of on-chip transformer connects the bottom crown negative pole as output signal of output capacitance;Transformation on sheet
The secondary coil intermediate node of device can ground connection or connect the bias voltage of next stage circuit module or unsettled.
Loaded impedance network of the present utility model and traditional frequency response of inductive impedance network, bandwidth and filtering performance contrast.
Due to the mismatch reason of transistor in the imperfection of input signal and edge combinational logic circuit, cause in output electric current Iec and remove
Desired outside the current signal of N × Fin Frequency point, there is also the harmonic signal of numerous input signal Fin, the most maximum humorous
Ripple is positioned near N × Fin frequency, such as (N ± 1) Fin, (N ± 2) Fin equifrequent point.Traditional with inductance for load
In edge combined type digital doubler, when being used in narrowband systems, the harmonic signal of Fin may fall in adjacent channel, carries
The noise level of high adjacent channel, reduces the sensitivity of adjacent channel;When being used in broadband system, in harmonic component distance bandwidth
Lower limit is too near, to such an extent as to the suppression to harmonic wave is extremely limited, simultaneously because inductive load is one-pole system, and can only be outside passband
Producing the harmonic inhibition capability of-20dB/dec, therefore the suppression to harmonic wave is limited.Such as the transformation carried according to this utility model
Device and the laod network system of electric capacity composition, will produce two to conjugate pole at load end, due to can be by designing transformation on sheet
Device is chosen different Lp, Ls and Cp, the values of Cs and designs mutual inductance value M of different transformators so that limit fp and fn position
In the both sides of required frequency N × Fin, it is possible not only to obtain stable broadband character, it is also possible to produce and filter outside the band of-40dB/dec
Ripple performance, can more efficiently suppress the harmonic signal of N × Fin adnexa.Simultaneously can also be by adjusting fp and fn limit
Position adjusts the size of pass band width, can obtain bandwidth more broader than traditional doubler.
Accompanying drawing explanation
Fig. 1 is traditional edge combination type doubler structured flowchart.
The edge combination type doubler that Fig. 2 is traditional realizes circuit diagram.
Fig. 3 is edge combined type digital doubler operation principle waveform diagram.
Fig. 4 is that the output of edge combined type digital doubler is decomposed into series of periodic pulse signal.
Fig. 5 is the circuit composition schematic diagram of this utility model embodiment.
Fig. 6 is one of implementation of this utility model embodiment.
Fig. 7 is load end one side of something small-signal equivalent circuit figure of this utility model embodiment.
Fig. 8 is laod network and traditional frequency response of inductive load network, bandwidth, the filtering of this utility model embodiment
Can contrast.
Detailed description of the invention
This utility model will be further described by following example in conjunction with accompanying drawing.
As it is shown in figure 5, this utility model be provided with the first edge combiner EC1, the second edge combiner EC2, based on transformation on sheet
The duopole laod network G of device;
The input signal of described first edge combiner EC1 and the second edge combiner EC2 is 360 °/2n by 2n phase contrast
Signal composition, the outfan of the first edge combiner EC1 connects primary coil one end of on-chip transformer and input capacitance Cp
Top crown, the outfan of the second edge combiner EC2 connects the other end of the primary coil of on-chip transformer and input capacitance Cp
Bottom crown, the primary coil intermediate node CTP of on-chip transformer meets the first edge combiner EC1 and the second edge combiner EC2
Supply voltage or the supply voltage of whole edge based on on-chip transformer combined type digital doubler;The secondary of on-chip transformer
Coil one end connects the top crown of output capacitance Cs as the positive pole of output signal Vout, the secondary coil of on-chip transformer another
End connects the bottom crown negative pole as output signal Vout of output capacitance Cs;The secondary coil intermediate node CTS of on-chip transformer
Ground connection or connect the bias voltage of next stage circuit module or unsettled.
It is illustrated in figure 6 the circuit diagram of one of the implementation of doubler that this utility model carried, described edge combiner
Can be by 2n group transistor N1cs,0~N1cs,n-1、N2cs,0~N2cs,n-1And N1cg,0~N1cg,n-1、N2cg,0~N2cg,n-1Composition, circuit is born
Carry part by differential transformers on sheet and electric capacity Cp、CsComposition, n is even number natural number, and described transistor can use cascade
One in nmos pass transistor, cascade PMOS transistor, cascade Bipolar transistor etc..At the beginning of differential transformers
Level coil intermediate node CTP can connect supply voltage etc. in order to supply to whole edge based on on-chip transformer combined type digital doubler
Electricity, secondary coil intermediate node CTS can ground connection or connect the bias voltage of next stage circuit or unsettled.At the first edge combiner EC1
In, transistor N1cs,iSource ground [i=0,1 ... (n-1)], transistor N1cs,iDrain electrode connect transistor N1cg,iSource electrode
[i=0,1 ... (n-1)], transistor N1cs,iGrid connect signal pn+1+2×i, wherein i=0,1 ... (n/2-1);When i is more than
(n/2-1) time, transistor N1cs,iGrid connect signal p1+2×i-n, wherein i=n/2, (n/2+1) ... (n-1);Transistor N1cg,i
Grid [i=0,1 ... (n-1)] connect signal p respectively2×i, wherein i=0,1 ... (n-1);Transistor N1cg,iDrain electrode [i=0,
1 ... (n-1)] one end and the top crown of input capacitance Cp of the primary coil of on-chip transformer are jointly connected.In the second edge group
In clutch EC2, transistor N2cs,iSource ground [i=0,1 ... (n-1)], transistor N2cs,iDrain electrode connect transistor N2cg,i
Source electrode [i=0,1 ... (n-1)], transistor N2cs,iGrid connect signal pn+2+2×i, wherein i=0,1 ... (n/2-2);When
When i is more than n/2-2, transistor N2cs,iGrid connect signal p2×i-n+2, wherein i=n/2-1, n/2+1 ... (n-1);Crystal
Pipe N2cg,iGrid [i=0,1 ... (n-1)] connect signal p respectively2×i+1, wherein i=0,1 ... (n-1);Transistor N2cg,i's
Drain electrode [i=0,1 ... (n-1)] connects the other end and the bottom crown of input capacitance Cp of the primary coil of on-chip transformer jointly.
The supply voltage of the primary coil intermediate node CTP edge fit edge combiner of on-chip transformer or the supply voltage of whole doubler;Sheet
One end of the secondary coil of upper transformator connects the top crown positive pole as output signal Vout of output capacitance Cs, transformation on sheet
The other end of the secondary coil of device connects the bottom crown negative pole as output signal Vout of output capacitance Cs;On-chip transformer
Secondary coil intermediate node CTS can ground connection or connect the bias voltage of next stage circuit module or unsettled.
Load end one side of something small-signal equivalent circuit figure of the present utility model as it is shown in fig. 7, wherein Iec be the output of edge combiner
Electric current, is represented by formula (3), Lp is primary inductance, and Rp is the equivalent parasitic resistance of primary inductance, and Cp is
Being connected on the input capacitance at transformer two ends, Ls is the inductance of transformer secondary coil, and Rs is transformer secondary output inductance
Equivalent parasitic resistance, Cs is the output capacitance being connected on transformer secondary coil two ends, and M is the mutual inductance value of transformator.Vout is for becoming
The output voltage of depressor secondary coil, is also the output voltage of whole EC doubler simultaneously.By the small-signal equivalent circuit figure of Fig. 7,
Can obtain the expression formula of Vout:
By formula (7) it will be seen that the expression formula of Vout has two pairs of conjugate poles:
With
Fig. 8 show loaded impedance network of the present utility model and the traditional frequency response of inductive impedance network, bandwidth and filtering
(in fig. 8, labelling A is the loaded impedance network frequency response of this utility model embodiment to performance comparison, and B is traditional bearing
Carrying impedance network frequency response, C is output signal amplitude).Due in the imperfection of input signal and edge combinational logic circuit
The mismatch reason of transistor, cause output electric current Iec in except desired in addition to the current signal of N × Fin Frequency point, there is also
The harmonic signal of numerous input signals Fin, wherein maximum harmonic wave is positioned near N × Fin frequency, such as (N ± 1) Fin, (N ± 2)
Fin equifrequent point.Traditional with inductance for the EC doubler of load in, when being used in narrowband systems, the harmonic signal of Fin
May fall in adjacent channel, improve the noise level of adjacent channel, reduce the sensitivity of adjacent channel;When being used in broadband system
During system, harmonic component distance bandwidth bound is too near, to such an extent as to the suppression to harmonic wave is extremely limited, simultaneously because inductive load is
One-pole system, can only produce the harmonic inhibition capability of-20dB/dec outside passband, and therefore the suppression to harmonic wave is limited.If
Use the transformator that put forward of this utility model and the laod network system of electric capacity composition, will produce two to conjugate pole at load end,
Owing to different Lp, Ls and Cp, the values of Cs can be chosen by design on-chip transformer and design different transformator mutual inductances
Value M so that limit fp and fn are positioned at the both sides of required frequency N × Fin, are possible not only to obtain stable broadband character, also may be used
To produce the outer filtering performance of the band of-40dB/dec, can more efficiently suppress the harmonic signal of N × Fin adnexa.The most also may be used
To adjust the size of pass band width by adjusting the position of fp and fn limit, bandwidth more broader than traditional doubler can be obtained.
Claims (2)
1. edge based on an on-chip transformer combined type digital doubler, it is characterised in that be provided with the first edge combiner,
Two edge combiners, duopole laod network based on on-chip transformer;
The input signal of described first edge combiner and the second edge combiner is by the signal that 2n phase contrast is 360 °/2n
Composition, primary coil one end of the outfan connection on-chip transformer of the first edge combiner and the top crown of input capacitance, second
The outfan of edge combiner connects the other end and the bottom crown of input capacitance, the on-chip transformer of the primary coil of on-chip transformer
Primary coil intermediate node connect the first edge combiner and the supply voltage of the second edge combiner or whole based on on-chip transformer
The supply voltage of edge combined type digital doubler;Secondary coil one end of on-chip transformer connects the top crown of output capacitance and makees
For the positive pole of output signal, the secondary coil other end of on-chip transformer connects bottom crown the bearing as output signal of output capacitance
Pole;The secondary coil intermediate node ground connection of on-chip transformer.
A kind of edge based on on-chip transformer combined type digital doubler, it is characterised in that described limit
Edge combiner is made up of 2n group transistor, and circuit load part is made up of differential transformers, input and output capacitors on sheet,
N is even number natural number, and described transistor uses cascade nmos pass transistor, cascade PMOS transistor, cascade
One in Bipolar transistor;Differential transformers primary coil intermediate node connects supply voltage, in order to whole based on sheet
The edge combined type digital doubler of transformator is powered, secondary coil intermediate node ground connection or connect next stage circuit bias voltage or
Unsettled;In the first edge combiner, transistor N1cs,iSource ground, i=0,1 ... (n-1), transistor N1cs,iDrain electrode
Connect transistor N1cg,iSource electrode, i=0,1 ... (n-1), transistor N1cs,iGrid connect signal pn+1+2×i, wherein i=0,1 ...
(n/2-1);When i is more than (n/2-1), transistor N1cs,iGrid connect signal p1+2×i-n, wherein i=n/2, (n/2+1) ...
(n-1);Transistor N1cg,iGrid [i=0,1 ... (n-1)] connect signal p respectively2×i, wherein i=0,1 ... (n-1);Brilliant
Body pipe N1cg,iDrain electrode [i=0,1 ... (n-1)] jointly connect one end of primary coil of on-chip transformer and the upper of input capacitance
Pole plate;In the second edge combiner, transistor N2cs,iSource ground [i=0,1 ... (n-1)], transistor N2cs,iLeakage
Pole connects transistor N2cg,iSource electrode [i=0,1 ... (n-1)], transistor N2cs,iGrid connect signal pn+2+2×i, wherein i=0,
1…(n/2-2);When i is more than n/2-2, transistor N2cs,iGrid connect signal p2×i-n+2, wherein i=n/2-1, n/2+1 ...
(n-1);Transistor N2cg,iGrid [i=0,1 ... (n-1)] connect signal p respectively2×i+1, wherein i=0,1 ... (n-1);Brilliant
Body pipe N2cg,iDrain electrode [i=0,1 ... (n-1)] jointly connect the other end of primary coil of on-chip transformer and input capacitance
Bottom crown;The supply voltage of the primary coil intermediate node edge fit edge combiner of on-chip transformer or the supply voltage of whole doubler;
One end of the secondary coil of on-chip transformer connects the top crown positive pole as output signal of output capacitance, on-chip transformer time
The other end of level coil connects the bottom crown negative pole as output signal of output capacitance;The secondary coil middle node of on-chip transformer
Put ground connection or connect the bias voltage of next stage circuit module or unsettled.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201620364588.3U CN205647440U (en) | 2016-04-27 | 2016-04-27 | Edge combination formula digital frequency multiplier based on transformer on piece |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201620364588.3U CN205647440U (en) | 2016-04-27 | 2016-04-27 | Edge combination formula digital frequency multiplier based on transformer on piece |
Publications (1)
Publication Number | Publication Date |
---|---|
CN205647440U true CN205647440U (en) | 2016-10-12 |
Family
ID=57060292
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201620364588.3U Withdrawn - After Issue CN205647440U (en) | 2016-04-27 | 2016-04-27 | Edge combination formula digital frequency multiplier based on transformer on piece |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN205647440U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105897170A (en) * | 2016-04-27 | 2016-08-24 | 加驰(厦门)微电子技术有限公司 | Edge combined digital frequency multiplier based on on-chip transformer |
-
2016
- 2016-04-27 CN CN201620364588.3U patent/CN205647440U/en not_active Withdrawn - After Issue
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105897170A (en) * | 2016-04-27 | 2016-08-24 | 加驰(厦门)微电子技术有限公司 | Edge combined digital frequency multiplier based on on-chip transformer |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Guan et al. | Low-power-consumption and high-gain CMOS distributed amplifiers using cascade of inductively coupled common-source gain cells for UWB systems | |
CN103095217B (en) | Low Phase Noise Voltage-controlled Oscillator | |
CN107231129B (en) | Harmonic control CMOS mixer based on transformer structure | |
CN103259553A (en) | A front-end system for radio devices | |
Ali et al. | A 42–46.4% PAE continuous class-F power amplifier with C gd neutralization at 26–34 GHz in 65 nm CMOS for 5G applications | |
CN104779919A (en) | Self-biased ultra wideband low-power-consumption low-noise amplifier (LNA) | |
Ying et al. | A HBT-based 300 MHz-12 GHz blocker-tolerant mixer-first receiver | |
TWI473419B (en) | Frequency doubler | |
Nocera et al. | Down-converter solutions for 77-GHz automotive radar sensors in 28-nm FD-SOI CMOS technology | |
CN104779917A (en) | Receiver front-end circuit based on integrated inductor noise cancelling technology | |
Krishnamurthy et al. | 580µW 2.2-2.4 GHz receiver with+ 3.3 dBm out-of-band IIP3 for IoT applications | |
CN102176657B (en) | Positive-feedback-broadband LNA (low noise amplifier) for millimeter wave frequency range | |
CN103078594A (en) | Radio-frequency front-end circuit for multiplexing current | |
CN205647440U (en) | Edge combination formula digital frequency multiplier based on transformer on piece | |
Ye et al. | A CMOS W-band× 4 frequency multiplier with cascading push-pull frequency doublers | |
Lin et al. | A 198.9 GHz-to-201.0 GHz injection-locked frequency divider in 65nm CMOS | |
CN103840770A (en) | Terahertz wave band quadrupler | |
Oz et al. | A compact 105–130 GHz push-push doubler, with 4dBm Psat and 18% efficiency in 28nm CMOS | |
CN201163761Y (en) | Harmonic generator | |
CN105897170B (en) | Edge combined type digital frequency multiplier based on on-chip transformer | |
Rastegar et al. | An integrated high linearity CMOS receiver frontend for 24-GHz applications | |
Li et al. | A 124 to 132.5 GHz frequency quadrupler with 4.4 dBm output power in 0.13 μm SiGe BiCMOS | |
Bourdel et al. | An inductorless CMOS UWB pulse generator with active pulse shaping circuit | |
WO2016041575A1 (en) | A power efficient frequency multiplier | |
Batistell et al. | SiP solutions for wireless transceiver impedance matching networks |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CP03 | Change of name, title or address |
Address after: 361000 Fujian City, Xiamen Software Park, the three phase of the main street, Yi Cheng, unit 359, 1404 Patentee after: Canada (Xiamen) microelectronics Limited by Share Ltd Address before: 361000 Xiamen, China (Fujian) free trade zone, Xiamen District, Hong Kong Road, No., unit 1702, No. 105 Patentee before: Chi Chi (Xiamen) Microelectronics Technology Co., Ltd. |
|
CP03 | Change of name, title or address | ||
AV01 | Patent right actively abandoned |
Granted publication date: 20161012 Effective date of abandoning: 20181120 |
|
AV01 | Patent right actively abandoned |