CN205584006U - Prevent surge circuit, switching power supply and display device - Google Patents
Prevent surge circuit, switching power supply and display device Download PDFInfo
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- CN205584006U CN205584006U CN201620202057.4U CN201620202057U CN205584006U CN 205584006 U CN205584006 U CN 205584006U CN 201620202057 U CN201620202057 U CN 201620202057U CN 205584006 U CN205584006 U CN 205584006U
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Abstract
The utility model discloses a prevent surge circuit, switching power supply and display device wherein, prevents that the surge circuit includes power source detection circuit and MOS pipe switch circuit, MOS pipe switch circuit has power input end and power output end, and power source detection circuit's sense terminal and MOS pipe switch circuit's power input end are connected, and power source detection circuit's control end and MOS pipe switch circuit's first controlled end are connected, power source detection circuit is used for when the power input end that detects MOS pipe switch circuit has the power input, and control MOS pipe switch circuit switch on, with export power supply. The utility model discloses technical scheme has the characteristics that the reliability is high.
Description
Technical field
This utility model relates to display device technology field, particularly to a kind of anti-surge circuit, Switching Power Supply and display device.
Background technology
The filter capacitor that current AC-DC switching power circuit, typically meeting arrange certain capacity at its input is filtered processing.
But, in power supply electrifying moment, circuit can produce surge current because of filter capacitor charging, therefore typically also can arrange anti-surge circuit carries out current limliting process.Traditional anti-surge circuit mainly includes a critesistor concatenated with circuit, utilizes its negative temperature coefficient feature to realize Anti-surging.In power supply electrifying moment, due to critesistor, to be in room temperature state resistance bigger so that the electric current flow through is less, reaches restriction effect；When through after a while, surge current disappears, and electric current tends to normal, and now critesistor is owing to along with self-heating, its resistance is gradually reduced, until being negligible, therefore, after circuit is normal, do not interfere with again normal circuit operation.
But, it is well known that the room temperature resistance of critesistor is the most all between several Europe to tens Europe, and in power supply electrifying moment, the surge current of tens peaces can be produced, the biggest electric current, the critesistor using tens ohm is only capable of playing the surge current of circuit certain inhibitory action, it is impossible to avoids the surge current produced in circuit largely, there is the defect of poor reliability.
Utility model content
Main purpose of the present utility model is to provide a kind of anti-surge circuit, it is intended to improves this anti-surge circuit inhibitory action to surge current, and improves the reliability of this anti-surge circuit.
For achieving the above object, the anti-surge circuit that the utility model proposes includes power sense circuit and metal-oxide-semiconductor on-off circuit；Described metal-oxide-semiconductor on-off circuit has power input and power output end, the test side of described power sense circuit is connected with the power input of described metal-oxide-semiconductor on-off circuit, and the end that controls of described power sense circuit is connected with the first controlled end of described metal-oxide-semiconductor on-off circuit；Wherein, described power sense circuit, for when the power input described metal-oxide-semiconductor on-off circuit being detected has power supply to input, controls the conducting of described metal-oxide-semiconductor on-off circuit, to export described power supply.
Preferably, described power sense circuit includes the first resistance, the 6th resistance, the first diode and the 4th audion；The test side that first end is described power sense circuit of described first resistance, the base stage interconnection of the second end of described first resistance, the negative electrode of described first diode, the first end of described 6th resistance and described 4th audion；The anode of described first diode, the second end of described 6th resistance and the grounded emitter of described 4th audion, the control end of the most described power sense circuit of current collection of described 4th audion.
Preferably, described metal-oxide-semiconductor on-off circuit includes the first electric capacity, the 3rd resistance, the 5th resistance and the second metal-oxide-semiconductor；First end is described metal-oxide-semiconductor on-off circuit first control end of described 5th resistance, the second end of described 5th resistance, the first end of described first electric capacity, the first end of described 3rd resistance and the gate interconnection of described second metal-oxide-semiconductor；The source electrode interconnection of the second end of described first electric capacity, the second end of described 3rd resistance and described second metal-oxide-semiconductor；The power input that link node is described metal-oxide-semiconductor on-off circuit of described first electric capacity, described 3rd resistance and described second metal-oxide-semiconductor, the power output end that drain electrode is described metal-oxide-semiconductor on-off circuit of described second metal-oxide-semiconductor.
Preferably, described anti-surge circuit also includes power cut off delay start-up circuit；The input of described power cut off delay start-up circuit is connected with the power output end of described metal-oxide-semiconductor on-off circuit, and the outfan of described power cut off delay start-up circuit is connected with the second controlled end of described metal-oxide-semiconductor on-off circuit.
Preferably, described power cut off delay start-up circuit includes the second resistance, the 4th resistance, the 7th resistance, the 8th resistance, the 9th resistance, the tenth resistance, the 11st resistance, the second diode, the second electric capacity, the 3rd audion, the 5th audion and the 6th audion；First end of described tenth resistance is connected with the second end of described 9th resistance, described tenth resistance and the input that link node is described power cut off delay start-up circuit of described 9th resistance；Second end interconnection of the second end of described tenth resistance, the anode of described second diode and described 11st resistance；First end of described 11st resistance, the first end of described second electric capacity, the first end of described 8th resistance and the grounded emitter of described 5th audion；The emitter stage interconnection of the second end of described second electric capacity, the negative electrode of described second diode and described 6th audion；The base stage of described 6th audion is connected with the first end of described 9th resistance, and the colelctor electrode of described 6th audion is connected with the second end of described 7th resistance；The base stage interconnection of the first end of described 7th resistance, the second end of described 8th resistance and described 5th audion；The colelctor electrode of described 5th audion is connected with the first end of described 4th resistance, the base stage interconnection of the second end of described 4th resistance, the first end of described second resistance and described 3rd audion；Second end and the emitter stage of described 3rd audion of described second resistance are connected with the power input of described metal-oxide-semiconductor on-off circuit, the outfan of the current collection the most described power cut off delay start-up circuit of described 3rd audion.
Preferably, described anti-surge circuit also includes reverse-connection preventing circuit；The input of described reverse-connection preventing circuit is for the voltage of input power circuit input end, second input of described reverse-connection preventing circuit is connected with the control end of described power sense circuit, and the outfan of described reverse-connection preventing circuit is connected with the power input of described metal-oxide-semiconductor control circuit.
Preferably, described reverse-connection preventing circuit includes the first metal-oxide-semiconductor；The first input end that drain electrode is described reverse-connection preventing circuit of described first metal-oxide-semiconductor, the grid of described first metal-oxide-semiconductor is described reverse-connection preventing circuit the second input, the outfan that source electrode is described reverse-connection preventing circuit of described first metal-oxide-semiconductor.
Preferably, described reverse-connection preventing circuit also includes the 12nd resistance, the 13rd resistance and the 3rd diode；First end of described 12nd resistance the first end with the grid of described first metal-oxide-semiconductor and described 13rd resistance respectively is connected, and the second end of described 13rd resistance is connected with the source electrode of described first metal-oxide-semiconductor；Second end of described 12nd resistance is connected with the negative electrode of described 3rd diode, described 13rd resistance and second input that link node is described reverse-connection preventing circuit of described 3rd diode.
This utility model also proposes a kind of Switching Power Supply, and described Switching Power Supply includes anti-surge circuit as above；Wherein, described anti-surge circuit includes power sense circuit and metal-oxide-semiconductor on-off circuit；Described metal-oxide-semiconductor on-off circuit has power input and power output end, the test side of described power sense circuit is connected with the power input of described metal-oxide-semiconductor on-off circuit, and the end that controls of described power sense circuit is connected with the first controlled end of described metal-oxide-semiconductor on-off circuit；Described power sense circuit, for when the power input described metal-oxide-semiconductor on-off circuit being detected has power supply to input, controls the conducting of described metal-oxide-semiconductor on-off circuit, to export described power supply.
This utility model also proposes a kind of display device, and described display device includes Switching Power Supply as above, and the structure of this display device breaker in middle power supply is identical with the structure of above-mentioned Switching Power Supply, and here is omitted.
The anti-surge circuit that the utility model proposes controls the conducting of described metal-oxide-semiconductor on-off circuit by using power sense circuit when power circuit powers on, switching characteristic due to the metal-oxide-semiconductor of metal-oxide-semiconductor on-off circuit, when conducting, internal resistance is by tapering into greatly, the electric current exported through the power output end VOUT of metal-oxide-semiconductor on-off circuit is incrementally increased along with the prolongation of power circuit power-on time, avoid power circuit powered on moment electric current excessive damage late-class circuit, during because powering on, the equivalent internal resistance of the metal-oxide-semiconductor of metal-oxide-semiconductor on-off circuit is gradually to be trended towards Rds (on) by infinity, Surge suppression effect is more preferable, so this anti-surge circuit has the advantages that reliability is high.
Accompanying drawing explanation
In order to be illustrated more clearly that this utility model embodiment or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in describing below is only embodiments more of the present utility model, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain other accompanying drawing according to the structure shown in these accompanying drawings.
Fig. 1 is the high-level schematic functional block diagram of this utility model anti-surge circuit first embodiment；
Fig. 2 is the high-level schematic functional block diagram of this utility model anti-surge circuit the second embodiment；
Fig. 3 is the high-level schematic functional block diagram of this utility model anti-surge circuit the 3rd embodiment；
Fig. 4 is an electrical block diagram of this utility model anti-surge circuit the 3rd embodiment.
Drawing reference numeral illustrates:
The realization of this utility model purpose, functional characteristics and advantage will in conjunction with the embodiments, are described further referring to the drawings.
Detailed description of the invention
Below in conjunction with the accompanying drawing in this utility model embodiment, the technical scheme in this utility model embodiment is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present utility model rather than whole embodiments.Based on the embodiment in this utility model, the every other embodiment that those of ordinary skill in the art are obtained under not making creative work premise, broadly fall into the scope of this utility model protection.
It addition, the description relating to " first ", " second " etc. in this utility model is only used for describing purpose, and it is not intended that indicate or imply its relative importance or the implicit quantity indicating indicated technical characteristic.Thus, define " first ", the feature of " second " can express or implicitly include at least one this feature.Additionally; technical scheme between each embodiment can be combined with each other; but must be based on those of ordinary skill in the art are capable of; when technical scheme combination occur conflicting maybe cannot realize time will be understood that the combination of this technical scheme does not exists, the most not this utility model require protection domain within.
The utility model proposes a kind of anti-surge circuit.
Referring to figs. 1 through the high-level schematic functional block diagram that Fig. 4, Fig. 1 are this utility model anti-surge circuit first embodiment；Fig. 2 is the high-level schematic functional block diagram of this utility model anti-surge circuit the second embodiment；Fig. 3 is the high-level schematic functional block diagram of this utility model anti-surge circuit the 3rd embodiment；Fig. 4 is an electrical block diagram of this utility model anti-surge circuit the 3rd embodiment.
As it is shown in figure 1, in this utility model embodiment, this anti-surge circuit includes power sense circuit 10 and metal-oxide-semiconductor on-off circuit 20；Described metal-oxide-semiconductor on-off circuit 20 has power input VIN and power output end VOUT, the test side of described power sense circuit 10 is connected with the power input VIN of described metal-oxide-semiconductor on-off circuit 20, and the end that controls of described power sense circuit 10 is connected with the first controlled end of metal-oxide-semiconductor on-off circuit 20；Wherein, described power sense circuit 10, for when the power input described MOS pipe on-off circuit 20 being detected has power supply to input, controls described metal-oxide-semiconductor on-off circuit 20 and turns on, to export described power supply.
When described anti-surge circuit powers on, the test side of described power sense circuit 10 detects that the power input VIN of described metal-oxide-semiconductor on-off circuit 20 has power input voltage VIN, described power sense circuit 10 control that end output is corresponding with described supply voltage VIN controls signal to described metal-oxide-semiconductor on-off circuit 20, described metal-oxide-semiconductor on-off circuit 20 is opened, and it is operated in variable resistance district, now, first controlled end of described metal-oxide-semiconductor on-off circuit 20 is minimum with the Negative Pressure Difference of power input VIN, the equivalent resistance of described metal-oxide-semiconductor on-off circuit 20 is maximum, the electric current of the power output end VOUT output of described metal-oxide-semiconductor on-off circuit 20 is minimum.Prolongation along with the power-on time of described power circuit, Negative Pressure Difference between first controlled end and the power input VIN of described metal-oxide-semiconductor on-off circuit 20 incrementally increases, the equivalent resistance of described metal-oxide-semiconductor on-off circuit 20 progressively reduces, and the electric current of the power output end output VOUT of described metal-oxide-semiconductor on-off circuit 20 incrementally increases.Until the constant current district of described metal-oxide-semiconductor on-off circuit 20 work, the electric current of the power output end VOUT output of described metal-oxide-semiconductor on-off circuit 20 is basically unchanged.
The anti-surge circuit that the utility model proposes controls the conducting of described metal-oxide-semiconductor on-off circuit 20 by using power sense circuit 10 when power circuit powers on, switching characteristic due to the metal-oxide-semiconductor of metal-oxide-semiconductor on-off circuit 20, when conducting, internal resistance is by tapering into greatly, the electric current exported through the power output end VOUT of metal-oxide-semiconductor on-off circuit 20 is incrementally increased along with the prolongation of power circuit power-on time, avoid power circuit powered on moment electric current excessive damage late-class circuit, during because powering on, the equivalent internal resistance of the metal-oxide-semiconductor of metal-oxide-semiconductor on-off circuit 20 is gradually to be trended towards Rds (on) by infinity, Surge suppression effect is more preferable, so this anti-surge circuit has the advantages that reliability is high.
Preferably, as shown in Figure 4, described power sense circuit 10 includes the first resistance R1, the 6th resistance R6, the first diode D1 and the 4th audion Q4；The test side that first end is described power sense circuit 10 of described first resistance R1, the base stage interconnection of second end of described first resistance R1, the negative electrode of described first diode D1, first end of described 6th resistance R6 and described 4th audion Q4；The anode of described first diode D1, second end of described 6th resistance R6 and the grounded emitter GND of described 4th audion Q4, the control end of the most described power sense circuit of current collection 10 of described 4th audion Q4.It should be noted that described 4th audion Q4 is NPN type triode.
Above-mentioned metal-oxide-semiconductor on-off circuit 20 includes the first electric capacity C1, the 3rd resistance R3, the 5th resistance R5 and the second metal-oxide-semiconductor Q2；First end is described metal-oxide-semiconductor on-off circuit 20 the first control end of described 5th resistance R5, second end of described 5th resistance R5, first end of described first electric capacity C1, first end of described 3rd resistance R3 and the gate interconnection of described second metal-oxide-semiconductor Q2；The source electrode interconnection of second end of described first electric capacity C1, second end of described 3rd resistance R3 and described second metal-oxide-semiconductor Q2；The power input that link node is described metal-oxide-semiconductor on-off circuit 20 of described first electric capacity C1, described 3rd resistance R3 and described second metal-oxide-semiconductor Q2, the power output end that drain electrode is described metal-oxide-semiconductor on-off circuit 20 of described second metal-oxide-semiconductor Q2.It should be noted that described second metal-oxide-semiconductor Q2 is enhancement mode PMOS.
When described anti-surge circuit powers on, the source electrode of described second metal-oxide-semiconductor Q2 and the first end input supply voltage VIN of described first resistance R1.Described first resistance R1 constitutes bleeder circuit with described 6th resistance R6, the voltage-drop loading that described 6th resistance R6 divides is in the base stage of described 4th audion Q4, described 4th audion Q4 conducting, described 4th audion Q4 exports positive voltage by described 5th resistance R5 to the grid of described second metal-oxide-semiconductor Q2, described second metal-oxide-semiconductor 20 turns on, described first electric capacity C1 charging.Now, the negative pressure between grid and the source electrode of described second metal-oxide-semiconductor Q2 is minimum, and the equivalent resistance of described second metal-oxide-semiconductor Q2 is maximum, and the electric current of the drain electrode output of described second metal-oxide-semiconductor Q2 is minimum.
Prolongation along with the conduction time of described anti-surge circuit, the voltage at described first electric capacity C1 two ends incrementally increases, negative pressure between grid and the source electrode of described second metal-oxide-semiconductor Q2 incrementally increases, the equivalent resistance of described second metal-oxide-semiconductor Q2 progressively reduces, and the electric current of the drain electrode output of described second metal-oxide-semiconductor Q2 incrementally increases.Until described first electric capacity C1 charging complete, described second metal-oxide-semiconductor Q2 is operated in constant current district, and the electric current of the drain electrode output of described second metal-oxide-semiconductor Q2 tends to constant.
In this preferred embodiment, by using the 4th audion Q4 to turn on when anti-surge circuit powers on, and then make described second metal-oxide-semiconductor Q2 conducting.Affected the conducting state of described second metal-oxide-semiconductor Q2 by described first electric capacity C1, and then the electric current of the Q2 drain electrode output of described second metal-oxide-semiconductor is incrementally increased.Owing to the charging current of the filter capacitor in described power circuit incrementally increases, power circuit will not produce surge current.Therefore, the reliability of this anti-surge circuit is the highest.
Further, as in figure 2 it is shown, described anti-surge circuit also includes power cut off delay start-up circuit 30；The input of described power cut off delay start-up circuit 30 is connected with the power output end end of described metal-oxide-semiconductor on-off circuit 20, and the outfan of described power cut off delay start-up circuit 30 is connected with the second control end of described metal-oxide-semiconductor on-off circuit 20.
When described anti-surge circuit powers on, the power input VIN input supply voltage VIN of described metal-oxide-semiconductor on-off circuit 20, the test side also input supply voltage VIN of described power sense circuit 10, described power sense circuit 10 control that end output is corresponding with described supply voltage VIN controls signal to described metal-oxide-semiconductor on-off circuit 20, described metal-oxide-semiconductor on-off circuit 20 is opened, and is operated in amplification region.Meanwhile, described metal-oxide-semiconductor on-off circuit 20 charges to described power cut off delay start-up circuit 30, due to the charging voltage direction of described power cut off delay start-up circuit 30, to open required voltage direction therewith contrary, described power cut off delay start-up circuit 30 ends, therefore, described power cut off delay start-up circuit 30 when described anti-surge circuit powers on described metal-oxide-semiconductor on-off circuit 20 without impact.Along with the prolongation of described anti-surge circuit power-on time, the circuit flowing through described metal-oxide-semiconductor on-off circuit 20 incrementally increases, and the output electric current of described anti-surge circuit is gradually increased, until described power circuit normally works.
When described anti-surge circuit power-off, on the one hand, the power input VIN no-voltage input of described metal-oxide-semiconductor on-off circuit 20, the test side of described power sense circuit 10 is also without input voltage, the outfan output of described power sense circuit 10 controls signal to the first control end of described metal-oxide-semiconductor on-off circuit 20 accordingly, and described metal-oxide-semiconductor on-off circuit 20 turns off.On the other hand, owing to the late-class circuit of described anti-surge circuit includes filter capacitor (not shown), therefore, when described metal-oxide-semiconductor on-off circuit 20 turns off, the voltage of the power output end of described metal-oxide-semiconductor on-off circuit 20 will not reduce to rapidly 0, but progressively reduces.When the output voltage of described metal-oxide-semiconductor on-off circuit 20 is less than described power cut off delay start-up circuit 30 charging voltage before this, described power cut off delay start-up circuit 30 turns on, described power cut off delay start-up circuit 30 exports the signal of telecommunication and controls end, so that described metal-oxide-semiconductor on-off circuit 20 is operated in rapidly cut-off region to the second of described metal-oxide-semiconductor on-off circuit 20.If described anti-surge circuit powers on again in the short time, owing to the output voltage of described metal-oxide-semiconductor on-off circuit 20 does not drop to make described power-off delay circuit 30 end size, therefore, in the short time, metal-oxide-semiconductor on-off circuit 20 is still operated in cut-off region.It is noted that when implementing the present embodiment, it is also possible to the first control end and second of described metal-oxide-semiconductor on-off circuit 20 is controlled end and merges into a control end, do not limit.
Set up described power cut off delay start-up circuit 30 to extend the deadline of described metal-oxide-semiconductor on-off circuit 20, make when repeating to power in the power circuit short time, metal-oxide-semiconductor on-off circuit 20 has little time to start rapidly, avoid filter capacitor quick charge again, further increase the reliability of described anti-surge circuit.
Preferably, as shown in Figure 4, described power cut off delay start-up circuit 30 includes the second resistance R2, the 4th resistance R4, the 7th resistance R7, the 8th resistance R8, the 9th resistance R9, the tenth resistance R10, the 11st resistance R11, the second diode D2, the second electric capacity C2, the 3rd audion Q3, the 5th audion Q5 and the 6th audion Q6；First end of described tenth resistance R10 is connected with second end of described 9th resistance R9, the input that link node is described power cut off delay start-up circuit 30 of described tenth resistance R10 and described 9th resistance R9；The second end interconnection of second end of described tenth resistance R10, the anode of described second diode D2 and described 11st resistance R11；First end of described 11st resistance R11, first end of described second electric capacity C2, first end of described 8th resistance R8 and the grounded emitter GND of described 5th audion Q5；The emitter stage interconnection of second end of described second electric capacity C2, the negative electrode of described second diode D2 and described 6th audion Q6；The base stage of described 6th audion Q6 is connected with first end of described 9th resistance R9, and the colelctor electrode of described 6th audion Q3 is connected with second end of described 7th resistance R7；The base stage interconnection of first end of described 7th resistance R7, second end of described 8th resistance R8 and described 5th audion Q5；The colelctor electrode of described 5th audion Q5 is connected with first end of described 4th resistance R4, the base stage interconnection of second end of described 4th resistance R4, first end of described second resistance R2 and described 3rd audion Q3；Second end and the emitter stage of described 3rd audion Q3 of described second resistance R2 are connected with the power input VIN of described metal-oxide-semiconductor on-off circuit 20, the outfan of the current collection the most described power cut off delay start-up circuit 30 of described 3rd audion Q3.
Further, as it is shown on figure 3, described anti-surge circuit also includes reverse-connection preventing circuit 40；The input of described reverse-connection preventing circuit 40 is for the voltage VIN of input power circuit input end, second input of described reverse-connection preventing circuit 40 is connected with the control end of described power sense circuit 10, and the outfan of described reverse-connection preventing circuit 10 is connected with the power input VIN of described metal-oxide-semiconductor on-off circuit 20.
When reverse power connection, the supply voltage VIN of input is anti-phase, and described reverse-connection preventing circuit 40 ends, and the power input no-voltage input of described metal-oxide-semiconductor on-off circuit 20, described metal-oxide-semiconductor on-off circuit 20 ends, and described anti-surge circuit no current exports.Set up described reverse-connection preventing circuit 40, circuit because reverse power connection can be avoided to suffer damage, further improve the reliability of described anti-surge circuit.
Preferably, described reverse-connection preventing circuit 40 includes the first metal-oxide-semiconductor Q1；The first input end that drain electrode is described reverse-connection preventing circuit 40 of described first metal-oxide-semiconductor Q1, the grid of described first metal-oxide-semiconductor Q1 is described reverse-connection preventing circuit 40 second input, the outfan that source electrode is described reverse-connection preventing circuit 40 of described first metal-oxide-semiconductor Q1.It is noted that described reverse-connection preventing circuit 40 also includes the 12nd resistance R12, the 13rd resistance R13 and the 3rd diode D3；First end of described 12nd resistance R12 is connected with the grid of described first metal-oxide-semiconductor Q1 and first end of described 13rd resistance R13 respectively, second end of described 12nd resistance R12 is connected with the negative electrode of described 3rd diode D3, second input that link node is described reverse-connection preventing circuit 40 of described 12nd resistance R12 and described 3rd diode D3.
It should be noted that in the present embodiment, described first metal-oxide-semiconductor Q1 is enhancement mode PMOS；Described 3rd audion Q3 and described 6th audion Q6 is PNP type triode, and described 5th audion Q5 is NPN type triode.
To sum up, and combine accompanying drawing 1 to Fig. 4, below the physical circuit principle of this utility model anti-surge circuit be described in detail:
When described anti-surge circuit switches on power, described first resistance R1 and described 6th resistance R6 constitutes bleeder circuit, and the voltage-drop loading that described 6th resistance R6 divides is in the base stage of described 4th audion Q4, described 4th audion Q4 conducting.Meanwhile, on the one hand, after the input voltage VIN of described anti-surge circuit is by the parasitic diode of described first metal-oxide-semiconductor Q1, through described 12nd resistance R12 and described 13rd resistance R13 dividing potential drop, there is provided a constant cut-in voltage for described first metal-oxide-semiconductor Q1, make described first metal-oxide-semiconductor Q1 in the conduction state.On the other hand, input voltage VIN charges to described first electric capacity C1 by the parasitic diode of described first metal-oxide-semiconductor Q1, and the size of this charging current is limited by described 5th resistance R5, the voltage at described first electric capacity C1 two ends is gradually increased, when the voltage at described first electric capacity C1 two ends reaches the cut-in voltage of described second metal-oxide-semiconductor Q2, described second metal-oxide-semiconductor Q2 enters amplification characteristic working area, the equivalent resistance of described second metal-oxide-semiconductor Q2 is gradually reduced along with described first being gradually increased of electric capacity C1 both end voltage, the electric current flowing through described first metal-oxide-semiconductor Q1 and described second metal-oxide-semiconductor Q2 is gradually increased, until normal circuit operation.
Increase along with the electric current flowing through described first metal-oxide-semiconductor Q1 and described second metal-oxide-semiconductor Q2, the output voltage of described anti-surge circuit is gradually increased, described tenth resistance R10 constitutes bleeder circuit with described 11st resistance R11, the voltage that described 11st resistance R11 is got is through described second diode D2 to described second electric capacity C2 charging, and the voltage swing until described second electric capacity C2 two ends is VOUTmax × R11/ (R10+R11) (herein ignoring the pressure drop of described second diode D2).Now, it is negative voltage between emitter stage and the base stage of described 6th audion Q6, described 6th audion Q6 cut-off, voltage between emitter stage and the base stage of described 5th audion Q5 is 0V, described 5th audion Q5 cut-off, described 3rd audion Q3 ends because of the cut-off of described 5th audion Q5.
When described anti-surge circuit deenergization, the base stage no-voltage input of described 4th audion Q4, described 4th audion Q4 cut-off, described first electric capacity C1 is discharged by described 3rd resistance R3, voltage between source electrode and the grid of described first metal-oxide-semiconductor Q1 and described second metal-oxide-semiconductor Q2 is all gradually reduced, and described first metal-oxide-semiconductor Q1 and described second metal-oxide-semiconductor Q2 all trends towards cut-off.
But, owing to including the electric capacity in parallel with described anti-surge circuit with the late-class circuit that described anti-surge circuit is connected, therefore, when described first metal-oxide-semiconductor Q1 and described second metal-oxide-semiconductor Q2 all trends towards cut-off, output voltage VO UT of described anti-surge circuit is not to disappear immediately, but is gradually reduced.When the output voltage of described anti-surge circuit deteriorates to less than voltage (VOUTmax × R11/ (R10+R11)) at described second electric capacity C2 two ends, described 6th audion Q6 conducting, the voltage being carried on described second electric capacity C2 entered described 7th resistance R7 and described 8th resistance R8 dividing potential drop, the base stage of the voltage input extremely described 5th audion Q5 that described 8th resistance R8 divides, described 5th audion Q5 conducting, described 3rd audion Q3 obtains forward bias voltage, described 3rd audion Q3 conducting.Now, described first electric capacity C1 is through described 3rd audion Q3 electric discharge so that described first metal-oxide-semiconductor Q1 and described second metal-oxide-semiconductor Q2 ends rapidly.Hereafter, in the short period of time, described anti-surge circuit is made to be again switched on power supply, the voltage at described first electric capacity C1 two ends is 0, described first metal-oxide-semiconductor Q1 and described second metal-oxide-semiconductor Q2 turns off, only when the voltage at described second electric capacity C2 two ends is less than during to 0.7 × (R7+R7)/R8, and described 5th audion Q5 ends, described 3rd audion Q3 cut-off, whole circuit enters power-up state.
Additionally, when the input voltage VIN reversal connection of described anti-surge circuit, owing to being negative voltage between base stage and the emitter stage of described 4th audion Q4, described 4th audion Q4 ends, cause no-voltage on described 13rd resistance R13, described first metal-oxide-semiconductor Q1 cut-off.Now, even if exist on described first electric capacity C1 voltage (as input voltage VIN from just connect quickly become reversal connection time, voltage on first electric capacity C1 also has little time to decline), due to the described 3rd anti-phase cut-off of diode D3, described first electric capacity C1 can not provide cut-in voltage for described first metal-oxide-semiconductor Q1.Making described first metal-oxide-semiconductor Q1 cut-off, described anti-surge circuit is without output voltage.
Technical solutions of the utility model have the advantages that one, by described voltage detecting circuit 10 to the first input end input voltage signal of described metal-oxide-semiconductor control circuit 20, so that the second metal-oxide-semiconductor Q2 in described metal-oxide-semiconductor control circuit 20 is operated in amplification region, so that the electric current flowing through described metal-oxide-semiconductor control circuit 20 incrementally increases, and then the output electric current of described anti-surge circuit is gradually increased, it is to avoid the generation of Anti-surging electric current.They are two years old, the described second metal-oxide-semiconductor Q2 cut-off of signal of telecommunication control is exported by setting up power-off delay circuit 30, make when repeating to power in the anti-surge circuit short time, described second metal-oxide-semiconductor Q2 is made not turn on rapidly because described first electric capacity C1 has little time to charge rapidly, it is to avoid anti-surge circuit and power circuit are impacted by big electric current continuously.Its three, set up reverse-connection preventing circuit 40 so that when anti-surge circuit or power circuit input voltage reverse connection, anti-surge circuit does not starts, it is to avoid circuit because input voltage reverse connection and the damage that causes.Its four, this circuit is made up of basic components and parts, simple in construction, and required device is few, has the feature of low cost.
This utility model also proposes a kind of Switching Power Supply, this Switching Power Supply includes anti-surge circuit, the concrete structure of this anti-surge circuit is with reference to above-described embodiment, owing to this Switching Power Supply have employed whole technical schemes of above-mentioned all embodiments, the most at least having all beneficial effects that the technical scheme of above-described embodiment is brought, this is no longer going to repeat them.Wherein, described anti-surge circuit includes power sense circuit 10 and metal-oxide-semiconductor on-off circuit 20；Described metal-oxide-semiconductor on-off circuit 20 has power input VIN and power output end VOUT, the test side of described power sense circuit 10 is connected with the power input VIN of described metal-oxide-semiconductor on-off circuit 20, and the end that controls of described power sense circuit 10 is connected with the first controlled end of described metal-oxide-semiconductor on-off circuit 20；Wherein, described power sense circuit 10, for when the power input described metal-oxide-semiconductor on-off circuit 20 being detected powers on, controls described metal-oxide-semiconductor on-off circuit 20 and turns on, to export described power supply.
This utility model also proposes a kind of display device, and described display device includes Switching Power Supply, and the circuit structure of this display device breaker in middle power supply is identical with the circuit structure of above-mentioned Switching Power Supply, and here is omitted.It is noted that described display device can be large-screen splicing system, television set etc., do not limit.
The foregoing is only preferred embodiment of the present utility model; not thereby the scope of the claims of the present utility model is limited; every under inventive concept of the present utility model; utilize the equivalent structure transformation that this utility model description and accompanying drawing content are made, or directly/be indirectly used in other relevant technical fields and be included in scope of patent protection of the present utility model.
Claims (10)
1. an anti-surge circuit, it is characterised in that include power sense circuit and metal-oxide-semiconductor on-off circuit；Described metal-oxide-semiconductor on-off circuit has power input and power output end, the power detecting end of described power sense circuit is connected with the power input of described metal-oxide-semiconductor on-off circuit, and the end that controls of described power sense circuit is connected with the first controlled end of described metal-oxide-semiconductor on-off circuit；Wherein, described power sense circuit, for when the power input described metal-oxide-semiconductor on-off circuit being detected has power supply to input, controls the conducting of described metal-oxide-semiconductor on-off circuit, to export described power supply.
2. anti-surge circuit as claimed in claim 1, it is characterised in that described power sense circuit includes the first resistance, the 6th resistance, the first diode and the 4th audion；The test side that first end is described power sense circuit of described first resistance, the base stage interconnection of the second end of described first resistance, the negative electrode of described first diode, the first end of described 6th resistance and described 4th audion；The anode of described first diode, the second end of described 6th resistance and the grounded emitter of described 4th audion, the control end of the most described power sense circuit of current collection of described 4th audion.
3. anti-surge circuit as claimed in claim 1, it is characterised in that described metal-oxide-semiconductor on-off circuit includes the first electric capacity, the 3rd resistance, the 5th resistance and the second metal-oxide-semiconductor；First end is described metal-oxide-semiconductor on-off circuit first control end of described 5th resistance, the second end of described 5th resistance, the first end of described first electric capacity, the first end of described 3rd resistance and the gate interconnection of described second metal-oxide-semiconductor；The source electrode interconnection of the second end of described first electric capacity, the second end of described 3rd resistance and described second metal-oxide-semiconductor；The power input that link node is described metal-oxide-semiconductor on-off circuit of described first electric capacity, described 3rd resistance and described second metal-oxide-semiconductor, the power output end that drain electrode is described metal-oxide-semiconductor on-off circuit of described second metal-oxide-semiconductor.
4. the anti-surge circuit as described in claims 1 to 3 any one, it is characterised in that described anti-surge circuit also includes power cut off delay start-up circuit；The input of described power cut off delay start-up circuit is connected with the power output end of described metal-oxide-semiconductor on-off circuit, and the outfan of described power cut off delay start-up circuit is connected with the second controlled end of described metal-oxide-semiconductor on-off circuit.
5. anti-surge circuit as claimed in claim 4, it is characterized in that, described power cut off delay start-up circuit includes the second resistance, the 4th resistance, the 7th resistance, the 8th resistance, the 9th resistance, the tenth resistance, the 11st resistance, the second diode, the second electric capacity, the 3rd audion, the 5th audion and the 6th audion；First end of described tenth resistance is connected with the second end of described 9th resistance, described tenth resistance and the input that link node is described power cut off delay start-up circuit of described 9th resistance；Second end interconnection of the second end of described tenth resistance, the anode of described second diode and described 11st resistance；First end of described 11st resistance, the first end of described second electric capacity, the first end of described 8th resistance and the grounded emitter of described 5th audion；The emitter stage interconnection of the second end of described second electric capacity, the negative electrode of described second diode and described 6th audion；The base stage of described 6th audion is connected with the first end of described 9th resistance, and the colelctor electrode of described 6th audion is connected with the second end of described 7th resistance；The base stage interconnection of the first end of described 7th resistance, the second end of described 8th resistance and described 5th audion；The colelctor electrode of described 5th audion is connected with the first end of described 4th resistance, the base stage interconnection of the second end of described 4th resistance, the first end of described second resistance and described 3rd audion；Second end and the emitter stage of described 3rd audion of described second resistance are connected with the power input of described metal-oxide-semiconductor on-off circuit, the outfan of the current collection the most described power cut off delay start-up circuit of described 3rd audion.
6. the anti-surge circuit as described in claims 1 to 3 any one, it is characterised in that described anti-surge circuit also includes reverse-connection preventing circuit；The input of described reverse-connection preventing circuit is for the voltage of input power circuit input end, second input of described reverse-connection preventing circuit is connected with the control end of described power sense circuit, and the outfan of described reverse-connection preventing circuit is connected with the power input of described metal-oxide-semiconductor control circuit.
7. anti-surge circuit as claimed in claim 6, it is characterised in that described reverse-connection preventing circuit includes the first metal-oxide-semiconductor；The first input end that drain electrode is described reverse-connection preventing circuit of described first metal-oxide-semiconductor, the grid of described first metal-oxide-semiconductor is described reverse-connection preventing circuit the second input, the outfan that source electrode is described reverse-connection preventing circuit of described first metal-oxide-semiconductor.
8. anti-surge circuit as claimed in claim 7, it is characterised in that described reverse-connection preventing circuit also includes the 12nd resistance, the 13rd resistance and the 3rd diode；First end of described 12nd resistance the first end with the grid of described first metal-oxide-semiconductor and described 13rd resistance respectively is connected, and the second end of described 13rd resistance is connected with the source electrode of described first metal-oxide-semiconductor；Second end of described 12nd resistance is connected with the negative electrode of described 3rd diode, described 12nd resistance and second input that link node is described reverse-connection preventing circuit of described 3rd diode.
9. a Switching Power Supply, it is characterised in that described Switching Power Supply includes the anti-surge circuit as described in claim 1 to 8 any one.
10. a display device, it is characterised in that described display device includes Switching Power Supply as claimed in claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620202057.4U CN205584006U (en) | 2016-03-16 | 2016-03-16 | Prevent surge circuit, switching power supply and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620202057.4U CN205584006U (en) | 2016-03-16 | 2016-03-16 | Prevent surge circuit, switching power supply and display device |
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| Publication Number | Publication Date |
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| CN205584006U true CN205584006U (en) | 2016-09-14 |
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| CN201620202057.4U Expired - Fee Related CN205584006U (en) | 2016-03-16 | 2016-03-16 | Prevent surge circuit, switching power supply and display device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108462163A (en) * | 2017-02-20 | 2018-08-28 | 成都鼎桥通信技术有限公司 | Meet the direct current reverse-connection preventing circuit of negative sense surge requirement |
| CN111158152A (en) * | 2020-02-17 | 2020-05-15 | Oppo广东移动通信有限公司 | Head-mounted display device and DLP projection system |
| WO2024060754A1 (en) * | 2022-09-19 | 2024-03-28 | 海信视像科技股份有限公司 | Lamp panel circuit |
-
2016
- 2016-03-16 CN CN201620202057.4U patent/CN205584006U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108462163A (en) * | 2017-02-20 | 2018-08-28 | 成都鼎桥通信技术有限公司 | Meet the direct current reverse-connection preventing circuit of negative sense surge requirement |
| CN108462163B (en) * | 2017-02-20 | 2019-09-17 | 成都鼎桥通信技术有限公司 | Meet the direct current reverse-connection preventing circuit of negative sense surge requirement |
| CN111158152A (en) * | 2020-02-17 | 2020-05-15 | Oppo广东移动通信有限公司 | Head-mounted display device and DLP projection system |
| WO2024060754A1 (en) * | 2022-09-19 | 2024-03-28 | 海信视像科技股份有限公司 | Lamp panel circuit |
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