CN205249177U - Multiplexing module of hardware logic resource - Google Patents

Abstract

The utility model relates to a multiplexing module of hardware logic resource, the same clock of whole module sharing, the input clock is connected to all triggers, the clock terminal of memory, address incoming signal is connected to the write address end of memory behind the two -stage trigger, while address incoming signal also lug connection holds to the address of reading of memory, it is connected to writing the messenger and holding of memory to make to input behind the two -stage trigger, wherein make ability incoming signal be connected to combinatory logic's input behind the one -level trigger, make simultaneously can incoming signal also lug connection reading the messenger and can hold to the memory, data input is connected to combinatory logic's input behind the one -level trigger, the input for combinatory logic is exported to the data terminal of reading of memory, and combinatory logic's output is connected to the write data end of memory with data input after also the feedback returns to merge simultaneously for the output of module through one -level trigger succeeding crop, the beneficial effects are that saving the combinatory logic resource has been realized, can utilize limited logical resource to realize the more data processing of large capacity.

Description

A kind of hardware logic resource multiplex module

Technical field

The utility model relates to a kind of logical resource multiplex technique, particularly a kind of hardware logic resource multiplex module.

Background technology

SDH (SDH) is widely used in fiber optic communication, comprises that backbone network, Metropolitan Area Network (MAN) also have Access Network.Along with portfolio constantly increases, to mass data intersect and the difficulty selected also increasing, especially to large capacityWhen access data intersects, need to expend a large amount of hardware logic resources, how utilize limited hardware resource to realize largerThe data cross of capacity, this design for hardware circuit is a challenge, especially processes pointer with logical resource multiplex techniqueProblem is extremely urgent.

Summary of the invention

In view of the problem that prior art exists, demand and application characteristic thereof that the utility model intersects for SDH, at monolithicOn FPGA, realized the logical resource Multiplexing module of the low order interlace algorithm capacity of 80G × 20G, specifically technical scheme is, a kind of hardwareLogical resource Multiplexing module, is characterized in that: input signal comprises clock, address input, enables input, data input signal,Whole module shares same clock, and input clock is connected to the clock end of all triggers, memory, address input signalAfter two-stage trigger, be connected to the write address end of memory, what simultaneously address input signal was also directly connected to memory reads groundLocation end, enables to input the Enable Pin of writing that is connected to memory after two-stage trigger, wherein enables input signal and triggers through one-levelAfter device, be connected to the input of combinational logic, enable input signal simultaneously and be also directly connected to the Enable Pin of reading of memory, dataInput is connected to the input of combinational logic after one-level trigger, and the read data end of memory is exported to the input of combinational logic,And the output of combinational logic also feeds back after merging with data input and connects as the output of module simultaneously after one-level triggerReceive the data terminal of writing of memory.

The beneficial effects of the utility model are, have realized the saving to combination logic resource, can utilize limited logicResource realizes more jumbo data processing, and the LUT resource expending can reduce by two orders of magnitude.

Brief description of the drawings

Fig. 1 is circuit theory diagrams of the present utility model.

Detailed description of the invention

As shown in Figure 1, processing low-order pointer with SDH illustrates. The frame multiplexing structure of SDH determines that its 8 VC4(are everyIndividual VC4 comprises again 63 VC12) totally 504 VC12 be that order arrives successively in time, might as well be successively suitable according to arrivingOrder is called time slot 0 to time slot 503, and each VC12 time slot has pointer expense separately to need to process, and while processing pointer expense, needsTo use the state of its processing last time and the input data of current this time slot simultaneously, suppose present clock period (time=0)Process time slot 0, namely combinational logic (need to be used the input pointer expense of current time slots 0 in the pointer expense of processing time slot 0The status information that data and last time thereof process), need to carry out the read memory operation of time slot 1 (setting is read address and is read simultaneouslyThe cache information of time slot 1), then in the time of the next clock cycle (time=1), time slot 0 result out and write buffer memoryIn order to calling (the write memory operation of time slot 0) next time, buffered results last time of time slot 1 has also read simultaneously, justCatch up with the input message of current time slots 1, can carry out the pointer overhead processing operation of time slot 1, go to read when ensuing simultaneouslyThe cache information of gap 2, until proceed to loop back after No. 503 time slot time slot 0 and the like.

The input of module comprises clock, INADD, input and enables and input data (requiring input to align), whereinINADD is used to indicate current time slots numbering, and it is (passable between slot cycle period that input enables to be used to indicate data validityThe available free period), whole module shares a clock, and memory is the RAM memory of standard, and (reading and writing clock is clockIdentical), write address, write enable, write data, read address, read to enable, read data pin, it connects as shown in the figure. Trigger isStandard not with reset not with the simplest preset trigger, have input data, output data, clock pins, its connect asShown in figure. Combinational logic is common logic circuit, combines, to concrete gate circuit combination by gate circuits such as AOIsStructure does not have particular/special requirement, as long as meet any group of timing closure (being less than a clock cycle from being input to the time delay of output)Logical can, its input signal is connected to the input pin of gate circuit, output signal comes from the efferent duct of gate circuitPin,

Trigger was used for a clock cycle of signal delay, and memory is used for the status information of certain subtask of buffer memory,Combinational logic is to realize the core that process subtask, and combinational logic part is wherein exactly the hardware money being re-usedSource, making identical multiple subtasks can share use (instead of has how many subtasks just to use with a hardware resourceHow many part hardware resources). Trigger and memory are in order to realize cost multiplexing and that additionally pay. Should be noted thatBe, in figure, combinational logic and trigger below thereof have formed the model that clock cycle delay is 1 jointly, but in fact this is notBe necessary, be greater than 1 only needs corresponding increase write address and writes the trigger progression enabling with matching delay if postpone(ensure to write enable, write address, write the alignment of data).

Principle

In SDH agreement, based on frame structure, bandwidth has been divided into many time slots, i.e. virtual containers at different levels, comprise high-order VC4 andThe VC12 of low order etc. In the time that needs intersect to time slot, first need according to time slot high-order, low-order pointer one-level level separatelyData are taken down, realize and resolve the hardware resource that these pointers need to consume some. Consider the number of time slotAmount a lot (particularly low order time slot), goes to resolve if each time slot consumes a logic hardware resource separately, has consumed largeThe hardware resource of amount. Simultaneously, due to SDH, time slot is that Queue sequence arrives, so every part of hardware resource can be quiteOnly work in long a period of time clock cycle and then wait until just works when next same time slot arrives again one time againThe clock cycle, be equivalent to a kind of hardware resource waste (compensatory, require, perhaps receive to some extent aspect power consumption in clock rateBenefit). When realize the parsing of SDH pointer with FPGA, under limited hardware resource, to realize more jumbo if considerData-handling capacity, can be used hardware resource multiplex technique, can allow so multiple low-order pointers parsings share same hardPart resource, by allowing resource work to save hardware resource within each clock cycle. By using the multiplexing knot in Fig. 1Structure, no longer needs to copy a lot of part identical combinational logics and goes to process different pointers, but multiplexing patrols with a combinationCollect and processed multiple different pointers parsings. The cost of doing so has just additionally consumed a small amount of memory resource and a small amount ofAuxiliary logic resource. Not enough when combination logic resource, and available memory resource is while also having redundancy, can adopt this multiplexingMethod, realizes the saving to combination logic resource, also just can under limited resource, realize more jumbo data processing.

In fact the multiplexing technology of hardware resource is not just processed pointer for SDH, anyly meets multiple tasks in sequentialCycle repeats the sight that order arrives successively and can apply. For can application hardware resource multiplexing, this generic task should meet3 points below:

(1) task can be split as the subtask of multiple repetitions, and each subtask is same class problem completely, Ke YiyongIdentical resource goes to process;

(2) all subtasks share same clock and can avoid completely in time, will not occur two or moreThe situation that subtask occurs simultaneously;

(3) subtask order arrival successively, and circulation occurs having index signal to indicate the numbering of current task.

So in order to process each subtask, need to know the state while processing this task last time, and current this taskInput, the output that then produces this task according to respective handling logic also needs this result cache simultaneously, withGetting time this task of circulation time ready can retaking of a year or grade status information while again occurring.

More abstract and general, the task processing that this class cycle is repeated to occur the successively operation that is divided three classes:

(1) Read_last: read buffer memory last time this task state outcome;

(2) Current: upgrade the input of current this task;

(3) Write: produce state that this task is new as exporting and write buffer memory.

The task of considering arrives a subtask in each clock cycle, so multiplexing resource is in each clock cycleInside, all in work, within n the cycle of clock, carry out following 3 operations: the Write operation of task (n-1), task simultaneouslyThe Current operation of n and the Read_last operation of task (n+1). As shown in the table:

The operating slotted table of table 1

The time shaft that the first behavior clock cycle in table is unit, Read_last, Current, Write tri-row are respectivelyThree kinds of corresponding above-mentioned operations, in a certain column clock cycle, the capable corresponding content of corresponding operating is the subtask volume of this operationNumber (consider that subtask sum M is certain and circulation occurs, actual subtask numbering may need after M deliveryTo).

Claims (1)

1. a hardware logic resource multiplex module, is characterized in that: input signal comprises the input of clock, address, enables input,The whole module of data input signal shares same clock, and input clock is connected to the clock end of all triggers, memory,Address input signal is connected to the write address end of memory after two-stage trigger, and address input signal is also directly connected to simultaneouslyMemory read address end, enable input and be connected to the Enable Pin of writing of memory after two-stage trigger, wherein enable input letterThe input that number is connected to combinational logic after one-level trigger, enables input signal simultaneously and is also directly connected to reading of memoryEnable Pin, data input is connected to the input of combinational logic after one-level trigger, and the read data end of memory is exported to combinationThe input of logic, and the output of combinational logic output as module after one-level trigger also feeds back with data defeated simultaneouslyAfter entering to merge, be connected to the data terminal of writing of memory.