CN205246716U

CN205246716U - Control formula signal generator outward

Info

Publication number: CN205246716U
Application number: CN201521029470.7U
Authority: CN
Inventors: 胡聪; 贾梦怡; 李智; 许川佩; 朱望纯; 牛军浩; 殷贤华
Original assignee: Guilin University of Electronic Technology
Current assignee: Guilin University of Electronic Technology
Priority date: 2015-12-11
Filing date: 2015-12-11
Publication date: 2016-05-18
Anticipated expiration: 2025-12-11

Abstract

The utility model discloses a control formula signal generator outward, including master control circuit, signal generating circuit, amplitude adjustment circuit and serial circuits, master control circuit receives the outer instruction that the device sent of controlling through serial circuits to according to the corresponding signal of command control signal generating circuit production, the signal is after the amplitude adjustment circuit carries out amplitude adjustment, and the test input of input to the outside instrument that awaits measuring holds. As long as the outer device of controlling possesses instruction reception and transmition function, can control a plurality of master control circuit, the utility model discloses control section produces the part separately with the signal, and consequently the weight that has significantly reduced, carried out the batch instrument and examined time measuring, can improve detection efficiency greatly, the selection of chip and peripheral circuit in master control circuit, signal generating circuit and the amplitude adjustment circuit possesses throughput the same or even better with present signal processor and stability, can provide signal the same or even higher grade of precision.

Description

A kind of external control type signal generator

Technical field

The utility model relates to instrument detection field, is specifically related to a kind of external control type signal generator.

Background technology

While producing instruments, need to use the signal detection instrument of different wave, frequency, amplitude and phase place,Existing signal generator is because the signal of its generation is accurate, the feature easily of debugging is widely used in surveyingIn amount, excitation and time domain response, signal generator is applied to instrument and detects, be undoubtedly best choosingSelect. But existing signal generator price is high, heavy, carry out batch detection on production line time,Need expend a large amount of human and material resources and fund, and detection efficiency is low. For present situation, need to propose onePlant and be applied to instrument detection, can ensure the accuracy of signal, can reduce costs again, improve and detect effectThe signal generator of rate.

Utility model content

The utility model provides a kind of external control type signal generator, solves existing signal generator and is applied toThe low problem of detection efficiency occurring when instrument detects.

The utility model addresses the above problem by the following technical programs:

A kind of external control type signal generator, comprises governor circuit, signal generating circuit, amplitude adjusted electricityRoad and serial port circuit;

The input of described signal generating circuit is connected with governor circuit, described signal generating circuit defeatedGoing out end is connected with the input of amplitude regulating circuit; Described amplitude regulating circuit and output with outsideThe detection input of instrument to be measured is connected; Described serial port circuit is connected with governor circuit, described serial port powerRoad is connected with external control device.

In such scheme, further comprise display circuit; The input of described display circuit and master control electricityRoad is connected.

In such scheme, further comprise key circuit; The output of described key circuit and master control electricityRoad is connected.

In such scheme, described serial port circuit by data interface connector, level translator, capacitor C 6,Capacitor C 7, capacitor C 11, capacitor C 12 and capacitor C 13 form;

No. 5 pins of described data interface connector connect digitally; 3 of described data interface connectorNumber pin is connected with No. 8 pins of level translator; No. 2 pins of described data interface connector withNo. 7 pins of level translator are connected; No. 1 pin of described level translator is through capacitor C 7 and electricityNo. 3 pins of flat turn parallel operation are connected; No. 4 pins of described level translator are through capacitor C 11 and levelNo. 5 pins of converter are connected; No. 9 pins of described level translator are connected with governor circuit; InstituteNo. 10 pins stating level translator are connected with governor circuit; No. 6 pins of described level translatorConnect digitally through capacitor C 12; No. 15 pins of described level translator connect digitally; Described levelNo. 2 pins of converter are connected with power supply VCC through capacitor C 6; Draw for No. 16 of described level translatorPin is connected with power supply VCC; Described power supply VCC connects digitally through capacitor C 13.

In such scheme, described signal generating circuit by DDS device J4, crystal oscillator CY1, capacitor C 1,Capacitor C 5, capacitor C 8, capacitor C 9, capacitor C 10, capacitor C 11, capacitor C 12, capacitor C 15,Capacitor C 16, resistance R 2, resistance R 3, resistance R 17, resistance R 18, resistance R 12, resistance R 8 withAnd resistance R 5 forms;

No. 1 pin of described DDS device J4 connects in analog through capacitor C 12; Described resistance R 8 also connectsIn capacitor C 12 two ends; No. 2 pins of described DDS device J4 connect in analog through capacitor C 10; InstituteNo. 3 pins stating DDS device J4 meet power supply VCC3.3 through capacitor C 11; Described power supply VCC3.3Connect digitally through capacitor C 9; No. 4 pins of described DDS device J4 meet power supply VCC3.3; DescribedNo. 5 pins of DDS device J4 meet power supply VCC3.3 through resistance R 12; 6 of described DDS device J4Number pin connects digitally through capacitor C 16; No. 7 pins of described DDS device J4 connect digitally; InstituteNo. 8 pins stating DDS device J4 are connected with No. 3 pins of crystal oscillator CY1; Described DDS device J4No. 9 pins connect digitally through resistance R 17; No. 10 pins of described DDS device J4 are through resistance R 18Connect digitally; No. 11 pins of described DDS device J4 connect digitally; Described DDS device J4'sNo. 12 pin connects digitally; No. 13 pins of described DDS device J4 are connected with governor circuit; DescribedNo. 14 pins of DDS device J4 are connected with governor circuit; No. 15 pins of described DDS device J4Be connected with governor circuit; No. 16 pins of described DDS device J4 are connected with amplitude regulating circuit; InstituteNo. 17 pins stating DDS device J4 connect in analog through capacitor C 5; 18 of described DDS device J4Number pin connects in analog; After No. 19 pins of described DDS device J4 are connected with resistance R 2, through electricityHolding C5 connects in analog; No. 19 pins of described DDS device J4 connect in analog through capacitor C 1; DescribedNo. 19 pins of DDS device J4 connect in analog through resistance R 3; Draw for No. 19 of described DDS device J4Pin is connected with amplitude regulating circuit; No. 20 pins of described DDS device J4 connect simulation through capacitor C 15Ground; No. 20 pins of described DDS device J4 connect in analog through resistance R 5; 4 of described crystal oscillator CY1Number pin meets power supply VCC3.3, and described power supply VCC3.3 connects digitally through capacitor C 8; Described crystal oscillatorNo. 2 pins of CY1 connect digitally.

In such scheme, described digitally through magnetic bead be connected in analog.

In such scheme, described amplitude regulating circuit is by amplitude regulator IC1, relay K 1, optocouplerU1, triode Q1, slide rheostat RP1, resistance R 1, resistance R 7, resistance R 9, resistance R 10,Resistance R 11, resistance R 13, diode D1, capacitor C 2 and capacitor C 3 form;

No. 1 pin of described amplitude regulator IC1 is connected with No. 1 pin of outside socket J3; InstituteNo. 2 pins stating amplitude regulator IC1 are connected with the sliding end of slide rheostat RP1; Described slip1 stiff end of rheostat RP1 is connected with power supply-5V, another 1 of described slide rheostat RP1Stiff end is connected with power supply+5V; Two of No. 3 pins of described amplitude regulator IC1 and relay K 1Individual normally opened contact is connected; No. 4 pins of described amplitude regulator IC1 connect digitally; Described amplitude is adjustedAfter No. 5 pins of joint device IC1 are connected with No. 7 pins of amplitude regulator IC1, with outside socket J6No. 1 pin be connected; No. 6 pins of described amplitude regulator IC1 connect digitally through capacitor C 2,No. 6 pins of described amplitude regulator IC1 meet power supply-5V; No. 8 of described amplitude regulator IC1Pin connects digitally through capacitor C 3, and No. 8 pins of described amplitude regulator IC1 meet power supply+5V; InstituteStating optocoupler U1 is made up of light emitting diode and phototriode; The anode of described light emitting diode is through electricityResistance R1 is connected with governor circuit, and the negative electrode of described light emitting diode connects digitally; Described photosensitive three utmost pointsThe colelctor electrode of pipe meets power supply+5V, the colelctor electrode phase of the colelctor electrode of described phototriode and triode Q1Connect; The emitter stage of described phototriode is connected with the base stage of triode Q1 through resistance R 7; Described threeThe emitter stage of utmost point pipe Q1 is connected with wherein 1 coil contact of relay K 1, described triode Q1Emitter stage be connected with the negative electrode of diode D1; Another 1 coil contact of described relay K 1 connects numberWord ground, another 1 coil contact of described relay K 1 is connected with the anode of diode D1; Described continuing1 normally-closed contact of electrical equipment K1 is connected with signal generating circuit through resistance R 9, described relay K 11 normally-closed contact connect digitally through resistance R 10; Another 1 normally-closed contact of described relay K 1Connect digitally through resistance R 11, another 1 normally-closed contact of described relay K 1 is through resistance R 13 and letterNumber circuit for generating is connected.

Advantage of the present utility model and effect are:

1, receive by serial port circuit the instruction that external control device sends by governor circuit, and according to instructionControl signal circuit for generating produces corresponding signal, sends merit as long as external control device possesses command receptionCan, can control multiple governor circuits, and the utility model control section and signal generatorSeparately, reduce weight, therefore, while carrying out the detection of batch instrument, can greatly improve detection efficiency;

2, governor circuit, signal generating circuit and amplitude regulating circuit chips and peripheral circuitSelect, possess even higher disposal ability identical with existing signal processor and stability, can provideIdentical even more high-class signal.

Brief description of the drawings

Fig. 1 is structural principle block diagram of the present utility model.

Fig. 2 is the schematic diagram of the utility model serial port circuit.

Fig. 3 is the schematic diagram of the utility model signal generating circuit.

Fig. 4 is the schematic diagram of the utility model amplitude regulating circuit.

Detailed description of the invention

Below in conjunction with embodiment, the utility model is described in further detail, but the utility model does not limit toIn these embodiment.

The disclosed a kind of external control type signal generator of the utility model: electricity occurs by governor circuit, signalRoad, amplitude regulating circuit, serial port circuit, display circuit and key circuit composition; There is electricity in signalThe input on road is connected with governor circuit, the output of signal generating circuit and amplitude regulating circuit defeatedEntering end is connected; Amplitude regulating circuit with output be connected with the detection input of outside instrument to be measured;Serial port circuit is connected with governor circuit, and serial port circuit is connected with external control device; The input of display circuitBe connected with governor circuit; The output of key circuit is connected with governor circuit, as shown in Figure 1.

Governor circuit is using MSP430F1612 microcontroller as main control chip, and MSP430F1612 is 16The signal processor of position super low-power consumption, possess that disposal ability is powerful, system works is stable, peripheral on sheetModule is abundant, development environment convenience and high-efficiency, multiple clock module, low-voltage, low-power consumption, adaptation workThe features such as industry level running environment. In the utility model, the effect of governor circuit is to pass through serial port circuitReceive the instruction of external control device, or receive instruction by scanning key circuit, and according to instruction controlSignal generating circuit produces corresponding signal and detects the performance of outside instrument to be measured, and controls demonstration electricityThe signal that road display circuit for generating produces. Above-mentioned instruction comprises waveform, frequency, the width of signalDegree and phase place. As long as external control device possesses instruction transmission and command reception function, just can pass through serial port powerRoad is controlled at least 1 governor circuit, in the time of batch detection instrument, without frequently moving signalGenerator; Of the present utility model signal generation is divided with external control device and separated, greatly reduced signalThe weight of generator, when instrument detects in batches, even if need to move signal generator, weight is also very little,Therefore, the utility model can improve detection efficiency greatly.

Serial port circuit is by data interface connector, level translator, capacitor C 6, capacitor C 7, electric capacityC11, capacitor C 12 and capacitor C 13 form; No. 5 pins of data interface connector connect digitally;No. 3 pins of data interface connector are connected with No. 8 pins of level translator; Data-interface connectsNo. 2 pins of device are connected with No. 7 pins of level translator; No. 1 pin of level translator is through electricityHolding C7 is connected with No. 3 pins of level translator; No. 4 pins of level translator are through capacitor C 11Be connected with No. 5 pins of level translator; No. 9 pins of level translator and the P3.5 of governor circuitPort is connected; No. 10 pins of level translator are connected with the P3.4 port of governor circuit; Level turnsNo. 6 pins of parallel operation connect digitally through capacitor C 12; No. 15 pins of level translator connect digitally;No. 2 pins of level translator are connected with power supply VCC through capacitor C 6; Draw for No. 16 of level translatorPin is connected with power supply VCC; Power supply VCC connects digitally through capacitor C 13, as shown in Figure 2.

In serial port circuit, the MAX3232 that level translator adopts MAXIM company of the U.S. to produce,MAX3232 is the RS-232 electrical level transferring chip that comprises two-way driver and receiver. Serial port power terminalBe RS-232C level, governor circuit end is Transistor-Transistor Logic level, and MAX3232 is for realizing the serial of the twoCommunication, carries out the level conversion of serial port input/output signal. RS-232 conversion chip inside hasAn electric pressure converter, for by power supply VCC voltage transitions be RS-232C interface required ± 10VVoltage. The utility model is used wherein road driver and a receiver of MAX3232, wherein, and No. 7Pin t2out is RS-232C level output end mouth, and No. 8 pin r2in are RS-232C level input ports,No. 9 pin r2out are TTL/CMOS level output end mouths, and lO pin t2in is TTL/CMOS levelInput port. The P3.5 of MSP430F1612 and P3.4 port, as the second function mouth, represent respectivelySerial data receiving port rxd and serial data transmit port txd.

In serial port circuit, data interface connector adopts DB9, is applicable to 9 of main control chipNeedle serial port. No. 2 pins are for receiving FPDP, and No. 3 pin sends FPDP, and No. 5 pins are for connecingGround port, the utility model adopts three-wire system to connect serial ports. External control device only need possess instruction send andCommand reception function, just can control the utility model, external control device and governor circuit communicationTime, be RS-232C level with driver by TTL/CMOS level conversion at the transmitting terminal of governor circuit,With receiver, RS-232C level is converted to TTL/CMOS level at receiving terminal again.

Signal generating circuit by DDS device J4, crystal oscillator CY1, capacitor C 1, capacitor C 5, capacitor C 8,Capacitor C 9, capacitor C 10, capacitor C 11, capacitor C 12, capacitor C 15, capacitor C 16, resistance R 2,Resistance R 3, resistance R 17, resistance R 18, resistance R 12, resistance R 8 and resistance R 5 form; DDSNo. 1 pin of device J4 connects in analog through capacitor C 12; Resistance R 8 is connected to capacitor C 12 two ends;No. 2 pins of DDS device J4 connect in analog through capacitor C 10; No. 3 pin warps of DDS device J4Capacitor C 11 meets power supply VCC3.3; Power supply VCC3.3 connects digitally through capacitor C 9; DDS device J4No. 4 pins meet power supply VCC3.3; No. 5 pins of DDS device J4 connect power supply through resistance R 12VCC3.3; No. 6 pins of DDS device J4 connect digitally through capacitor C 16; 7 of DDS device J4Number pin connects digitally; No. 8 pins of DDS device J4 are connected with No. 3 pins of crystal oscillator CY1; DDSNo. 9 pins of device J4 connect digitally through resistance R 17; No. 10 pins of DDS device J4 are through resistanceR18 connects digitally; No. 11 pins of DDS device J4 connect digitally; Draw for No. 12 of DDS device J4Pin connects digitally; No. 13 pins of DDS device J4 are connected with the sd end of governor circuit; DDS deviceNo. 14 pins of J4 are connected with the scl end of governor circuit; No. 15 pins of DDS device J4 and masterThe fs end of control circuit is connected; Resistance R 9 in No. 16 pins of DDS device J4 and amplitude regulating circuitOne end be connected; No. 17 pins of DDS device J4 connect in analog through capacitor C 5; DDS device J4No. 18 pins connect in analog; After No. 19 pins of DDS device J4 are connected with resistance R 2, through electricityHolding C5 connects in analog; No. 19 pins of DDS device J4 connect in analog through capacitor C 1; DDS deviceNo. 19 pins of J4 connect in analog through resistance R 3; No. 19 pins of DDS device J4 and amplitude adjustedIn circuit, one end of resistance R 13 is connected; No. 20 pins of DDS device J4 connect simulation through capacitor C 15Ground; No. 20 pins of DDS device J4 connect in analog through resistance R 5; No. 4 pins of crystal oscillator CY1 connectPower supply VCC3.3, power supply VCC3.3 connects digitally through capacitor C 8; No. 2 pins of crystal oscillator CY1 connect numberWord ground, as shown in Figure 3.

Digitally through magnetic bead be connected in analog. Data signal is carried a large amount of harmonic waves, if not by numeralGround with separate from access point in analog, the easy interference simulation signal of harmonic wave in data signal. Work as simulationWhen signal is high frequency or forceful electric power signal, also can affect the normal work of digital circuit. The utility model bagContain what digital circuit of analog circuit, the index of the harmonic effects simulation small-signal that data signal is carried,Therefore the utility model adopts magnetic bead to connect digitally and in analog, by common ground digitally and in analogResistance drops to minimum. Magnetic bead adopts the Ferrite Material sintered surface at high band with good resistance characteristicBecome, the high-frequency noise and the spike that are exclusively used on Inhibitory signal line, power line disturb, and also have absorption quietThe ability of electric pulse.

DDS device J4 in signal generating circuit is AD9834, AD9834 be by phase accumulator,Sinusoidal read-only storage SINROM and 10 D/A converters are integrated in the DDS on single CMOS chipCircuit. AD9834 only needs a reference clock, a low precision resistance and 8 decoupling capacitors, justCan produce digitized sine wave, frequency can reach 25MHz. The digital circuit part of AD9834 inside is logicalOften be operated in 2.5V. The voltage of No. 5 pins is down to 2.5V by voltage-stablizer on chip. AD9834'sThe operating voltage of digital interface is also from the voltage of No. 5 pins. When the electricity of No. 5 pins of AD9834When pressure is equal to or less than 2.7V, No. 4 pins and No. 6 pins are simultaneously restrained, thereby by chipVoltage-stablizer bypass. 13,14, No. 15 pins of AD9834 are controlled by governor circuit, respectively with master controlSd, the scl of circuit, fs end, the sine wave that AD9834 produces and triangular signal iout are from 19The output of number pin, the square-wave signal sign of generation is after internal low pass filter and comparator, from 16The output of number pin.

The 1-20 pin of AD9834 be respectively FSADJUST, REFOUT, COMP, AVDD, DVDD,CAP、DGND、MCLK、FSELECT、PSELECT、RESET、SLEEP、SDATA、SCLK、FSYNC、SIGN, VIN, AGND, IOUT and IOUTB. The 1-4 pin of crystal oscillator CY1 be respectively GND, GND,CLKOUT and VCC.

Amplitude regulating circuit by amplitude regulator IC1, relay K 1, optocoupler U1, triode Q1,Slide rheostat RP1, resistance R 1, resistance R 7, resistance R 9, resistance R 10, resistance R 11, resistanceR13, diode D1, capacitor C 2 and capacitor C 3 form; No. 1 pin of amplitude regulator IC1 withNo. 1 pin of outside socket J3 is connected; No. 2 pins of amplitude regulator IC1 and slide rheostatThe sliding end of RP1 is connected; 1 stiff end of slide rheostat RP1 is connected with power supply-5V, slidesAnother 1 stiff end of rheostat RP1 is connected with power supply+5V; No. 3 pins of amplitude regulator IC1Be connected with two normally opened contacts of relay K 1; No. 4 pins of amplitude regulator IC1 connect digitally;After No. 5 pins of amplitude regulator IC1 are connected with No. 7 pins of amplitude regulator IC1, with outsideNo. 1 pin of socket J6 is connected; No. 6 pins of amplitude regulator IC1 connect digitally through capacitor C 2,No. 6 pins of amplitude regulator IC1 meet power supply-5V; No. 8 pins of amplitude regulator IC1 are through electricityHold C3 and connect digitally, No. 8 pins of amplitude regulator IC1 meet power supply+5V; Optocoupler U1 is by luminousDiode and phototriode composition; The anode of light emitting diode is connected with governor circuit through resistance R 1,The negative electrode of light emitting diode connects digitally; The colelctor electrode of phototriode meets power supply+5V, photosensitive three utmost pointsThe colelctor electrode of pipe is connected with the colelctor electrode of triode Q1; The emitter stage of phototriode through resistance R 7 withThe base stage of triode Q1 is connected; Wherein 1 coil of the emitter stage of triode Q1 and relay K 1Contact is connected, and the emitter stage of triode Q1 is connected with the negative electrode of diode D1; Another 1 of relay K 1Individual coil contact connects digitally, another 1 coil contact of relay K 1 and the anode phase of diode D1Connect; 1 normally-closed contact of relay K 1 in resistance R 9 and signal generating circuit AD9834 19Number pin is connected, and 1 normally-closed contact of relay K 1 connects digitally through resistance R 10; Relay K 1Another 1 normally-closed contact connect digitally through resistance R 11, another 1 normally-closed contact warp of relay K 1Resistance R 13 is connected with No. 16 pins of AD9834 in signal generating circuit. The group of amplitude regulating circuitOne-tenth and circuit diagram are as shown in Figure 4.

Amplitude regulator IC1 is AD603,8 pins of AD603 be respectively GPOS, GENG,VINP, COMM, FDBK, VNEG, VOUT and VPOS. Signal generating circuit producesSinusoidal wave and triangular signal iout is 600mV left and right, and square-wave signal sign is output as a 3V left sideThe right side, all needs decay to input to AD603 again, the utility model adopt respectively R9 and R10, R11 andR13 carries out ratio decay; Relay K 1 is for switching sign and iout signal; Relay K 1 is logicalDisconnected moment can produce counter electromotive force, therefore reversal connection diode between two coil contacts of relay K 1D1, for the protection of relay K 1; Between governor circuit and triode Q1, be connected in series optocoupler U1, enterThe conversion of row electrical-optical-electricity, plays buffer action. Optocoupler U1 is made up of light emitting source and light-receiving device, luminousSource and light-receiving device are assembled in same closed shell, to each other with transparent insulator isolation, light emitting sourcePin is input, and the pin of light-receiving device is output, and optocoupler U1 of the present utility model is by luminous twoUtmost point pipe and phototriode composition.

For AD603, its gain G F is determined by the type of attachment of No. 5 pins and No. 7 pins. WhenWhen No. 5 pins and No. 7 pin short circuits, GF=31.07dB; No. 5 pins and No. 7 pins itBetween access resistance R EXT, GF can be arranged on to the arbitrary value between 31.07dB～51.07dB,But the gain accuracy under this pattern decreases, when outer meeting resistance is during in 2K left and right, errorGreatly; When No. 5 pins and No. 7 pins are during for open circuit, GF=51.07dB. If in No. 7 pins and 4Between number pin, access suitable resistance and can improve gain, maximum can reach 60dB.

AD603 has three kinds of mode of operations:

(1) by No. 5 pins and No. 7 pin short circuits, can obtain maximum bandwidth is 90MHz, gainScope is-11.07dB～+ 31.07dB;

(2) between No. 5 pins and No. 7 pins, access resistance R EXT, No. 5 pins and No. 4Between pin, access the electric capacity of 5.6pF as frequency compensation;

(3) No. 5 pins and No. 7 pin open circuits access 18pF between No. 7 pins and No. 4 pinsElectric capacity for extension frequency response range.

In pattern (2), according to the relational expression of amplifier, choosing suitable REXT value can obtainDifferent gain ranging values, in the time of REXT=2.15K Europe, gain ranging is-1dB～+ 41dB; At mouldIn formula (3), gain ranging is 8.93dB～51.07dB, and bandwidth is 9MHz. When VG existsWhile carrying out linear gain control with 40dB/V (being 25mV/dB) in the scope of-500mV～+ 500mV,Gain G (dB) with the pass of VG (V) is: G=40VG+GOi (i=1,2,3), wherein VG=VPOS-VNEG.In pattern (1), GOi=10dB; In pattern (2), GOi=10dB～30dB is (by external electricityResistance REXT determines); In pattern (3), GOi=30dB. When controlling voltage VG at-500mV～+ 500mVOutside time, gain G and VG no longer meet linear relationship. In the time of VG=-526mV, gaining isG=GF-42.14, in the time of VG=+526, gains as G=GF. The utility model need control AD603 0～Between 30dB, can select pattern (1) or pattern (2), in order to make circuit simpler, this practicalityThe novel pattern (1) of selecting.

Display circuit adopts PVG19264, for display waveform, frequency, amplitude and phase place. Use20K rheostat regulates PVG19264 gray scale, with time suitable aobvious by regulating this resistance to selectShow gray scale.

For ease of detecting, the utility model has increased key circuit, and key circuit is matrix form button,For in the time not using external control device, outside instrument to be measured being detected, matrix form button is for selectingWaveform frequency, amplitude and phase place.

The course of work of the present utility model is: governor circuit receives external control device by serial port circuit and sendsInstruction, or receive instruction by scanning key circuit, and according to instruction control signal circuit for generatingProduce corresponding signal iout or sign, signal iout or sign carry out width through amplitude regulating circuitAfter degree regulates, input to the detection input of outside instrument to be measured, outside instrument to be measured detected,Meanwhile, governor circuit control display circuit idsplay order comprises waveform, frequency, amplitude and phase placeInformation.

Claims

1. an external control type signal generator, is characterized in that:

Comprise governor circuit, signal generating circuit, amplitude regulating circuit and serial port circuit;

2. a kind of external control type signal generator according to claim 1, is characterized in that: enterOne step comprises display circuit; The input of described display circuit is connected with governor circuit.

3. a kind of external control type signal generator according to claim 1, is characterized in that: enterOne step comprises key circuit; The output of described key circuit is connected with governor circuit.

4. a kind of external control type signal generator according to claim 1, is characterized in that:

Described serial port circuit by data interface connector, level translator, capacitor C 6, capacitor C 7,Capacitor C 11, capacitor C 12 and capacitor C 13 form;

5. a kind of external control type signal generator according to claim 1, is characterized in that:

Described signal generating circuit is by DDS device J4, crystal oscillator CY1, capacitor C 1, capacitor C 5, electricityHold C8, capacitor C 9, capacitor C 10, capacitor C 11, capacitor C 12, capacitor C 15, capacitor C 16, electricity5 groups of resistance R2, resistance R 3, resistance R 17, resistance R 18, resistance R 12, resistance R 8 and resistance RBecome;

6. a kind of external control type signal generator according to claim 5, is characterized in that: instituteState digitally through magnetic bead be connected in analog.

7. a kind of external control type signal generator according to claim 1, is characterized in that:

Described amplitude regulating circuit is by amplitude regulator IC1, relay K 1, optocoupler U1, triodeQ1, slide rheostat RP1, resistance R 1, resistance R 7, resistance R 9, resistance R 10, resistance R 11,Resistance R 13, diode D1, capacitor C 2 and capacitor C 3 form;