CN205192420U - Test piece that squints within a definite time layer upon layer in control multilayer printed circuit board - Google Patents
Test piece that squints within a definite time layer upon layer in control multilayer printed circuit board Download PDFInfo
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- CN205192420U CN205192420U CN201520884244.0U CN201520884244U CN205192420U CN 205192420 U CN205192420 U CN 205192420U CN 201520884244 U CN201520884244 U CN 201520884244U CN 205192420 U CN205192420 U CN 205192420U
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Abstract
The utility model relates to a test piece that squints within a definite time layer upon layer in control multilayer printed circuit board, characterized by: including test piece body, be equipped with multilayer inner -layer core plate skew detection line on the test piece body, test piece body surface is equipped with outer electrical test point and test piece, and the test piece links together with printed circuit board's conducting hole, and center that outer electrical test order is equipped with each layer inner -layer core plate of conducting hole connection detection line that squints. Each layer inner -layer core plate skew detects line arrangement in the left and right sides of conducting hole, and the inner -layer core plate skew detection line and the controlling of conducting hole of the left and right sides have the skew size between the side. The test piece is a plurality of, and a conducting hole is connected respectively to every test piece. The utility model discloses can carry out assay and improve effectively bad board skew size, reduce the production of defective products.
Description
Technical field
The utility model relates to a kind ofly monitors the test pieces offset between multilayer printed circuit board interior-layer layer.
Background technology
The development trend of, multifunction lightening, integrated along with consumption electronic product, its manufacture craft to P.e.c. Rigid Flex requires more and more higher.Comply with this trend, the printed-wiring board (PWB) with the application of multilayer core material can become the pith of printed circuit board (PCB) gradually.There is multilayer core material application of printed wiring board, as the term suggests be exactly the printed-wiring board (PWB) of core material quantity > 2 layers, core material quantity≤2 layer of normal printed wiring board, the advantages such as its effect can allow printed-wiring board (PWB) thickness of slab is thinner, the number of plies is more, Signal transmissions is faster, finished size is less.
Current multilayer printed circuit board is short-circuited when finished product electrical functionality is tested, and generally can analyze reason, as core material skew, but can not analyze the size of concrete skew.
Summary of the invention
The purpose of this utility model overcomes the deficiencies in the prior art, provides a kind of and monitor the test pieces offset between multilayer printed circuit board interior-layer layer, analyzes bad plate offset dimensions and effectively improve, and reduces the generation of defective products.
According to the technical scheme that the utility model provides, a kind ofly monitor the test pieces offset between multilayer printed circuit board interior-layer layer, it is characterized in that: comprise test pieces body, test pieces body is provided with multilayer core material offset detection circuit, test pieces body surface is provided with outer testing electrical property point and test block, the via of test block and printed-wiring board (PWB) links together, and the center of outer testing electrical property point is provided with via and connects each layer core material offset detection circuit.
Further, described each layer core material offset detection line arrangement, in the left and right sides of via, has offset dimensions between the core material offset detection circuit of the left and right sides and the left and right sides of via.
Further, described test block is multiple, and each test block connects a via respectively.
The utility model has the advantages that the test pieces by designing can monitor the concrete size offset between printed-wiring board (PWB) interior-layer layer.In test pieces is different by setting, layer line is to the size of via, interior layer line and via is done the measuring point of testing electrical property at skin, has short circuit then to indicate skew during measurement.
Accompanying drawing explanation
Fig. 1 is the front view of standard test piece described in the utility model.
Fig. 2 is the side view of Fig. 1.
Fig. 3 is the vertical view of Fig. 1.
Embodiment
Below in conjunction with concrete accompanying drawing, the utility model is described in further detail.
As shown in Fig. 1 ~ figure, the test pieces offset between described monitoring multilayer printed circuit board interior-layer layer comprises test pieces body 1, first offset detection circuit 2, outer testing electrical property point 3, second offset detection circuit 4, test block 5, the 3rd offset detection circuit 6, via 7, the 4th offset detection circuit 8 etc.
As shown in FIG. 1 to 3, the utility model comprises test pieces body 1, test pieces body 1 is provided with multilayer core material offset detection circuit (as shown in FIG. 1 to 3, first offset detection circuit 2, second offset detection circuit 4, the 3rd offset detection circuit 6 and the 4th offset detection circuit 8), according to the internal layer quantity correspondence increase and decrease of actual printed-wiring board (PWB), 4 layers of core material offset detection circuit in the present embodiment, can be devised.Described test pieces body 1 surface is provided with circular outer testing electrical property point 3 and square test block 5, test block 5 links together with the via 7 of printed-wiring board (PWB), and the center of outer testing electrical property point 3 is provided with via and connects each layer core material offset detection circuit.Described each layer core material offset detection line arrangement is in the left and right sides of via 7, between the core material offset detection circuit of the left and right sides and the left and right sides of via 7, there is offset dimensions A, this size A can arrange multiple different size simultaneously, the via 7 that each test block 5 is connected is designed to a size A, as shown in Figure 3,0.2mm and 0.23mm two kinds is devised.Interior layer line and via are done the measuring point of testing electrical property at skin by the utility model, have short circuit then to indicate skew during measurement.
Principle of work of the present utility model: in use, is set to open circuit by test block 5 and outer testing electrical property point 3; The test pieces of the corresponding number of plies of the internal layer quantitative design according to actual printed wire is on the break edge of printed-wiring board (PWB), if the test block short circuit of the core material offset detection circuit of test block 5 and certain one deck, then can judge that the internal layer circuit of this layer offset by A size to the left or to the right.Because the left and right distance of core material offset detection circuit and via can be set to multiple different size, if be designed to other size, then can judge concrete offset dimensions, then the rest may be inferred for other layer.
When printed-wiring board (PWB) has buried via hole layer, only need buried via hole layer measurement circuit and buried via hole layer test block be set on described test pieces body, do some vias and corresponding test block when finished product again, then can monitor when finished product testing electrical property.
Enforcement of the present utility model can monitor offset dimensions between multilayer printed circuit board interior-layer layer, test pieces can design on the large plate and platelet of printed-wiring board (PWB) simultaneously, physical dimension is little, do not take up space, can adjust accordingly according to dissimilar, size, the number of plies printed-wiring board (PWB), be convenient to printed-wiring board (PWB) processing factory management and control quality, improve and promote processing procedure productive capacity.
Claims (3)
1. monitor the test pieces offset between multilayer printed circuit board interior-layer layer for one kind, it is characterized in that: comprise test pieces body (1), test pieces body (1) is provided with multilayer core material offset detection circuit, test pieces body (1) surface is provided with outer testing electrical property point (3) and test block (5), test block (5) links together with the via (7) of printed-wiring board (PWB), and the center of outer testing electrical property point (3) is provided with via and connects each layer core material offset detection circuit.
2. the test pieces offset between monitoring multilayer printed circuit board interior-layer layer as claimed in claim 1, it is characterized in that: described each layer core material offset detection line arrangement, in the left and right sides of via (7), has offset dimensions between the left and right sides of the core material offset detection circuit of the left and right sides and via (7).
3. the test pieces offset between monitoring multilayer printed circuit board interior-layer layer as claimed in claim 1, is characterized in that: described test block (5) is for multiple, and each test block (5) connects a via (7) respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520884244.0U CN205192420U (en) | 2015-11-06 | 2015-11-06 | Test piece that squints within a definite time layer upon layer in control multilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520884244.0U CN205192420U (en) | 2015-11-06 | 2015-11-06 | Test piece that squints within a definite time layer upon layer in control multilayer printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205192420U true CN205192420U (en) | 2016-04-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520884244.0U Active CN205192420U (en) | 2015-11-06 | 2015-11-06 | Test piece that squints within a definite time layer upon layer in control multilayer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205192420U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105277110A (en) * | 2015-11-06 | 2016-01-27 | 高德（江苏）电子科技有限公司 | Test piece for monitoring offset between inner layers of multi-layer printed circuit board |
-
2015
- 2015-11-06 CN CN201520884244.0U patent/CN205192420U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105277110A (en) * | 2015-11-06 | 2016-01-27 | 高德（江苏）电子科技有限公司 | Test piece for monitoring offset between inner layers of multi-layer printed circuit board |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: Jiangsu province Wuxi Chunhui road 214101 Xishan City Economic Development Zone No. 32 Patentee after: Gaode (Jiangsu) Electronic Technology Co.,Ltd. Address before: Jiangsu province Wuxi Chunhui road 214101 Xishan City Economic Development Zone No. 32 Patentee before: GULTECH (JIANGSU) ELECTRONIC TECHNOLOGIES CO.,LTD. |
|
| CP01 | Change in the name or title of a patent holder |