CN205070992U - Host computer transceiver, receiving and dispatching system and host computer receiving and dispatching system - Google Patents
Host computer transceiver, receiving and dispatching system and host computer receiving and dispatching system Download PDFInfo
- Publication number
- CN205070992U CN205070992U CN201520867192.6U CN201520867192U CN205070992U CN 205070992 U CN205070992 U CN 205070992U CN 201520867192 U CN201520867192 U CN 201520867192U CN 205070992 U CN205070992 U CN 205070992U
- Authority
- CN
- China
- Prior art keywords
- electronic switch
- transceiver
- voltage
- bus
- host computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
The utility model relates to a communication equipment field especially relates to a host computer transceiver, receiving and dispatching system and host computer receiving and dispatching system. The utility model provides a host computer transceiver passes through balanced bridge conduct drive, can change the polarity of bus wantonly, can make communication bus nonpolarity, convenient construction. The encoder that the host computer transceiver adopted non -return -to -zero communication to pass through in the transceiver realizes that finite difference model passes through the balanced bridge drive to be realized, in digital communication system, and the natural interference killing feature that can both improve the bus of this dual mode. Through set up current detection module in the host computer transceiver, make the host computer transceiver possess the bus and open a way and short circuit monitoring ability. Power consumptive through the current detection bus, the electric current is less than restriction value explanation bus opens a way, and the electric current is higher than the short circuit of restriction value explanation bus. The built -in constant voltage power supply of transceiver realizes the adaptation to wide input voltage, therefore the operating voltage scope broad of host computer transceiver, and adaptable multiple host unit power reduces the power supply circuit cost.
Description
Technical field
The utility model relates to communication equipment field, particularly relates to a kind of host transceiver, receive-transmit system and main frame receive-transmit system.
Background technology
Host transceiver adopts wire transmission, and host transceiver is used for being connected with main frame, as the important communication port of main frame, but the structure of existing host transceiver composition is comparatively complicated, hardware cost is higher, and is unfavorable for installing, and the maintenance for the later stage is made troubles equally.
Utility model content
Technical problem to be solved in the utility model is: provide a kind of structure is simple, cost is low host transceiver, receive-transmit system and main frame receive-transmit system.
In order to solve the problems of the technologies described above, the first technical scheme that the utility model adopts is:
A kind of host transceiver, comprises power module, flow restricter, receiving terminal, transmitting terminal and balanced bridge; Described receiving terminal comprises current detection module and decoder; Described transmitting terminal comprises encoder;
Described power module is connected with current detection module by flow restricter; Described power module is connected with balanced bridge by flow restricter;
Described current detection module is connected with decoder; Described encoder is by balanced bridge and twisted pair line connection.
The second technical scheme that the utility model adopts is:
A kind of receive-transmit system, comprises above-mentioned host transceiver, twisted-pair feeder and more than one from machine transceiver;
Describedly to be connected with host transceiver from machine transceiver by twisted-pair feeder.
The 3rd technical scheme that the utility model adopts is:
A kind of main frame receive-transmit system, comprises multiple above-mentioned host transceiver, first order grader and second level grader;
Two receiving terminals are connected with a first order grader; Three first order graders are connected with a second level grader, and described second level grader is connected with main frame.
The beneficial effects of the utility model are:
The host transceiver that the utility model provides as driving, can change arbitrarily the polarity of bus by balanced bridge, and communication bus can be made nonpolarity, polarity can connect two interface lead, convenient construction arbitrarily.Host transceiver adopts non-return-to-zero communication to be realized by the encoder in transceiver, and difference modes is driven by balanced bridge and realizes, in digital communication systems, and the natural antijamming capability that can improve bus of these two kinds of modes.By arranging current detection module in host transceiver, host transceiver is made to possess bus open circuit and short circuit monitoring capability.By the power consumption of current detecting bus, lower than limits value, electric current illustrates that bus is opened a way, electric current illustrates bus short circuit higher than limits value.The built-in stabilized voltage power supply of transceiver realizes the adaptation to wide input voltage, and therefore the operating voltage range of host transceiver is wider, can adapt to multiple host power supply, reduces power circuit cost.The maximum transmission distance of host transceiver can reach more than 1000 meters, and long-distance transmissions is achieved, as differential mode, NRZ mode, electric current loop type of drive after relying on various ways to improve bus antijamming capability.Another Bus Speed is configurable, reduces Bus Speed and also can improve distance.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of host transceiver of the present utility model;
Fig. 2 is the structural representation of flow restricter of the present utility model;
Fig. 3 is the structural representation of a kind of receive-transmit system of the present utility model;
Fig. 4 is the structural representation of a kind of main frame receive-transmit system of the present utility model;
Label declaration:
10, power module; 20, flow restricter; 30, receiving terminal; 31, current detection module; 32, decoder; 40, transmitting terminal; 41, encoder; 50, balanced bridge.
Embodiment
By describing technology contents of the present utility model in detail, realized object and effect, accompanying drawing is coordinated to be explained below in conjunction with execution mode.
Please refer to Fig. 1, a kind of host transceiver that the utility model provides, comprise power module 10, flow restricter 20, receiving terminal 30, transmitting terminal 40 and balanced bridge 50; Described receiving terminal 30 comprises current detection module 31 and decoder 32; Described transmitting terminal 40 comprises encoder 41;
Described power module is connected with current detection module by flow restricter; Described power module is connected with balanced bridge by flow restricter;
Described current detection module is connected with decoder; Described encoder is by balanced bridge and twisted pair line connection.
The beneficial effects of the utility model are: the host transceiver that the utility model provides as driving, can change arbitrarily the polarity of bus by balanced bridge, and communication bus can be made nonpolarity, polarity can connect two interface lead, convenient construction arbitrarily.Host transceiver adopts non-return-to-zero communication to be realized by the encoder in transceiver, and difference modes is driven by balanced bridge and realizes, in digital communication systems, and the natural antijamming capability that can improve bus of these two kinds of modes.By arranging current detection module in host transceiver, host transceiver is made to possess bus open circuit and short circuit monitoring capability.By the power consumption of current detecting bus, lower than limits value, electric current illustrates that bus is opened a way, electric current illustrates bus short circuit higher than limits value.The built-in stabilized voltage power supply of transceiver realizes the adaptation to wide input voltage, and therefore the operating voltage range of host transceiver is wider, can adapt to multiple host power supply, reduces power circuit cost.The maximum transmission distance of host transceiver can reach more than 1000 meters, and long-distance transmissions is achieved, as differential mode, NRZ mode, electric current loop type of drive after relying on various ways to improve bus antijamming capability.Another Bus Speed is configurable, reduces Bus Speed and also can improve distance.
Further, as shown in Figure 2, described flow restricter is the voltage-stabiliser tube and resistance that are connected in series.
Seen from the above description, the Adj voltage fixed characteristic of output voltage Vout when working according to voltage-stabiliser tube and resistance, wherein exports maximum current=(Vout-Vadj)/resistance.
Further, described current detection module comprises first processor, sampling resistor, the first voltage detection unit and the second voltage detection unit; Described first voltage detection unit is connected with first processor respectively with the second voltage detection unit;
Described first voltage detection unit flows into the first magnitude of voltage before sampling resistor for detecting electric current;
Described second voltage detection unit is for detecting the second magnitude of voltage after outflow of bus current sampling resistor.
Seen from the above description, can learn that electric current is flowing through the magnitude of voltage before and after sampling resistor by the first voltage detection unit and the second voltage detection unit, the voltage difference learnt and flow through before and after sampling resistor can be calculated by first processor, again divided by the resistance of sampling resistor, the current value in now path can be obtained, realize the current detecting to this path.
Further, described decoder comprises the first voltage input end, the second voltage input end, the second processor and decoder module;
Described first voltage input end is connected with the first voltage detection unit;
Described second voltage input end is connected with the second voltage detection unit;
Described first voltage input end is connected with the second processor respectively with the second voltage input end;
Described second processor is connected with decoder module.
Seen from the above description, the change of the operating current of bus is converted to digital signal, and fault-signal.Sampling resistor both end voltage can be obtained poor by the first voltage input end and the second voltage input end, obtain load current change (being the effective information sent from the transmitting terminal of machine transceiver) by the second processor, data form is on demand sent after decoding by recycling decoder module.
Further, described balanced bridge comprises the first electronic switch, the second electronic switch, the 3rd electronic switch and the 4th electronic switch;
Described first electronic switch, the second electronic switch, the 3rd electronic switch are connected with decoder respectively with the 4th electronic switch.
Seen from the above description, be connected with decoder respectively with the 4th electronic switch by the first electronic switch, the second electronic switch, the 3rd electronic switch, the break-make of four electronic switches can be controlled, and then change polarity of voltage on twisted-pair feeder.
Further, described flow restricter is by the first electronic switch of being connected in series and the second electronic switch ground connection; Described flow restricter is by the 3rd electronic switch that is connected in series and the 4th electronic switch ground connection;
The path of described first electronic switch and the second electronic switch is provided with first make contact; Described first make contact and twisted pair line connection;
The path of described 3rd electronic switch and the 4th electronic switch is provided with the second contact point; Described second contact point and twisted pair line connection.
Refer to Fig. 3, a kind of receive-transmit system that the utility model provides, comprise above-mentioned host transceiver, twisted-pair feeder and more than one from machine transceiver;
Describedly to be connected with host transceiver from machine transceiver by twisted-pair feeder.
Host transceiver is by twisted-pair feeder and multiple from machine transceiver communications, host transceiver and have specific communication protocol between machine transceiver, there is unique identification to arranging from machine transceiver by numbering or address etc., make multiple from separate communicating with host transceiver between machine transceiver, can prevent from the signal disturbing between machine transceiver.
Refer to Fig. 4, a kind of main frame receive-transmit system that the utility model provides, comprise multiple above-mentioned host transceiver, first order grader and second level grader;
Two receiving terminals are connected with a first order grader; Three first order graders are connected with a second level grader, and described second level grader is connected with main frame.
Further, between second level grader and main frame, third level grader is also comprised; Three second level graders are connected with a third level grader; Described third level grader is connected with main frame.
Interconnective first order grader and second level grader is increased between host transceiver and main frame, the data first received host transceiver receiving terminal by first order grader and second level grader carry out classification process, can improve the data-handling efficiency of main frame.Through experimental results demonstrate, when the quantity of first order grader and second level grader is 3:1, the data-handling efficiency of main frame is the highest, than the improved efficiency about 5% of prior art.
A kind of receive-transmit system that the utility model provides, comprises above-mentioned main frame receive-transmit system, twisted-pair feeder and more than one from machine transceiver;
Describedly to be connected with main frame receive-transmit system from machine transceiver by twisted-pair feeder.
Main frame receive-transmit system is by twisted-pair feeder and multiple from machine transceiver communications, host transceiver and have specific communication protocol between machine transceiver, there is unique identification to arranging from machine transceiver by numbering or address etc., make multiple from separate communicating with host transceiver between machine transceiver, can prevent from the signal disturbing between machine transceiver.
Please refer to Fig. 1-3, embodiment one of the present utility model is:
A kind of host transceiver that the utility model provides, comprises power module, flow restricter, receiving terminal, transmitting terminal and balanced bridge; Described receiving terminal comprises current detection module and decoder; Described transmitting terminal comprises encoder;
Described power module is connected with current detection module by flow restricter; Described power module is connected with balanced bridge by flow restricter; Wherein, described flow restricter is the voltage-stabiliser tube and resistance that are connected in series.The Adj voltage fixed characteristic of output voltage Vout when working according to voltage-stabiliser tube and resistance, wherein exports maximum current=(Vout-Vadj)/resistance.
Wherein, described current detection module comprises first processor, sampling resistor, the first voltage detection unit and the second voltage detection unit; Described first voltage detection unit is connected with first processor respectively with the second voltage detection unit; Described first voltage detection unit flows into the first magnitude of voltage before sampling resistor for detecting electric current; Described second voltage detection unit is for detecting the second magnitude of voltage after outflow of bus current sampling resistor.Can learn that electric current is flowing through the magnitude of voltage before and after sampling resistor by the first voltage detection unit and the second voltage detection unit, the voltage difference learnt and flow through before and after sampling resistor can be calculated by first processor, again divided by the resistance of sampling resistor, the current value in now path can be obtained, realize the current detecting to this path.
Described current detection module is connected with decoder; Wherein, described decoder comprises the first voltage input end, the second voltage input end, the second processor and decoder module; Described first voltage input end is connected with the first voltage detection unit; Described second voltage input end is connected with the second voltage detection unit; Described first voltage input end is connected with the second processor respectively with the second voltage input end; Described second processor is connected with decoder module.Convert the change of the operating current of bus to digital signal, and fault-signal.Sampling resistor both end voltage can be obtained poor by the first voltage input end and the second voltage input end, obtain load current change (being the effective information sent from the transmitting terminal of machine transceiver) by the second processor, data form is on demand sent after decoding by recycling decoder module.
Described encoder is by balanced bridge and twisted pair line connection.Wherein, described balanced bridge comprises the first electronic switch, the second electronic switch, the 3rd electronic switch and the 4th electronic switch; Described first electronic switch, the second electronic switch, the 3rd electronic switch are connected with decoder respectively with the 4th electronic switch.Be connected with decoder respectively with the 4th electronic switch by the first electronic switch, the second electronic switch, the 3rd electronic switch, the break-make of four electronic switches can be controlled, and then change polarity of voltage on twisted-pair feeder.
Described flow restricter is by the first electronic switch of being connected in series and the second electronic switch ground connection; Described flow restricter is by the 3rd electronic switch that is connected in series and the 4th electronic switch ground connection; The path of described first electronic switch and the second electronic switch is provided with first make contact; Described first make contact and twisted pair line connection; The path of described 3rd electronic switch and the 4th electronic switch is provided with the second contact point; Described second contact point and twisted pair line connection.
Refer to Fig. 1-4, embodiment two of the present utility model is:
The present embodiment two increases first order grader and second level grader on the basis of above-described embodiment one; Form main frame receive-transmit system by multiple above-mentioned host transceiver, first order grader and second level grader, two receiving terminals are connected with a first order grader; Three first order graders are connected with a second level grader, and described second level grader is connected with main frame.Interconnective first order grader and second level grader is increased between host transceiver and main frame, the data first received host transceiver receiving terminal by first order grader and second level grader carry out classification process, can improve the data-handling efficiency of main frame.Through experimental results demonstrate, when the quantity of first order grader and second level grader is 3:1, the data-handling efficiency of main frame is the highest, than the improved efficiency about 5% of prior art.
Further scheme is, between second level grader and main frame, also comprise third level grader; Three second level graders are connected with a third level grader; Described third level grader is connected with main frame.
Because main frame adopts non-return-to-zero mode activated bus, bus obtains continued power ability, can obtain power supply, reduce the power supply cost of system from machine from bus.Bus is nonpolarity, arbitrarily can access bus, decrease construction cost from machine.Drive bus owing to have employed difference modes, therefore antijamming capability is superior.Contrast RS485 bus transceiver, 485 transceiver advantages are not for distinguish main frame from machine transceiver architecture, and shortcoming is that bus has polarity cause construction inconvenient and cannot provide bus-powered ability.Contrast RS232 bus transceiver, the advantage of 232 transceivers does not distinguish main frame from machine transceiver architecture, shortcoming is bus is not difference modes poor anti jamming capability, needs at least 3 lines to realize two-way communication, only supports an access from machine and supporting bus is not powered.
In sum, a kind of host transceiver, receive-transmit system and the main frame receive-transmit system that provide of the utility model.The host transceiver that the utility model provides as driving, can change arbitrarily the polarity of bus by balanced bridge, and communication bus can be made nonpolarity, polarity can connect two interface lead, convenient construction arbitrarily.Host transceiver adopts non-return-to-zero communication to be realized by the encoder in transceiver, and difference modes is driven by balanced bridge and realizes, in digital communication systems, and the natural antijamming capability that can improve bus of these two kinds of modes.By arranging current detection module in host transceiver, host transceiver is made to possess bus open circuit and short circuit monitoring capability.By the power consumption of current detecting bus, lower than limits value, electric current illustrates that bus is opened a way, electric current illustrates bus short circuit higher than limits value.The built-in stabilized voltage power supply of transceiver realizes the adaptation to wide input voltage, and therefore the operating voltage range of host transceiver is wider, can adapt to multiple host power supply, reduces power circuit cost.The maximum transmission distance of host transceiver can reach more than 1000 meters, and long-distance transmissions is achieved, as differential mode, NRZ mode, electric current loop type of drive after relying on various ways to improve bus antijamming capability.Another Bus Speed is configurable, reduces Bus Speed and also can improve distance.
The foregoing is only embodiment of the present utility model; not thereby the scope of the claims of the present utility model is limited; every equivalents utilizing the utility model specification and accompanying drawing content to do; or be directly or indirectly used in relevant technical field, be all in like manner included in scope of patent protection of the present utility model.
Claims (9)
1. a host transceiver, is characterized in that, comprises power module, flow restricter, receiving terminal, transmitting terminal and balanced bridge; Described receiving terminal comprises current detection module and decoder; Described transmitting terminal comprises encoder;
Described power module is connected with current detection module by flow restricter; Described power module is connected with balanced bridge by flow restricter;
Described current detection module is connected with decoder; Described encoder is by balanced bridge and twisted pair line connection.
2. host transceiver according to claim 1, is characterized in that, described flow restricter is the voltage-stabiliser tube and resistance that are connected in series.
3. host transceiver according to claim 1, is characterized in that, described current detection module comprises first processor, sampling resistor, the first voltage detection unit and the second voltage detection unit; Described first voltage detection unit is connected with first processor respectively with the second voltage detection unit;
Described first voltage detection unit flows into the first magnitude of voltage before sampling resistor for detecting electric current;
Described second voltage detection unit is for detecting the second magnitude of voltage after outflow of bus current sampling resistor.
4. host transceiver according to claim 3, is characterized in that, described decoder comprises the first voltage input end, the second voltage input end, the second processor and decoder module;
Described first voltage input end is connected with the first voltage detection unit;
Described second voltage input end is connected with the second voltage detection unit;
Described first voltage input end is connected with the second processor respectively with the second voltage input end;
Described second processor is connected with decoder module.
5. host transceiver according to claim 1, is characterized in that, described balanced bridge comprises the first electronic switch, the second electronic switch, the 3rd electronic switch and the 4th electronic switch;
Described first electronic switch, the second electronic switch, the 3rd electronic switch are connected with decoder respectively with the 4th electronic switch.
6. host transceiver according to claim 5, is characterized in that, described flow restricter is by the first electronic switch of being connected in series and the second electronic switch ground connection; Described flow restricter is by the 3rd electronic switch that is connected in series and the 4th electronic switch ground connection;
The path of described first electronic switch and the second electronic switch is provided with first make contact; Described first make contact and twisted pair line connection;
The path of described 3rd electronic switch and the 4th electronic switch is provided with the second contact point; Described second contact point and twisted pair line connection.
7. a receive-transmit system, is characterized in that, comprises the host transceiver described in claim 1-6 any one, twisted-pair feeder and more than one from machine transceiver;
Describedly to be connected with host transceiver from machine transceiver by twisted-pair feeder.
8. a main frame receive-transmit system, is characterized in that, comprises the host transceiver described in multiple claim 1-6 any one, first order grader and second level grader;
Two receiving terminals are connected with a first order grader; Three first order graders are connected with a second level grader, and described second level grader is connected with main frame.
9. main frame receive-transmit system according to claim 8, is characterized in that, between second level grader and main frame, also comprise third level grader; Three second level graders are connected with a third level grader; Described third level grader is connected with main frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520867192.6U CN205070992U (en) | 2015-11-03 | 2015-11-03 | Host computer transceiver, receiving and dispatching system and host computer receiving and dispatching system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520867192.6U CN205070992U (en) | 2015-11-03 | 2015-11-03 | Host computer transceiver, receiving and dispatching system and host computer receiving and dispatching system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205070992U true CN205070992U (en) | 2016-03-02 |
Family
ID=55397492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520867192.6U Active CN205070992U (en) | 2015-11-03 | 2015-11-03 | Host computer transceiver, receiving and dispatching system and host computer receiving and dispatching system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205070992U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105391471A (en) * | 2015-11-03 | 2016-03-09 | 福州东日信息技术有限公司 | Host transceiver, transmitting and receiving system and host transmitting and receiving system |
-
2015
- 2015-11-03 CN CN201520867192.6U patent/CN205070992U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105391471A (en) * | 2015-11-03 | 2016-03-09 | 福州东日信息技术有限公司 | Host transceiver, transmitting and receiving system and host transmitting and receiving system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN205844970U (en) | A kind of display terminal with USB Type C interface and display system | |
| CN205038637U (en) | RS232 and RS485422 interface converter based on microprocessor | |
| CN102169472B (en) | RS485 bus interface circuit | |
| CN105471569B (en) | Multinode electric current loop full-duplex communication circuit | |
| CN205070992U (en) | Host computer transceiver, receiving and dispatching system and host computer receiving and dispatching system | |
| CN206975454U (en) | Reservoir gate remote monitoring system | |
| CN210137320U (en) | RS485 circuit capable of automatically switching receiving and transmitting states | |
| CN104077260B (en) | A kind of concentrator M BUS host communication interface arrangements | |
| CN205142206U (en) | Switch circuit of communication direction | |
| CN209184614U (en) | Instrument bus host communication circuit | |
| CN205070989U (en) | Follow quick -witted transceiver, receiving and dispatching system and follow quick -witted receiving and dispatching system | |
| CN105391471A (en) | Host transceiver, transmitting and receiving system and host transmitting and receiving system | |
| CN206975450U (en) | A kind of mbus circuits of opto-electrical direct reader | |
| CN104991198A (en) | Battery tour inspection processing circuit based on ARM platform multichannel switching | |
| CN103507658B (en) | Battery-driven car and bus control system thereof | |
| CN203149564U (en) | Serial-port automatic switching device | |
| CN202586495U (en) | Intelligent transformer station lightning arrester on-line monitoring IED based on ARM + DSP | |
| CN209311880U (en) | A kind of switch acquisition control device | |
| CN202126687U (en) | RS485 bus interface circuit | |
| CN105262501A (en) | Slave computer receiver, receiving system and slave computer receiving and sending system | |
| CN202798661U (en) | Industrial control bus structure | |
| CN206077379U (en) | Repeat circuit and half duplex communication circuit for half duplex communication | |
| CN201781265U (en) | Motor differential protection device | |
| CN203243323U (en) | Apparatus used for long-distance transmission of USB signal | |
| CN205958995U (en) | Wired teletransmission valve accuse direct - reading photoelectric water meter's electrical system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |