CN205029662U - Low -cost HART -FSK sends receiving circuit - Google Patents
Low -cost HART -FSK sends receiving circuit Download PDFInfo
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- CN205029662U CN205029662U CN201520836023.6U CN201520836023U CN205029662U CN 205029662 U CN205029662 U CN 205029662U CN 201520836023 U CN201520836023 U CN 201520836023U CN 205029662 U CN205029662 U CN 205029662U
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Abstract
The utility model relates to a low -cost HART -FSK sends receiving circuit, include: master control treater, output modulator filter circuit, input demodulator filtering comparison circuit, power supply circuit and HART bus circuit, the master control treater links to each other with output modulator filter circuit and input demodulator filtering comparison circuit respectively, output modulator filter circuit and input demodulator filtering comparison circuit link to each other with HART bus circuit respectively, power supply circuit links to each other with master control treater, output modulator filter circuit and input demodulator filtering comparison circuit respectively. The utility model provides a low -cost HART -FSK sends receiving circuit, simple structure need not the HART chip, can accomplish the HART communication, reduces product hardware cost effectively.
Description
Technical field
The utility model relates to industry spot instrument field, particularly a kind of low cost HART-FSK transmitter/receiver circuit.
Background technology
Fieldbus is the focus of current Automatic Measurement Technique development.By fieldbus, digital communication technology can extend to field level instrument, brings a revolution to the hierarchy of control.Bussing technique becomes inexorable trend to total digitalization development, and for meeting from simulation to digital transition, the HART agreement taking into account analog-and digital-two kinds of communication modes is arisen at the historic moment.In the application of industry spot instrument, many users require that field instrument has HART agreement, so that produced on-site operation.At present, the chip price of HART agreement is all higher, is unfavorable for the competitiveness improving product, requires that the HART agreement of a low cost of design sends and receiver in the case, provides low cost HART implementation.
Summary of the invention
The purpose of this utility model is to provide a kind of low cost HART-FSK transmitter/receiver circuit, to overcome the defect existed in prior art; The utility model structure is simple, is easy to realize.
For achieving the above object, the technical solution of the utility model is: a kind of low cost HART-FSK transmitter/receiver circuit, comprising: a main control processor, an output modulator filter circuit, an input demodulator filtering comparison circuit, a power circuit and a HART bus circuit; Described main control processor is connected with described output modulator filter circuit and described input demodulator filtering comparison circuit respectively; Described output modulator filter circuit and described input demodulator filtering comparison circuit are connected with described HART bus circuit respectively; Described power circuit is connected with described main control processor, described output modulator filter circuit and described input demodulator filtering comparison circuit respectively.
In the utility model one embodiment, described main control processor comprises a STM32L152.
In the utility model one embodiment, described output modulator filter circuit comprises a micro-control processor; The end of described micro-control processor to be connected with an amplifier output and through the 4th capacity earth through the first electric capacity respectively; The reverse input end of described amplifier is connected with the output of described amplifier; The positive input of described amplifier to be connected with described main control processor and through the second grounding through resistance through the first resistance respectively; The end of described micro-control processor and end are corresponding to the second electric capacity and the 3rd capacity earth respectively; The OUT end of described micro-control processor is held with the first diode anode and described HART bus circuit TEST respectively and is connected; Described first diode cathode is connected with the 3rd resistance one end, and ground connection; The described 3rd resistance other end is connected with transistor emitter; Described transistor base is held with the BASE of described micro-control processor and is connected; Described transistor collector accesses described HART bus circuit LOOP+ through the 5th electric capacity one end and the second diode respectively and holds; The described 5th electric capacity other end is connected with the 3rd diode anode, and accesses described HART bus circuit TEST and hold; Described 3rd diode cathode is held with described HART bus circuit LOOP-and is connected.
In the utility model one embodiment, described input demodulator filtering comparison circuit comprises a comparator; The output of described comparator is connected with described main control processor through one end of the 4th resistance; First output of power circuit described in another termination of described 4th resistance; The reverse input end of described comparator is connected with one end of the 6th electric capacity and one end of the 5th resistance respectively; The other end of described 6th electric capacity accesses the anode of the second diode through one end of the 6th resistance and the 7th electric capacity; The negative electrode of described second diode accesses described HART bus circuit LOOP+ and holds; The other end of described 5th resistance is connected with the second output of described power circuit and the 7th resistance one end respectively; The described 7th resistance other end is connected with the positive input of described comparator and one end of the 8th resistance respectively; The other end of described 8th resistance is connected with the output of described comparator.
In the utility model one embodiment, described power circuit comprises a power supply chip circuit; Described power supply chip circuit Vout holds the first output as described power circuit; The Vout end of described power supply chip circuit is connected through the negative electrode of the 9th resistance with the 4th diode, and as the second output of described power circuit; The anode of described 4th diode is connected with the 8th electric capacity one end, and ground connection; The described 8th electric capacity other end is connected with the negative electrode of described 4th diode.
Compared to prior art, the utility model has following beneficial effect: a kind of low cost HART-FSK transmitter/receiver circuit that the utility model proposes, and structure is simple, without the need to HART chip, can HART communication be completed, effectively reduce products-hardware cost, improve the competitiveness of HART product.
Accompanying drawing explanation
Fig. 1 is the circuit theory diagrams of a kind of low cost HART-FSK transmitter/receiver circuit in the utility model.
Fig. 2 is the circuit diagram of a kind of low cost HART-FSK transmitter/receiver circuit in the utility model one embodiment.
Embodiment
Below in conjunction with accompanying drawing, the technical solution of the utility model is specifically described.
The utility model provides a kind of low cost HART-FSK transmitter/receiver circuit, as shown in Figure 1 and Figure 2, comprising: a main control processor, an output modulator filter circuit, an input demodulator filtering comparison circuit, a power circuit and a HART bus circuit; Main control processor is respectively with output modulator filter circuit and input demodulator filtering comparison circuit and be connected; Output modulator filter circuit and input demodulator filtering comparison circuit are connected with HART bus circuit respectively; Power circuit is respectively with main control processor, output modulator filter circuit and input demodulator filtering comparison circuit and be connected.
Further, in the present embodiment, as shown in Figure 2, main control processor comprises a STM32L152.
Further, in the present embodiment, as shown in Figure 2, output modulator filter circuit comprises a micro-control processor; The C2 end of micro-control processor to be connected with an amplifier output and through the 4th electric capacity C48 ground connection through the first electric capacity C46 respectively; The reverse input end of amplifier is connected with the output of amplifier; The positive input of amplifier to be connected with main control processor and through the second resistance R39 ground connection through the first resistance R35 respectively; The C3 end of micro-control processor and C1 end are corresponding to the second electric capacity C47 and the 3rd electric capacity C49 ground connection respectively; The OUT end of micro-control processor is held with the first diode D15 anode and HART bus circuit TEST respectively and is connected; First diode D15 negative electrode is connected with the 3rd resistance R36 one end, and ground connection; The 3rd resistance R36 other end is connected with triode Q10 emitter; Triode Q10 base stage is held with the BASE of micro-control processor and is connected; Triode Q10 collector electrode accesses HART bus circuit LOOP+ end through the 5th electric capacity C32 one end and the second diode D13 respectively; The 5th electric capacity C32 other end is connected with the 3rd diode D14 anode, and accesses HART bus circuit TEST and hold; 3rd diode D14 negative electrode is held with HART bus circuit LOOP-and is connected.
Further, in the present embodiment, as shown in Figure 2, input demodulator filtering comparison circuit and comprise a comparator U13A; The output of comparator U13A is connected with main control processor through one end of the 4th resistance R33; First output of another termination power circuit of the 4th resistance R33; The reverse input end of comparator U13A is connected with one end of the 6th electric capacity C44 and one end of the 5th resistance R37 respectively; The other end of the 6th electric capacity C44 accesses the anode of the second diode through one end of the 6th resistance R40 and the 7th electric capacity C45; The negative electrode access HART bus circuit LOOP+ end of the second diode; The other end of the 5th resistance R37 is connected with the second output of power circuit and the 7th resistance R38 one end respectively; The 7th resistance R38 other end is connected with the positive input of comparator U13A and one end of the 8th resistance R34 respectively; The other end of the 8th resistance R34 is connected with the output of comparator U13A.
Further, in the present embodiment, as shown in Figure 2, power circuit comprises a power supply chip circuit; Power supply chip circuit Vout holds the first output as power circuit; The Vout end of power supply chip circuit is connected with the negative electrode of the 4th diode U12 through the 9th resistance R32, and as the second output of power circuit; The anode of the 4th diode U12 is connected with the 8th electric capacity C30 one end, and ground connection; The 8th electric capacity C30 other end is connected with the negative electrode of the 4th diode U12.
A kind of low cost HART-FSK transmitter/receiver circuit understood the utility model further to allow those skilled in the art and propose; be described below in conjunction with existing software and control method; existing software involved in this declarative procedure and control method are not all the objects that the utility model is protected, and the utility model only protects structure and the annexation thereof of this circuit.
Main control processor transfers character to be sent to HART-FSK number format, then transfers HART-FSK analog format to by output modulation filter circuit, sends to HART bus; Character signal to be received transfers HART-FSK number format by HART bus to through input demodulation filtering comparison circuit, then transfers reception character to.The utility model adopts software simulation technology, by transmission and the reception of software simulating HART agreement, reduces the cost of product, realizes also realizing HART communication without HART interface chip.
Main control processor first transfers character to UART character format, is defined as 1 start bit+8 bit data+1, position odd parity bit+1 position of rest, then transfers bit digital to HART-FSK form.Bit=0, by the bit width of baud rate 1200bit/s, transfers 2200hz output waveform to, amounts to output 2200/1200 square wave; Bit=1, by the bit width of baud rate 1200bit/s, transfers 1200hz output waveform to, amounts to output 1200/1200 square wave.Export the waveform that square wave is transferred to HART-FSK by modulation filter circuit.HART-FSK analog signal is transferred to square wave and exports by input demodulation filtering comparison circuit.Above 2 data transfer directions to phase, can realize the bidirectional communication function of character data.
Further, in the present embodiment, main control processor transfers square wave to bit data, wherein 1 1200hz square wave " bit=1 ", and 2200/1200 2200hz square wave transfers to " bit=0 ", then transfers reception character to according to the form of UART.
Further, in the present embodiment, main control processor take STM32L152 as main control chip.Its data export, and by built-in 32 bit timing devices, precisely export HART-FSK square wave, then by filter circuit, the exportable FSK physical layer signal meeting HART protocol requirement completely.Its data input, and by demodulator filtering comparison circuit (band return difference), detect square, then by the seizure of STM32L152 main control chip, identification, conversion, realize the process from analog to digital.
Be more than preferred embodiment of the present utility model, all changes done according to technical solutions of the utility model, when the function produced does not exceed the scope of technical solutions of the utility model, all belong to protection range of the present utility model.
Claims (5)
1. a low cost HART-FSK transmitter/receiver circuit, is characterized in that, comprising: a main control processor, an output modulator filter circuit, an input demodulator filtering comparison circuit, a power circuit and a HART bus circuit; Described main control processor is connected with described output modulator filter circuit and described input demodulator filtering comparison circuit respectively; Described output modulator filter circuit and described input demodulator filtering comparison circuit are connected with described HART bus circuit respectively; Described power circuit is connected with described main control processor, described output modulator filter circuit and described input demodulator filtering comparison circuit respectively.
2. a kind of low cost HART-FSK transmitter/receiver circuit according to claim 1, it is characterized in that, described main control processor comprises a STM32L152.
3. a kind of low cost HART-FSK transmitter/receiver circuit according to claim 1, is characterized in that, described output modulator filter circuit comprises a micro-control processor; The end of described micro-control processor to be connected with an amplifier output and through the 4th capacity earth through the first electric capacity respectively; The reverse input end of described amplifier is connected with the output of described amplifier; The positive input of described amplifier to be connected with described main control processor and through the second grounding through resistance through the first resistance respectively; The end of described micro-control processor and end are corresponding to the second electric capacity and the 3rd capacity earth respectively; The OUT end of described micro-control processor is held with the first diode anode and described HART bus circuit TEST respectively and is connected; Described first diode cathode is connected with the 3rd resistance one end, and ground connection; The described 3rd resistance other end is connected with transistor emitter; Described transistor base is held with the BASE of described micro-control processor and is connected; Described transistor collector accesses described HART bus circuit LOOP+ through the 5th electric capacity one end and the second diode respectively and holds; The described 5th electric capacity other end is connected with the 3rd diode anode, and accesses described HART bus circuit TEST and hold; Described 3rd diode cathode is held with described HART bus circuit LOOP-and is connected.
4. a kind of low cost HART-FSK transmitter/receiver circuit according to claim 1, is characterized in that, described input demodulator filtering comparison circuit comprises a comparator; The output of described comparator is connected with described main control processor through one end of the 4th resistance; First output of power circuit described in another termination of described 4th resistance; The reverse input end of described comparator is connected with one end of the 6th electric capacity and one end of the 5th resistance respectively; The other end of described 6th electric capacity accesses the anode of the second diode through one end of the 6th resistance and the 7th electric capacity; The negative electrode of described second diode accesses described HART bus circuit LOOP+ and holds; The other end of described 5th resistance is connected with the second output of described power circuit and the 7th resistance one end respectively; The described 7th resistance other end is connected with the positive input of described comparator and one end of the 8th resistance respectively; The other end of described 8th resistance is connected with the output of described comparator.
5. a kind of low cost HART-FSK transmitter/receiver circuit according to claim 4, is characterized in that, described power circuit comprises a power supply chip circuit; Described power supply chip circuit Vout holds the first output as described power circuit; The Vout end of described power supply chip circuit is connected through the negative electrode of the 9th resistance with the 4th diode, and as the second output of described power circuit; The anode of described 4th diode is connected with the 8th electric capacity one end, and ground connection; The described 8th electric capacity other end is connected with the negative electrode of described 4th diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520836023.6U CN205029662U (en) | 2015-10-27 | 2015-10-27 | Low -cost HART -FSK sends receiving circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520836023.6U CN205029662U (en) | 2015-10-27 | 2015-10-27 | Low -cost HART -FSK sends receiving circuit |
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| Publication Number | Publication Date |
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| CN205029662U true CN205029662U (en) | 2016-02-10 |
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| CN201520836023.6U Active CN205029662U (en) | 2015-10-27 | 2015-10-27 | Low -cost HART -FSK sends receiving circuit |
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- 2015-10-27 CN CN201520836023.6U patent/CN205029662U/en active Active
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