CN204947320U - A kind of chip structure reducing semiconductor laser encapsulation stress - Google Patents
A kind of chip structure reducing semiconductor laser encapsulation stress Download PDFInfo
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- CN204947320U CN204947320U CN201520663400.0U CN201520663400U CN204947320U CN 204947320 U CN204947320 U CN 204947320U CN 201520663400 U CN201520663400 U CN 201520663400U CN 204947320 U CN204947320 U CN 204947320U
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Abstract
The utility model relates to a kind of chip structure reducing semiconductor laser encapsulation stress.Described chip structure is in the gain waveguide type semiconductor laser structure with pulse current injectingt region and luminance gain region, etch 2 grooves extended along laser generation direction, pulse current injectingt region is positioned in the middle of 2 grooves, by suitably strengthening the A/F of groove and regulating and controlling A/F and depth ratio, solder during follow-up encapsulation is fully entered and to infiltrate in the groove of both sides, luminance gain region and to decrease the solder of both sides, luminance gain region, residual stress obviously reduces, and sharp optical wavelength of penetrating is single and stable; Improve conductive and heat-conductive ability simultaneously.The utility model method does not increase operation and manufacturing cost, is beneficial to commercial Application.
Description
Technical field
The utility model relates to a kind of chip structure for reducing semiconductor laser encapsulation stress, belongs to semiconductor laser chip technical field.
Background technology
Not only high-output power is required for semiconductor laser, also requires single and stable wavelength, to ensure the irradiation of laser, conduction or pumping effect.The structure of the semiconductor laser chip generally adopted at present as shown in Figure 1, on semiconductor chip 1, adopt metal organic vapor method to grow the first coating layer 2, first light waveguide-layer 3, light emitting active layer 4, second light waveguide-layer 5 and the second coating layer 6 in turn, then utilize the method for photoetching and vapor phase epitaxial growth, etching forms luminance gain region A after removing part second light waveguide-layer 5 and the second coating layer 6, then part covers and injects barrier layer 7, deposit P face electric contacting layer 8 again, form pulse current injectingt region W, finally deposit N face electric contacting layer 9.By the confinement effect of pulse current injectingt region W and gain of light region A to electronics and photon, the power output of improving laser device and stability.Chip of laser needs to be sintered to heat sink upper use by solder, and general technology is sintered and alloy solder layer and P face electric contacting layer 8.Brazing metal deformation in the heating and cooling process of sintering is much bigger compared with semiconductor light emitting layer, and the solder in both sides, luminance gain region can produce significant residual stress to luminance gain region A after sintering, as shown in fig. 1 by means of arrows.
In the quantum well structure that current semiconductor laser generally adopts, quantum size effect makes the degeneracy of being with of the heavy hole of active area materials and light hole remove, and this symmetry corresponded in crystal changes, and can cause the anisotropy of transition matrix element.When trap material is subject to the effects of strain being parallel or perpendicular to direction, trap face, the heavy hole energy level of its top of valence band and the position of light hole energy level, curvature and effective mass all will change.Therefore, the stress that luminance gain region is subject to not only affects threshold current and the enhancement effect of semiconductor laser, also the physical characteristic of shoot laser will be changed, the wavelength of laser, peak position and polarization mode all will change, and generally show as optical maser wavelength and occur multiplet of doublet and constantly conversion (as shown in Figure 3).And normally work and required be single glow peak and the stable laser of wavelength location.Thus, need to optimize chip structure, reduce the solder residue stress after semiconductor laser sintering.
To the concern of Output of laser glow peak and the stability of wavelength and the encapsulation stress of noise spectra of semiconductor lasers chip in existing semiconductor laser, be from the epitaxial structure in chip or fit with chip heat sinkly modify and optimize.And in practical application chip of laser by solder mount heat sink on, suffered effect of stress is also due to solder and heat sink distortion and is delivered to chip light emitting layer via solder.Therefore, prior art well solves the problem that lasing fluorescence peak wavelength stability and encapsulation stress effectively reduce.
Summary of the invention
For the deficiencies in the prior art, the utility model provides a kind of semiconductor laser chip structure with low encapsulation stress and high Laser output stability, to solve the laser multiplet of doublet and the problems such as wavelength location instability that in prior art, semiconductor laser chip causes due to sintering residual stress after packaging.
The technical solution of the utility model is as follows:
A kind of chip structure reducing semiconductor laser encapsulation stress, be included in the gain waveguide type semiconductor laser structure with pulse current injectingt region and luminance gain region that on semiconductor substrate, extension is formed, and there are 2 grooves extended along laser generation direction, described luminance gain region is arranged at the centre position of 2 grooves.
Preferably, the toatl proportion that the width sum of described 2 groove opening accounts for Chip-wide controls at 5-30%, and the A/F of described groove and the ratio of the degree of depth are at 2-50.By suitably strengthening the A/F of groove and regulating and controlling A/F and depth ratio, solder during follow-up encapsulation is fully entered and to infiltrate in groove and to decrease the solder of both sides, luminance gain region, ensure the conductive and heat-conductive ability of chip sintered surface, thus the residual stress produced after obviously reducing sintering encapsulation, obtain the chip of laser that luminous peak position is single and stable.
Preferably, the width of described semiconductor laser chip is 100-500 μm, and the width in luminance gain region is the 20%-80% of Chip-wide, and the width in luminance gain region is generally 20-200 μm.
Preferably, the cross sectional shape of described groove is square, trapezoidal or semicircle.When adopting trapezoidal, under groove, the ratio of the length of side and upper shed is at 50%-150%.2 preferably described groove shapes, measure-alike.
Preferably, the width of groove opening is 5-50 μm, and the toatl proportion accounting for Chip-wide controls at 5-30%, to reduce the solder around luminance gain region;
Preferably, the degree of depth of groove is 0.5-5 μm, and the width of groove and the ratio of the degree of depth are at 2-50, and the width of preferred groove and the ratio of the degree of depth are at 10-20 further; To ensure that solder fully enters and infiltrates trench interiors.
According to the utility model, preferably, the A/F of groove is 15-30 μm, and the degree of depth is 1-2 μm.
According to the utility model, described gain waveguide type semiconductor laser structure grows in turn on the semiconductor substrate to have the first coating layer, the first light waveguide-layer, light emitting active layer, the second light waveguide-layer and the second coating layer; 2 grooves extended along laser generation direction are formed at the second cover surface chemical wet etching, gash depth reaches the second light waveguide-layer of at least whole second coating layer and suitable thickness, between 2 grooves part luminance gain region on leave electrical pumping window, second coating layer of remainder has barrier layer, is namely pulse current injectingt region directly over luminance gain region.Also deposit P face electric contacting layer and N face electric contacting layer, form chip structure of the present utility model.
According to the utility model, described groove utilizes photoetching process to carry out etching at chip surface and is formed, and at least etches away the second coating layer of described trench region and the second light waveguide-layer of suitable thickness; Or any layer etched in light emitting active layer, the first light waveguide-layer, the first coating layer, or etch into semiconductor substrate layer.
In the utility model, described semiconductor chip is selected from GaAs substrate, SiC substrate, InP-base sheet or GaN base sheet.Adopt AlGaInP or AlGaInAs material system to obtain the excitation wavelength of 0.6-1 μm, adopt adaptive light waveguide-layer and coating layer material.According to the laser of required wavelength, suitably determine the thickness of each layer, composition and doping etc.
The beneficial effects of the utility model:
The utility model passes through the outer shape of chip and the design optimization of structure, adopt the chip structure of the groove of both sides, luminance gain region design proper width and the degree of depth, the solder of subsequent packaging procedures is fully entered and infiltrates realization in groove to regulate and control the distribution of the solder of chip surface, decrease the solder of both sides, luminance gain region, reduce effect of stress suffered in the use procedure of chip after sintering has encapsulated, obtain the minimizing semiconductor laser encapsulation stress of low-cost high-efficiency and promote the wavelength unicity of shoot laser and the chip structure of stability.Simultaneously whole P face electric contacting layer by solder fit to heat sink on, to ensure that conductive and heat-conductive ability can not reduce because of the introducing of groove.
The chip structure that the utility model reduces encapsulation stress utilizes existing technique to manufacture, and without the need to extra equipment, therefore can not bring the increase of manufacturing cost, is easy to realize.
Accompanying drawing explanation
Fig. 1 is the structural representation of the original semiconductor laser chip of comparative example.A is luminance gain region, and W is pulse current injectingt region.Arrow represents both sides solder after sintering to the residual stress that luminance gain region A produces; Fig. 2 is the structural representation of the utility model semiconductor laser chip.A is luminance gain region, and W is pulse current injectingt region.In Fig. 1, Fig. 2,1, semiconductor chip, the 2, first coating layer, the 3, first light waveguide-layer, 4, light emitting active layer, the 5, second light waveguide-layer, the 6, second coating layer, 7, inject barrier layer, 8, P face electric contacting layer, 9, N face electric contacting layer; In Fig. 2, the second coating layer 6 is divided into three parts after photoetching.
Fig. 3 is that after the encapsulation of comparative example original semiconductor laser chip, laser wavelength presents bimodal situation, has two glow peaks closed on.Fig. 4 is that after the semiconductor laser chip encapsulation of the utility model embodiment 1, laser wavelength presents single crest situation.
Embodiment
Below in conjunction with embodiment, comparative example and accompanying drawing, the utility model is described further.But be not limited thereto.
Embodiment 1:
Reduce a chip structure for semiconductor laser encapsulation stress, as shown in Figure 2.
GaAs substrate 1 there are successively AlGaAs first light waveguide-layer 3 of AlGaAs first coating layer 2,0.5 μm of epitaxially grown 1 μm, AlGaAs second light waveguide-layer 5 of the light emitting active layer 4,0.5 μm of AlGaInAs/AlGaAs quantum well structure and AlGaAs second coating layer 6, Chip-wide L of 1 μm are 300 μm.
There are 2 grooves extended along laser generation direction at chip upper surface along laser generation direction, formed by photoetching removal the second coating layer 6 of full depth and the second light waveguide-layer 5 of segment thickness; To be width between two grooves the be pulse current injectingt region W of 50 μm, trench cross section shape is square, and width is 20 μm, and the degree of depth is 1.2 μm.
Second coating layer 6 is coated with the injection barrier layer 7 of 0.3 μm above, and injecting barrier layer is SiO
2material, electrical pumping window part (no barrier layer) in the middle of the W of pulse current injectingt region, P face electric contacting layer 8 and N face electric contacting layer 9 lay respectively at most last layer and the basecoat of chip structure, adopt Ti/Pt/Au and Ni/Au multiple layer metal thin-film material respectively.
By the chip P face of making by indium solder be sintered to AlN ceramic heat sink on, extraction electrode line, carries out energising test, records it and swashs the wave spectrum penetrated.As shown in Figure 4, wavelength presents single crest, is qualified product.
Comparative example 1:
With gain waveguide type semiconductor laser chip structure as shown in Figure 1 as a comparison case.Define except platform except not processing groove in electric contacting layer side, P face but etched completely light-emitting zone both sides, the structure of laser is all identical with embodiment 1 with packaging technology.
Adopt chip of laser of the present utility model under identical packaging technology, to make Laser Devices with former contrast chip respectively, test its wavelength, as shown in Figure 3, wavelength presents bimodal situation, has two glow peaks closed on.
The product package experiment of embodiment 1 chip of laser and comparative example 1 obtains correction data as following table 1:
Table 1
Note: " multiplet of doublet " refers to that wavelength presents bimodal or 3 and above multiple glow peaks closed on.
Test data shows, adopts the Laser Devices that chip of laser of the present utility model obtains under same package technique, and the stress produced due to encapsulation significantly reduces, and its multiplet of doublet ratio declines to a great extent, successful, can the qualification rate of obvious improving laser device.
Embodiment 2: a kind of chip structure reducing semiconductor laser encapsulation stress, as shown in Figure 2.
On GaAs substrate 1, epitaxy grows AlGaAs first light waveguide-layer 3 of AlGaAs first coating layer 2,0.35 μm having 0.9 μm, AlGaAs second light waveguide-layer 5 of the light emitting active layer 4,0.35 μm of AlGaInAs/AlGaAs quantum well structure and AlGaAs second coating layer 6, Chip-wide L of 0.8 μm is in turn 200 μm.Have 2 grooves at chip upper surface along laser generation direction, trench cross section shape is square, and width is 15 μm, and the degree of depth is 1 μm.These 2 groove interval mid portions to be width be pulse current injectingt region W of 35 μm.Remainder is identical with embodiment 1.
By the chip P face of the present embodiment by indium solder be sintered to AlN ceramic heat sink on, extraction electrode line, carries out energising test, records it and swashs the wave spectrum penetrated.
Comparative example 2: as described in Figure 1, define except platform except not having groove in electric contacting layer side, P face but etched completely light-emitting zone both sides, the structure of laser is all identical with embodiment 2 with packaging technology for chip of laser structure.Test its wavelength.Experiment shows, the multiplet of doublet ratio of the present embodiment 2 drops to 7% by 25.3% of comparative example 2.
Embodiment 3: a kind of chip structure reducing semiconductor laser encapsulation stress, as shown in Figure 2.
GaAs substrate 1 adopting metal organic vapor method grow AlGaAs first light waveguide-layer 3 of AlGaAs first coating layer 2,0.6 μm of 0.8 μm, AlGaAs second light waveguide-layer 5 of the light emitting active layer 4,0.6 μm of AlGaInP/AlGaAs quantum well structure and AlGaAs second coating layer 6, Chip-wide L of 1.5 μm is in turn 500 μm.
At the groove of chip upper surface along 100 μm, You Liangtiao interval, laser generation direction, trench cross section shape is square, and width is 30 μm, and the degree of depth is 2 μm.Article two, to be width between groove the be pulse current injectingt region W of 100 μm.Second coating layer 6 upper part covers the injection barrier layer 7 of 0.25 μm, and injecting barrier layer is SiN, and pulse current injectingt region W mid portion no barrier layer, reserves the electrical pumping window in luminance gain region; Depositing below P face electric contacting layer 8, GaAs substrate 1 on injection barrier layer 7 is N face electric contacting layer 9, adopts Ti/Pt/Au and Ni/Au multiple layer metal film respectively.
By the chip P face of embodiment 3 by golden tin solder be sintered to AlN ceramic heat sink on, extraction electrode line, carries out energising test, records it and swashs the wave spectrum penetrated.
Comparative example 3: as shown in Figure 1, define except platform except not processing groove in electric contacting layer side, P face but etched completely light-emitting zone both sides, all the other are identical with embodiment 3, test its wavelength for structure.Data show, the multiplet of doublet ratio of the present embodiment 3 drops to 4.9% by 20.2% of comparative example 3.
Claims (10)
1. one kind is reduced the chip structure of semiconductor laser encapsulation stress, comprise semiconductor chip, this chip structure is by the gain waveguide type semiconductor laser structure with pulse current injectingt region and luminance gain region that metal organic vapor method is formed on above-mentioned semiconductor chip; Have 2 grooves extended along laser generation direction, above-mentioned luminance gain region is arranged at the centre position of 2 grooves.
2. the as claimed in claim 1 chip structure reducing semiconductor laser encapsulation stress, it is characterized in that the toatl proportion that the width sum of described 2 groove opening accounts for Chip-wide controls at 5-30%, the A/F of described groove and the ratio of the degree of depth are at 2-50.
3. the chip structure reducing semiconductor laser encapsulation stress as claimed in claim 1, it is characterized in that the width of described semiconductor laser chip is 100-500 μm, the width in luminance gain region is the 20%-80% of Chip-wide.
4. the chip structure reducing semiconductor laser encapsulation stress as claimed in claim 1, is characterized in that the cross sectional shape of described groove is square, trapezoidal or semicircle.
5. the as claimed in claim 1 chip structure reducing semiconductor laser encapsulation stress, is characterized in that 2 described groove shapes, measure-alike.
6. the chip structure reducing semiconductor laser encapsulation stress as claimed in claim 1, it is characterized in that the width of groove opening is 5-50 μm, the toatl proportion accounting for Chip-wide controls at 5-30%.
7. the chip structure reducing semiconductor laser encapsulation stress as claimed in claim 1, it is characterized in that the degree of depth of described groove is 0.5-5 μm, the width of groove and the ratio of the degree of depth are at 2-50.
8. the chip structure reducing semiconductor laser encapsulation stress as claimed in claim 1, it is characterized in that the degree of depth of described groove is 0.5-5 μm, the width of groove and the ratio of the degree of depth are at 10-20.
9. the chip structure reducing semiconductor laser encapsulation stress as claimed in claim 1, it is characterized in that the A/F of groove is 15-30 μm, the degree of depth is 1-2 μm.
10. the chip structure reducing semiconductor laser encapsulation stress as claimed in claim 1, it is characterized in that described gain waveguide type semiconductor laser structure, is grow in turn on the semiconductor substrate to have the first coating layer, the first light waveguide-layer, light emitting active layer, the second light waveguide-layer and the second coating layer; 2 grooves extended along laser generation direction are formed at the second cover surface chemical wet etching, gash depth reaches the second light waveguide-layer of at least whole second coating layer and suitable thickness, between 2 grooves part luminance gain region on leave electrical pumping window, second coating layer of remainder has barrier layer, is namely pulse current injectingt region directly over luminance gain region; Also deposit P face electric contacting layer and N face electric contacting layer.
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| CN201520663400.0U CN204947320U (en) | 2015-08-28 | 2015-08-28 | A kind of chip structure reducing semiconductor laser encapsulation stress |
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Address after: Tianchen Avenue high tech Zone of Ji'nan City, Shandong Province, No. 1835 250101 Patentee after: SHANDONG HUAGUANG OPTOELECTRONICS CO., LTD. Address before: 250101 Shandong city of Ji'nan province high tech Zone (Lixia) Tianchen Street No. 1835 Patentee before: Shandong Huaguang Photoelectronic Co., Ltd. |