CN204905985U - ORING control circuit and electrical power generating system - Google Patents
ORING control circuit and electrical power generating system Download PDFInfo
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- CN204905985U CN204905985U CN201520402749.9U CN201520402749U CN204905985U CN 204905985 U CN204905985 U CN 204905985U CN 201520402749 U CN201520402749 U CN 201520402749U CN 204905985 U CN204905985 U CN 204905985U
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- 230000005669 field effect Effects 0.000 claims abstract description 91
- 230000002159 abnormal effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 4
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/007—Fail-safe circuits
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- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
Abstract
The utility model discloses a ORING control circuit and electrical power generating system, this ORING control circuit include field effect transistor, triode VT102, triode VT104 and switching circuit, wherein, field effect transistor's source connection holds to input voltage, field effect transistor's drain electrode is connected to output and closes way voltage end, field effect transistor's grid is held to auxiliary electrical power source through switching circuit connection, the auxiliary electrical power source end is connected to the input voltage end through triode VT102, the auxiliary electrical power source end is connected to output through triode VT104 and closes way voltage end, triode VT102 is connected to the first input end of switching circuit, triode VT104 is connected to the second input of switching circuit, the switching circuit switching on and turn -offing according to triode VT102 and triode VT104's, and optionally is connected to in auxiliary electrical power source end or the earthing terminal with field effect transistor's grid. Whole ORING control circuit passes through field effect transistor and triode to be realized, under the control function's that realizes ORING control circuit prerequisite, provides the ORING control circuit of a low cost.
Description
Technical Field
The utility model relates to the field of communication, indicate an ORING control circuit and electrical power generating system especially.
Background
With the continuous development of communication equipment, the requirements on the reliability and the cost of power supply of a power supply system are higher and higher, and a power supply adopts a redundancy backup design, so that the power supply reliability of a product is improved. For example, a schematic structural diagram of a power supply system including an ORING control circuit is shown in fig. 1, where the power supply system includes two power supplies, namely a power supply 1 and a power supply 2, and an input voltage Vin of each power supply is controlled by a corresponding ORING control circuit and is connected to the bus voltage through the corresponding ORING control circuit. The purpose of doing so is in order to prevent because when certain power supply broke down, another power supply can not receive the influence of trouble power supply, can continue to supply power for the later stage load to guarantee the normal work of whole communication equipment.
At present, the ORING control circuit is usually implemented by using a fet and an op-amp (or a comparator), and referring to fig. 2, the ORING control circuit implemented by a fet and an op-amp in the prior art is shown. The input voltage Vin is connected to the source electrode of the field-effect tube Q1, the output voltage Vout is connected to the drain electrode of the field-effect tube Q1, and the on-off of the field-effect tube is controlled through the operational amplifier F, so that the control function of the ORING control circuit is realized.
The other is realized by integrating an ORING control chip. Referring to fig. 3, the ORING control circuit implemented by integrating an ORING control chip in the prior art is shown. The input voltage Vin is connected to the source of the fet Q2, the output voltage Vout is connected to the drain of the fet Q2, and the on/off of the fet Q2 is controlled by an integrated chip in the prior art, such as an ORING control chip, so as to implement the control function of the ORING control circuit.
The power supply system comprises a plurality of paths of input voltages Vin, and each path of input voltage Vin is controlled by a corresponding ORING control circuit. Fig. 2 and 3 show the ORING control circuit corresponding to one input voltage Vin.
In fig. 2 and 3, according to the control principle of the ORING control circuit, when the input voltage Vin is normally supplied with power, the source and the drain of the fet are turned on, so that the input voltage Vin can provide the output voltage Vout through the fet; when the input power supply is abnormal, the source electrode and the drain electrode of the field effect tube are disconnected, so that the input voltage Vin of the input voltage end cannot be supplied to the output combined circuit voltage end through the field effect tube, and through the control of the on and off of the field effect tube in the ORING control circuit, the connection between the input power supply and the bus is disconnected through the field effect tube when the input power supply is abnormal, so that the abnormal input power supply cannot be connected to the bus, and the abnormal input voltage Vin is effectively isolated.
For the ORING control circuit provided in fig. 2 and 3, the two schemes have the advantages of simple peripheral circuit, high reliability, and high cost, and are difficult to be applied to low-cost application requirements.
SUMMERY OF THE UTILITY MODEL
In order to solve the above problem, the utility model provides a ORING control circuit and electrical power generating system can provide the lower reliable ORING control circuit of a cost.
In order to achieve the above object, the present invention provides an ORING control circuit, which includes a field effect transistor Q118, a transistor VT102, a transistor VT104, and a switching circuit; wherein,
the source electrode of the field effect transistor Q118 is connected to the input voltage end; the drain electrode of the field effect transistor Q118 is connected to the output combining voltage end; the grid of the field effect transistor Q118 is connected to the auxiliary power supply end through the switching circuit;
the auxiliary power supply end is connected to an input voltage end through a triode VT 102; the auxiliary power supply end is connected to the output combining voltage end through the triode VT 104;
the triode VT102 is connected to a first input end of the switching circuit; the triode VT104 is connected to the second input end of the switching circuit;
the switching circuit selectively connects the gate of the fet Q118 to one of the auxiliary power supply terminal or the ground terminal according to the turning on and off of the transistor VT102 and the transistor VT 104.
Preferably, the auxiliary power supply terminal is connected to an emitter of the transistor VT102, and a base of the transistor VT102 is connected to the input voltage terminal;
the auxiliary power supply end is connected to the emitter of the triode VT104, and the base of the triode VT104 is connected to the output combining voltage end.
Preferably, the transistor VT102 and the transistor VT104 are PNP transistors.
Preferably, the switching circuit selectively connects the gate of the field effect transistor Q118 to one of the auxiliary power source terminal or the ground terminal according to the on and off of the transistor VT102 and the transistor VT104 specifically includes:
when the transistor VT102 is turned off and the transistor VT104 is turned on, the switching circuit connects the gate of the field effect transistor Q118 to the auxiliary power source terminal; the switching circuit connects the gate of the fet Q118 to ground when the transistor VT102 is on and the transistor VT104 is off.
Preferably, the switching circuit comprises a transistor VT106, a transistor VT108, and a transistor VT 110;
the base electrode of the triode VT106 is connected to the collector electrode of the triode VT102, and the emitter electrode of the triode VT106 is grounded; the collector of the transistor VT106 is connected to the collector of the transistor VT 104;
the base electrode of the triode VT108 is connected to the collector electrode of the triode VT104, and the emitter electrode of the triode VT108 is grounded; the collector of the triode VT108 is connected to the auxiliary power supply end;
the base electrode of the triode VT110 is connected to the collector electrode of the triode VT108, and the emitter electrode of the triode VT110 is grounded; the collector of the transistor VT110 is connected to the auxiliary power source terminal.
Preferably, the auxiliary power supply terminal is connected to the emitter of the transistor VT102 through a resistor R112, and the auxiliary power supply terminal is connected to the emitter of the transistor VT104 through a resistor R112.
Preferably, the base of the transistor VT106 is grounded through a resistor R120;
the collector of the transistor VT108 is connected to the auxiliary power supply terminal through the resistor R114;
the collector of the transistor VT110 is connected to the auxiliary power source terminal through a resistor R116.
Preferably, the switching circuit comprises a field effect transistor Q106, a field effect transistor Q108 and a field effect transistor Q110;
the grid electrode of the field effect transistor Q106 is connected to the collector electrode of the triode VT102, and the source electrode of the field effect transistor Q106 is grounded; the drain electrode of the field effect transistor Q106 is connected to the collector electrode of the triode VT 104;
the grid electrode of the field effect transistor Q108 is connected to the collector electrode of the triode VT104, and the source electrode of the field effect transistor Q108 is grounded; the drain electrode of the field effect transistor Q108 is connected to the auxiliary power supply end;
the grid electrode of the field effect transistor Q110 is connected to the drain electrode of the field effect transistor Q108, and the source electrode of the field effect transistor Q110 is grounded; the drain of the fet Q110 is connected to the auxiliary power supply terminal.
Preferably, the gate of the field effect transistor Q106 is grounded through a resistor R120; the drain of the field effect transistor Q108 is connected to the auxiliary power supply terminal through a resistor R114; the drain of the fet Q110 is connected to the auxiliary power supply terminal through a resistor R116.
In order to achieve the above object, the present invention provides a power supply system, which includes any one of the above ORING control circuits.
Compared with the prior art, the utility model provides a technical scheme includes: the ORING control circuit comprises a field effect transistor Q118, a triode VT102, a triode VT104 and a switching circuit; wherein, the source electrode of the field effect transistor Q118 is connected to the input voltage end; the drain electrode of the field effect transistor Q118 is connected to the output combining voltage end; the grid of the field effect transistor is connected to the auxiliary power supply end through the switching circuit; the auxiliary power supply end is connected to an input voltage end through a triode VT 102; the auxiliary power supply end is connected to the output combining voltage end through the triode VT 104; the triode VT102 is connected to a first input end of the switching circuit; the triode VT104 is connected to the second input end of the switching circuit; the switching circuit selectively connects the gate of the fet to one of the auxiliary power supply terminal or the ground terminal in accordance with the on and off of the transistor VT102 and the transistor VT 104. The switching circuit can be realized by a triode or a field effect transistor. Therefore, the whole ORING control circuit is realized through the field effect transistor and the triode, the cost is low, and the ORING control circuit with low cost is provided on the premise of realizing the control function of the ORING control circuit.
Drawings
The drawings in the embodiments of the present invention are described below, and the drawings in the embodiments are used for further understanding of the present invention, and are used together with the description to explain the present invention, and do not constitute a limitation to the scope of the present invention.
FIG. 1 is a diagram illustrating a power system including an ORING control circuit according to the prior art;
FIG. 2 is a schematic diagram of a prior art ORING control circuit implemented by a FET and an operational amplifier;
FIG. 3 is a schematic diagram illustrating a prior art ORING control circuit implemented by integrating an ORING control chip;
fig. 4 is a circuit diagram of an ORING control circuit according to the present invention;
fig. 5 is a circuit diagram of an ORING control circuit including another switching circuit according to the present invention.
Detailed Description
To facilitate understanding of those skilled in the art, the following further description of the present invention is provided in conjunction with the accompanying drawings and is not intended to limit the scope of the present invention. In the present application, the embodiments and various aspects of the embodiments may be combined with each other without conflict.
Referring to fig. 4, the present invention provides an ORING control circuit, which includes a field effect transistor Q118, a transistor VT102, a transistor VT104, and a switching circuit; wherein, the source electrode of the field effect transistor Q118 is connected to the input voltage end; the drain electrode of the field effect transistor Q118 is connected to the output combining voltage end; the grid of the field effect transistor Q118 is connected to the auxiliary power supply end through the switching circuit; the auxiliary power supply end is connected to an input voltage end through a triode VT 102; the auxiliary power supply end is connected to the output combining voltage end through the triode VT 104; the triode VT102 is connected to a first input end of the switching circuit; the triode VT104 is connected to the second input end of the switching circuit;
the switching circuit selectively connects the gate of the fet Q118 to one of the auxiliary power supply terminal or the ground terminal according to the turning on and off of the transistor VT102 and the transistor VT 104.
The operating characteristic of the field-effect transistor Q118 is that when the voltage difference between the gate voltage and the source voltage is greater than the turn-on threshold voltage vgs (th) of the field-effect transistor, the source and the drain of the field-effect transistor Q118 are connected, the input voltage Vin of the input voltage end is provided to the output combining voltage end through the field-effect transistor Q118, and when the voltage difference between the gate voltage and the source voltage is less than the turn-on threshold voltage vgs (th) of the field-effect transistor, the source and the drain of the field-effect transistor Q118 are disconnected, and the input voltage Vin of the input voltage end cannot be provided to the output combining voltage end.
Specifically, in the embodiment of the present invention, the auxiliary power source terminal is connected to the emitter of the transistor VT102, and the base of the transistor VT102 is connected to the input voltage terminal; the auxiliary power supply end is connected to the emitter of the triode VT104, and the base of the triode VT104 is connected to the output combining voltage end. The transistor VT102 and the transistor VT104 are PNP transistors. The PNP type triode has the working characteristic that when the voltage difference between the emitter voltage and the base voltage is larger than the saturation voltage Veb (sat) of the emitter-base of the triode, the emitter and the collector of the triode are conducted, and when the voltage difference between the emitter voltage and the base voltage is smaller than the saturation voltage Veb (sat) of the emitter-base of the triode, the emitter and the collector of the triode are disconnected.
The operation of the circuit is described below. When the power circuit works normally, the input voltage Vin is slightly larger than the output voltage Vout, at this time, the emitter voltage of the transistor VT102 is equal to the emitter voltage of the transistor VT104, and the base voltage of the transistor VT102 is larger than the base voltage of the transistor VT104, so that the transistor VT104 is in a conducting state, and the transistor VT102 is in a turn-off state.
Specifically, since the auxiliary voltage Vap of the auxiliary power source terminal is usually much higher than the input voltage Vin and the output voltage Vout, the auxiliary voltage Vap will form a loop through the emitter-base of the transistor VT104 and the output voltage Vout, so that the transistor VT104 is turned on.
For the transistor VT102, the base voltage Vb _102 is Vin, the emitter voltage Ve _102 is Vout + veb (sat), and Vin is greater than Vout, so the difference between the emitter voltage Ve _102 and the base voltage Vb _102 of the transistor VT102 is less than veb (sat), and therefore the transistor VT102 is in the off state. In this embodiment, the saturation voltage veb (sat) of the emitter-base of the transistor is illustrated as 0.7.
When the power supply circuit normally operates, the input voltage Vin is 11V, the output voltage Vout is 10V, the auxiliary voltage Vap of the auxiliary power supply terminal is 20V, the transistor VT104 is in a conducting state, the base voltage of the transistor VT104 is less than the emitter voltage, the base voltage of the transistor VT104 is 10V, and the emitter voltage of the transistor VT104 is 10+ 0.7-10.7V; the voltage of the emitter of the transistor VT102 is also 10.7V, the voltage of the base of the transistor VT102 is also 11V, the voltage difference between the voltage of the emitter and the base of the transistor VT102 is less than 0.7V, and the transistor VT102 is in an off state.
When the power circuit is abnormal, the input voltage Vin will be smaller than the output voltage Vout. When one of the two input voltages Vin is over-voltage, the other circuit is normal, and for the abnormal power, the Vin is smaller than Vout; when one of the two input voltages Vin is short-circuited, that is, one of the two input voltages Vin is short-circuited, and the other input voltage Vin is normally output, the condition that Vin is smaller than Vout also occurs for the short-circuited power.
In the abnormal condition of the power circuit, the voltage of the emitter of the transistor VT102 is equal to the voltage of the emitter of the transistor VT104, and the voltage of the base of the transistor VT102 is lower than the voltage of the base of the transistor VT104, so that the transistor VT102 is in the on state and the transistor VT104 is in the off state.
Specifically, since the auxiliary voltage Vap is usually much higher than the input voltage Vin and the output voltage Vout, the auxiliary voltage Vap will loop through the emitter-base stage of the transistor VT102 and the input voltage Vin, so that the transistor VT102 is turned on.
When the power circuit operates abnormally, the input voltage Vin is 0.5V, the output voltage Vout is 10V, the auxiliary voltage Vap of the auxiliary power supply terminal is 20V, the transistor VT102 is in a conducting state, the base voltage of the transistor VT104 is smaller than the emitter voltage, the base voltage of the transistor VT102 is 0.5V, and the emitter voltage of the transistor VT102 is 0.5+0.7 to 1.2V; the emitter voltage of the transistor VT104 is 1.2V, the base voltage of the transistor VT104 is 10V, the base voltage of the transistor VT104 is greater than the emitter voltage, and the transistor VT104 is in an off state.
The operation principle of the switching circuit will be explained below.
The embodiment of the utility model provides an in, switching circuit according to triode VT102 and triode VT104 to switch on and turn off, selectively with field effect transistor Q118's grid be connected to one in the supplementary power end or the earthing terminal specifically include:
when the transistor VT102 is turned off and the transistor VT104 is turned on, the switching circuit connects the gate of the field effect transistor Q118 to the auxiliary power source terminal; the switching circuit connects the gate of the fet Q118 to ground when the transistor VT102 is on and the transistor VT104 is off.
The auxiliary voltage Vap is connected to the gate of the field effect transistor Q118 through the switching circuit, under the condition that the triode VT102 is turned off and the triode VT104 is turned on, the switching circuit connects the gate of the field effect transistor Q118 to the auxiliary power supply terminal, the auxiliary voltage Vap can apply voltage to the gate of the field effect transistor Q118, the gate voltage of the field effect transistor Q118 is greater than the source voltage, conduction is performed between the source and the drain of the field effect transistor Q118, and therefore the input voltage Vin of the input voltage terminal is provided to the output combining voltage terminal through the field effect transistor Q118.
The auxiliary voltage Vap is connected to the gate of the fet Q118 through the switching circuit, and when the transistor VT102 is turned on and the transistor VT104 is turned off, the auxiliary voltage Vap applies a voltage to the gate of the fet Q118, the gate voltage of the fet Q118 is lower than the source voltage, and the source and drain of the fet Q118 are disconnected, so that the input voltage Vin of the input voltage terminal cannot be supplied to the output combining voltage terminal through the fet Q118.
The following describes the structure of the switching circuit in detail.
In an embodiment of the present invention, the switching circuit is implemented by a triode, and specifically, the switching circuit includes a triode VT106, a triode VT108, and a triode VT 110;
the base electrode of the triode VT106 is connected to the collector electrode of the triode VT102, and the emitter electrode of the triode VT106 is grounded; the collector of the transistor VT106 is connected to the collector of the transistor VT 104;
the base electrode of the triode VT108 is connected to the collector electrode of the triode VT104, and the emitter electrode of the triode VT108 is grounded; the collector of the triode VT108 is connected to the auxiliary power supply end;
the base electrode of the triode VT110 is connected to the collector electrode of the triode VT108, and the emitter electrode of the triode VT110 is grounded; the collector of the transistor VT110 is connected to the auxiliary power source terminal.
The auxiliary power source terminal is connected to the emitter of the transistor VT102 through the resistor R112, and the auxiliary power source terminal is connected to the emitter of the transistor VT104 through the resistor R112. The base of the triode VT102 is connected to the input voltage end through the resistor R122; the base of the triode VT104 is connected to the output combining voltage end through the resistor R126; the base of the transistor VT102 is grounded through a capacitor C124; the base of the triode VT104 is grounded through a capacitor C128; the base of the triode VT106 is grounded through a resistor R120; the collector of the transistor VT108 is connected to the auxiliary power supply terminal through the resistor R114; the collector of the transistor VT110 is connected to the auxiliary power source terminal through a resistor R116.
For the switching circuit, when the transistor VT102 is turned off and the transistor VT104 is turned on, the transistor VT106 is also turned off because the transistor VT102 is turned off; when the transistor VT104 is turned on, the auxiliary power supply drives the transistor VT108 through the resistor R112 and the emitter-collector of the transistor VT104, so that the transistor VT108 is turned on, and when the transistor VT108 is turned on, the base of the transistor VT110 is connected to the ground, so that the transistor VT110 is turned off, so that the collector of the transistor VT110 outputs a high level, and the field effect tube Q118 is driven, so that the field effect tube Q118 is turned on, and a current flows from the input voltage Vin to the combiner bus Vout.
For the above switching circuit, under the condition that the transistor VT102 is turned on and the transistor VT104 is turned off, at this time, the auxiliary power supply drives the transistor VT106 through the resistor R112 and the emitter-collector of the transistor VT102, so that the transistor VT106 is turned on, the collector of the transistor VT106 is at a low level, that is, the base of the transistor VT108 is at a low level, the transistor VT108 is also not turned on, the auxiliary power supply drives the transistor VT110 through the resistor R114, the transistor VT110 is turned on, and finally, the collector of the VT110 outputs a low level, that is, the switching circuit connects the gate of the field effect transistor to the ground terminal, so that the field effect transistor Q118 is turned off, and the input voltage Vin and the bus voltage Vout.
The embodiment of the present invention provides still another kind of switching circuit, refer to fig. 5, for the utility model provides a contain another kind of switching circuit's aring control circuit's circuit diagram. In which the switching circuit is implemented by means of field effect transistors, and in particular, as shown in connection with figure 5,
the switching circuit comprises a field effect transistor Q106, a field effect transistor Q108 and a field effect transistor Q110;
the grid electrode of the field effect transistor Q106 is connected to the collector electrode of the triode VT102, and the source electrode of the field effect transistor Q106 is grounded; the drain electrode of the field effect transistor Q106 is connected to the collector electrode of the triode VT 104;
the grid electrode of the field effect transistor Q108 is connected to the collector electrode of the triode VT104, and the source electrode of the field effect transistor Q108 is grounded; the drain electrode of the field effect transistor Q108 is connected to the auxiliary power supply end;
the grid electrode of the field effect transistor Q110 is connected to the drain electrode of the field effect transistor Q108, and the source electrode of the field effect transistor Q110 is grounded; the drain of the fet Q110 is connected to the auxiliary power supply terminal.
The auxiliary power source terminal is connected to the emitter of the transistor VT102 through the resistor R112, and the auxiliary power source terminal is connected to the emitter of the transistor VT104 through the resistor R112. The base of the triode VT102 is connected to the input voltage end through the resistor R122; the base of the triode VT104 is connected to the output combining voltage end through the resistor R126; the base of the transistor VT102 is grounded through a capacitor C124; the base of the triode VT104 is grounded through a capacitor C128; the grid of the field effect transistor Q106 is grounded through a resistor R120; the drain of the field effect transistor Q108 is connected to the auxiliary power supply terminal through a resistor R114; the drain of the fet Q110 is connected to the auxiliary power supply terminal through a resistor R116.
For the switching circuit, when the transistor VT102 is turned off and the transistor VT104 is turned on, the transistor VT106 is also turned off because the transistor VT102 is turned off; when the transistor VT104 is turned on, the auxiliary power supply drives the fet Q108 through the resistor R112 and the emitter-collector of the transistor VT104, so that the fet Q108 is turned on, and when the fet Q108 is turned on, the gate of the fet Q110 is connected to the ground, so that the fet Q110 is turned off, and therefore the drain of the fet Q110 outputs a high level, and the fet Q118 is driven, so that the fet Q118 is turned on, and a current flows from the input voltage Vin to the combiner bus Vout.
For the above switching circuit, under the condition that the triode VT102 is turned on and the triode VT104 is turned off, at this time, the auxiliary power supply drives the fet Q106 through the resistor R112 and the emitter-collector of the triode VT102, so that the fet Q106 is turned on, the drain of the fet Q106 is at a low level, that is, the gate of the fet Q108 is at a low level, the fet Q108 is also not turned on, the auxiliary power supply drives the fet Q110 through the resistor R114, the fet Q110 is turned on, and the drain of the fet Q110 finally outputs a low level, that is, the switching circuit connects the gate of the fet to the ground, so that the fet Q118 is disconnected, and the input voltage Vin and the bus voltage Vout after combination are also disconnected in time.
It should be noted that the above-mentioned embodiments are only for facilitating understanding of those skilled in the art, and are not intended to limit the scope of the present invention, and any obvious substitutions, modifications, etc. made by those skilled in the art without departing from the spirit of the present invention are within the scope of the present invention.
Claims (10)
1. An ORING control circuit, which is characterized in that the ORING control circuit comprises a field effect transistor Q118, a triode VT102, a triode VT104 and a switching circuit; wherein,
the source electrode of the field effect transistor Q118 is connected to the input voltage end; the drain electrode of the field effect transistor Q118 is connected to the output combining voltage end; the grid of the field effect transistor Q118 is connected to the auxiliary power supply end through the switching circuit;
the auxiliary power supply end is connected to an input voltage end through a triode VT 102; the auxiliary power supply end is connected to the output combining voltage end through the triode VT 104;
the triode VT102 is connected to a first input end of the switching circuit; the triode VT104 is connected to the second input end of the switching circuit;
the switching circuit selectively connects the gate of the fet Q118 to one of the auxiliary power supply terminal or the ground terminal according to the turning on and off of the transistor VT102 and the transistor VT 104.
2. The ORING control circuit of claim 1, wherein,
the auxiliary power supply end is connected to an emitting electrode of the triode VT102, and a base electrode of the triode VT102 is connected to the input voltage end;
the auxiliary power supply end is connected to the emitter of the triode VT104, and the base of the triode VT104 is connected to the output combining voltage end.
3. The ORING control circuit of claim 2, wherein the transistor VT102 and the transistor VT104 are PNP transistors.
4. The ORING control circuit of claim 2, wherein the switching circuit selectively connects the gate of the fet Q118 to one of the auxiliary power supply terminal or the ground terminal in response to the switching on and off of the transistor VT102 and the transistor VT104, comprises:
when the transistor VT102 is turned off and the transistor VT104 is turned on, the switching circuit connects the gate of the field effect transistor Q118 to the auxiliary power source terminal; the switching circuit connects the gate of the fet Q118 to ground when the transistor VT102 is on and the transistor VT104 is off.
5. The ORING control circuit of claim 4, wherein the switching circuit comprises a transistor VT106, a transistor VT108, and a transistor VT 110;
the base electrode of the triode VT106 is connected to the collector electrode of the triode VT102, and the emitter electrode of the triode VT106 is grounded; the collector of the transistor VT106 is connected to the collector of the transistor VT 104;
the base electrode of the triode VT108 is connected to the collector electrode of the triode VT104, and the emitter electrode of the triode VT108 is grounded; the collector of the triode VT108 is connected to the auxiliary power supply end;
the base electrode of the triode VT110 is connected to the collector electrode of the triode VT108, and the emitter electrode of the triode VT110 is grounded; the collector of the transistor VT110 is connected to the auxiliary power source terminal.
6. The ORING control circuit of claim 2, wherein,
the auxiliary power supply terminal is connected to the emitter of the transistor VT102 through the resistor R112, and the auxiliary power supply terminal is connected to the emitter of the transistor VT104 through the resistor R112.
7. The ORING control circuit of claim 5 or 6,
the base of the triode VT106 is grounded through a resistor R120;
the collector of the transistor VT108 is connected to the auxiliary power supply terminal through the resistor R114;
the collector of the transistor VT110 is connected to the auxiliary power source terminal through a resistor R116.
8. The ORING control circuit of claim 4, wherein the switching circuit comprises a FET Q106, a FET Q108, and a FET Q110;
the grid electrode of the field effect transistor Q106 is connected to the collector electrode of the triode VT102, and the source electrode of the field effect transistor Q106 is grounded; the drain electrode of the field effect transistor Q106 is connected to the collector electrode of the triode VT 104;
the grid electrode of the field effect transistor Q108 is connected to the collector electrode of the triode VT104, and the source electrode of the field effect transistor Q108 is grounded; the drain electrode of the field effect transistor Q108 is connected to the auxiliary power supply end;
the grid electrode of the field effect transistor Q110 is connected to the drain electrode of the field effect transistor Q108, and the source electrode of the field effect transistor Q110 is grounded; the drain of the fet Q110 is connected to the auxiliary power supply terminal.
9. The ORING control circuit of claim 8, wherein the gate of fet Q106 is coupled to ground through resistor R120; the drain of the field effect transistor Q108 is connected to the auxiliary power supply terminal through a resistor R114; the drain of the fet Q110 is connected to the auxiliary power supply terminal through a resistor R116.
10. A power supply system comprising the ORING control circuit of any one of claims 1-9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520402749.9U CN204905985U (en) | 2015-06-11 | 2015-06-11 | ORING control circuit and electrical power generating system |
| PCT/CN2015/092189 WO2016197500A1 (en) | 2015-06-11 | 2015-10-19 | Oring control circuit and electricity power system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520402749.9U CN204905985U (en) | 2015-06-11 | 2015-06-11 | ORING control circuit and electrical power generating system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204905985U true CN204905985U (en) | 2015-12-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520402749.9U Expired - Fee Related CN204905985U (en) | 2015-06-11 | 2015-06-11 | ORING control circuit and electrical power generating system |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN204905985U (en) |
| WO (1) | WO2016197500A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106300321A (en) * | 2016-08-31 | 2017-01-04 | 四川升华电源科技有限公司 | Power supply anti-back flow circuit |
| WO2018076794A1 (en) * | 2016-10-25 | 2018-05-03 | 宁德时代新能源科技股份有限公司 | Redundant backup control circuit of battery management system |
| CN110994779A (en) * | 2019-12-20 | 2020-04-10 | 苏州浪潮智能科技有限公司 | Main and standby power supply combining control circuit and control method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117741494A (en) * | 2023-12-22 | 2024-03-22 | 山东省国防动员指挥保障中心 | Power supply state monitoring method and circuit of air quality monitoring device for civil air defense |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7466573B2 (en) * | 2006-05-16 | 2008-12-16 | Honeywell International, Inc. | Method and apparatus for integrated active-diode-ORing and soft power switching |
| CN102625511B (en) * | 2011-01-26 | 2014-03-26 | 陈建华 | Self-boosting wind and light complementation solar energy street lamp controller |
| CN102545868A (en) * | 2011-12-28 | 2012-07-04 | 华为技术有限公司 | ORing Fet blocking circuit and power system |
-
2015
- 2015-06-11 CN CN201520402749.9U patent/CN204905985U/en not_active Expired - Fee Related
- 2015-10-19 WO PCT/CN2015/092189 patent/WO2016197500A1/en active Application Filing
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106300321A (en) * | 2016-08-31 | 2017-01-04 | 四川升华电源科技有限公司 | Power supply anti-back flow circuit |
| WO2018076794A1 (en) * | 2016-10-25 | 2018-05-03 | 宁德时代新能源科技股份有限公司 | Redundant backup control circuit of battery management system |
| CN110994779A (en) * | 2019-12-20 | 2020-04-10 | 苏州浪潮智能科技有限公司 | Main and standby power supply combining control circuit and control method |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2016197500A1 (en) | 2016-12-15 |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151223 Termination date: 20170611 |
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| CF01 | Termination of patent right due to non-payment of annual fee |