CN204832878U - Switching mode digital display constant voltage power supply - Google Patents
Switching mode digital display constant voltage power supply Download PDFInfo
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- CN204832878U CN204832878U CN201520594630.6U CN201520594630U CN204832878U CN 204832878 U CN204832878 U CN 204832878U CN 201520594630 U CN201520594630 U CN 201520594630U CN 204832878 U CN204832878 U CN 204832878U
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- module
- digital display
- switching mode
- converter
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Abstract
The utility model discloses a switching mode digital display constant voltage power supply, it includes power module, power module is connected with keyboard module, FPGA master control circuit, DA converter, operational amplifier, display circuit, the keyboard module is connected with the FPGA master control circuit input, the FPGA master control circuit output is connected with and shows circuit input end, DA converter input, DA converter output is connected with operational amplifier, the DA converter is provided with two the tunnel side by side. Its interference killing feature is strong, convenience, good reliability, stabilization of output just can show in a flexible way in the regulation.
Description
Technical field
The utility model relates to a kind of power supply, refers more particularly to a kind of switching mode digital display stabilized voltage supply.
Background technology
Along with the develop rapidly of computing machine and mechanics of communication, from tradition application middle and small scale chip structure Circuits System to applying single-chip microcomputer widely, to the application of DSP and FPGA today in system, electronic design technology has marched toward a brand-new stage, and traditional power supply can not meet the more and more higher electronic equipment of precision requirement.The method of current generation D.C. regulated power supply is roughly divided into two kinds: one is analogy method, another kind is numerical approach, the former circuit all adopts mimic channel to control, the latter is controlled automatically by digital circuit, and D.C. regulated power supply is necessary towards the development in digital automatic control direction.Therefore the research for switching mode digital display stabilized voltage supply is also necessary.
Utility model content
The purpose of this utility model is to provide a kind of switching mode digital display stabilized voltage supply, and its antijamming capability is strong, flexible adjustment is convenient, reliability is strong, output voltage stabilization and can showing.
In order to realize above object, the technical solution adopted in the utility model is: a kind of switching mode digital display stabilized voltage supply, and it comprises power module, and described power module is connected with Keysheet module, FPGA governor circuit, D/A converter, operational amplifier, display circuit; Described Keysheet module is connected with FPGA governor circuit input end; Described FPGA governor circuit output terminal is connected with display circuit input end, D/A converter input end; Described D/A converter output terminal is connected with operational amplifier; Described D/A converter is set side by side with and is no less than two-way.
Further, frequency divider is provided with in described FPGA governor circuit; Described frequency divider is connected with Keysheet module input end; Described Keysheet module output terminal is connected with counter module; Described counter module output terminal be connected with side by side alternative module and two, decimal system decoding module; Described two, decimal system decoding module is connected with D/A converter; Described alternative module is connected with 7 segment decoders; Described 7 segment decoders are connected with segment encode control end.
Further, described frequency divider is set side by side with two, and one is 1,000,000 frequency dividers, and another is 2,000,000 frequency dividers; Described 2,000,000 frequency dividers are connected with Keysheet module; Described 1,000,000 frequency dividers are connected with counter module.
Further, described FPGA governor circuit adopts EP2C5T144 chip.
Further, described display circuit have employed common cathode digital display tube.
Further, described D/A change-over circuit adopts D/AC0832 chip.
Further, have employed ISL6443 power supply chip in described power module.
The beneficial effects of the utility model:
The utility model utilizes the high resolving power of D/A converter and the Automatic Measurement Technique of FPGA to devise Switching Power Supply, can conveniently input and selected scheduled voltage, can realize doubleway output simultaneously; compare single channel to export; security is higher, and the output current on every road reduces, and overload protection is easier.All functions are realized by the keyboard on panel, bring great convenience, improve work efficiency to Experiment of Electrical Circuits.
Accompanying drawing explanation
Fig. 1 is that the utility model integrated circuit connects block diagram.
Fig. 2 is FPGA device inside functional module connecting frame figure in the utility model.
Embodiment
The technical solution of the utility model is understood better in order to make those skilled in the art; below in conjunction with accompanying drawing, the utility model is described in detail; the description of this part is only exemplary and explanatory, should not have any restriction to protection domain of the present utility model.
As shown in Figure 1-2, anatomical connectivity of the present utility model closes and is: a kind of switching mode digital display stabilized voltage supply, and it comprises power module, and described power module is connected with Keysheet module, FPGA governor circuit, D/A converter, operational amplifier, display circuit; Described Keysheet module is connected with FPGA governor circuit input end; Described FPGA governor circuit output terminal is connected with display circuit input end, D/A converter input end; Described D/A converter output terminal is connected with operational amplifier; Described D/A converter is set side by side with and is no less than two-way.
Preferably, frequency divider is provided with in described FPGA governor circuit; Described frequency divider is connected with Keysheet module input end; Described Keysheet module output terminal is connected with counter module; Described counter module output terminal be connected with side by side alternative module and two, decimal system decoding module; Described two, decimal system decoding module is connected with D/A converter; Described alternative module is connected with 7 segment decoders; Described 7 segment decoders are connected with segment encode control end.
Preferably, described frequency divider is set side by side with two, and one is 1,000,000 frequency dividers, and another is 2,000,000 frequency dividers; Described 2,000,000 frequency dividers are connected with Keysheet module; Described 1,000,000 frequency dividers are connected with counter module.
Preferably, described FPGA governor circuit adopts EP2C5T144 chip.
Preferably, described display circuit have employed common cathode digital display tube.
Preferably, described D/A change-over circuit adopts D/AC0832 chip.
Preferably, have employed ISL6443 power supply chip in described power module.
Below in conjunction with accompanying drawing, the utility model is described in further detail.
This system comprises FPGA governor circuit, D/A change-over circuit, display circuit, key circuit, operational amplification circuit, power module etc., by button to FPGA input signal, FPGA obtains " ten " and " individual position " counting pulse signal, counted by counter module, outside display circuit is given to show current magnitude of voltage in signal one tunnel of internal counter, another road exports analog quantity through D/A converter, amplify through operational amplifier isolation again, control the base stage of output power pipe, different voltage is exported along with the change of power tube base voltage, realize doubleway output simultaneously, output voltage range is 0 ~ 9.9V, stepping is 0.1V.Fundamental power supply module is that each several part circuit is powered.Another FPGA device inside selects each functional modules such as 1 module to form by frequency divider, counter module, 2, can realize relation and the effect of each functional module.Namely 50MHZ obtains the signal of 50HZ through 1,000,000 frequency dividers, is re-used as the work clock of 100 system Counter modules, simultaneously as the input signal of keyboard; Namely 50MHZ obtains the work clock of signal as Keysheet module of 25HZ through 2,000,000 frequency dividers; The counting pulse signal of Keysheet module to input disappears and trembles process; 100 system up-down counter modules realize the tally function of 0-99; 2 select 1 module to realize selecting the display integer of data and the function of decimal; It is the character code of numeral method that 7 segment decoder modules realize the output Binary Conversion of counter; Binary-decimal decoder module realizes the binary data output signal of counter be converted to required for D/A.
Principle:
The utility model utilizes the high resolving power of D/A converter and the Automatic Measurement Technique of FPGA to devise Switching Power Supply, can conveniently input and selected scheduled voltage, can realize doubleway output simultaneously; compare single channel to export; security is higher, and the output current on every road reduces, and overload protection is easier.All functions are realized by the keyboard on panel, bring great convenience, improve work efficiency to Experiment of Electrical Circuits.
+ the 5V ,+12V of this power supply and-12V are provided by fundamental power supply module, and+5V is FPGA operating voltage, are also the operating voltage of D/A chip, and+12V and-12V is that operational amplifier is powered; By " ten " button or " individual position " button to FPGA input signal, FPGA obtains counting pulse signal, by its inner interlock circuit thus counting, outside display circuit is given to show current magnitude of voltage in signal one tunnel of internal counter, another road divides two-way to give two D/A converters respectively, and D/A change-over circuit by digital quantity in proportion, converts analog voltage to, again through adjustment, thus the DC voltage of stable output.
Key circuit adopt mechanical keyboard, two groups by key control, carry out doubleway output.
Display circuit adopts common cathode charactron static state display, this display packing requires that each door all needs 8 delivery outlet and controls, the advantage of static display is that display is stable, when LEDs ON electricity is certain, the brightness of display is high, control system is in operational process, and only when needs upgrade displaying contents, FPGA just performs a display update subroutine, so greatly save the processing time, improve the work efficiency of FPGA.
D/A change-over circuit adopts D/AC0832 chip, and its inner structure is made up of 8 input registers, 8 DAC registers, 8 D/A converters.V
cCbe chip power voltage, voltage is 12V, V
reffor reference voltage, size is 5V, R
fbfor feedback resistance exit, this end can connect operational amplifier output terminal, and GND is divided into AGND and DGNA, i.e. simulating signal ground and digital signal ground.To input latches data to DAC register, data enter D/A converter, start conversion.I
out1for analog current output terminal 1, when input numeral is complete 1, input current is maximum, and during full 0, output current is 0, I
out2for analog current output terminal 2, I
out1+ I
out2=constant.In order to analog current is converted to analog voltage, need two output terminal I
out1and I
out2receive two input ends of operational amplifier respectively, obtain unipolar output voltage U through one-level amplifier
0.
Because designed stabilized voltage supply magnitude of voltage is made up of integer and decimal, so the core of D/A converter module converts digital signal to analog voltage fraction part and integral part respectively, the current output terminal of D/AC0832 chip accesses two parallel resistances, resistance ratio is 10/1, thus realize flowing into 0.1 times that the current value of integrated operational amplifier changes D/AC0832 output current into, then by the amplifier magnitude of voltage that to change this analog-signal transitions be fraction part.
Native system FPGA model is the EP2C5T144 of altera corp CycloneII series, and equivalent gate number is 230,000.Power acquisition 5V direct current, by fundamental power supply system perfect on plate for the elements such as FPGA provide required various voltages, and can outwards export 5V, 3.3V, 1.2V voltage.Is furnished with EPCSISI8 configuring chip, JTAG and AS two kinds of download ports, the active crystal oscillator of 50MHz.Be provided with 6 LED light emitting diodes, be used as simple output.All pins of FPGA are all drawn by 2.54mm standard row pin.
The input voltage of power supply partial circuit is 5V.The ISL6443 family power supply chip that Intersil company releases is integrated with two synchronous buck controllers (PWM) and a linear voltage regulator.Two PWM are that 180 degree of out-phase are synchronous, sufficiently lower the effective value of input current and ripple voltage, reduce the requirement to input filter, thus both can independently provide FPGA core voltage V
cCINT, independently can provide I/O voltage V again
cCIO.Kernel and I/O voltage are the guarantees that FPGA system normally works.The core voltage of FPGA is set as 1.2V, by V
out1there is provided, I/O voltage is decided to be 3.3V here, by V
out2there is provided.V
cC_5Vbe the output pin of embedded 5V linear voltage regulator (LDO), for IC, low-side gate drive provide bias voltage, and power for the outside boostrap circuit of high-end gate driver.If be used as 5V power supply input time, this pin must and V
inbe connected.V
cC_5Vpin must pass through the shunt capacitance ground connection near the 4.7uF of this pin, to realize decoupling.If V
cC_5Voutput short-circuit, then thermal overload protection circuit will start.
I/O voltage, core voltage supply electrical connection circuit, V
cCIOtwo groups of voltages all connect 3.3V.FPGA has a lot of I/O, and they are groupings.In EP2C5T144 chip, be divided into four groups, the I/O pin powered often organized is independently, therefore can adopt different level standards.The all IO pin of the design all adopt 3.3V voltage standard, so all V
cCIOall connect 3.3V.
V
cCINTfor the input of FPGA core operational voltage.The FPGA of CycloneII series all adopts the core voltage of 1.2V, so connect 1.2V here.
EP2C5T144 provides 8 road clocks for user, plate carries the active crystal oscillator of 50M, direct scaling down processing obtains 25Hz frequency, all the other 7 tunnels have 3 tunnels to receive on interface board to use, other 4 tunnels directly expand on plank, when inputting for external clock, in order to increase stability, π type filtering process is done to clock importation, simultaneously containing resistance buffering.
Time JTAG or ASP work is downloaded, pilot lamp is lighted, and extinguishes after success.Button, can reconfigure FPGA, is equivalent to reset, and after pressing, pilot lamp is bright, the fetch program from configuring chip, and after successfully reading, program starts normal operation, and LED extinguishes.ASP and jtag interface circuit, adopt EPCSISI8 configuring chip, 1M capacity, is applicable to EP2C5T and uses.
FPGA device function module section, because fpga chip carries the active crystal oscillator of 50MHZ, its frequency is too high, and having to pass through suitable frequency division could use.Namely obtain the signal of 50HZ through 1,000,000 frequency dividers, be re-used as the work clock of 100 system Counter modules, simultaneously as the input signal of keyboard; Namely 50MHZ obtains the work clock of signal as Keysheet module of 25HZ through 2,000,000 frequency dividers; The counting pulse signal of Keysheet module to input disappears and trembles process; 100 system up-down counter modules realize the tally function of 0-99; 2 select 1 module to realize selecting the display integer of data and the function of decimal; It is the character code of numeral method that 7 segment decoder modules realize the output Binary Conversion of counter; Binary-decimal decoder module realizes the binary data output signal of counter be converted to required for D/A.
It should be noted that, in this article, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise which key element, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.
Apply specific case herein to set forth principle of the present utility model and embodiment, the explanation of above example just understands method of the present utility model and core concept thereof for helping.The above is only preferred implementation of the present utility model, should be understood that, due to the finiteness of literal expression, and objectively there is unlimited concrete structure, for those skilled in the art, under the prerequisite not departing from the utility model principle, some improvement, retouching or change can also be made, also above-mentioned technical characteristic can be combined by rights; These improve retouching, change or combination, or the design of utility model and technical scheme are directly applied to other occasion without improving, and all should be considered as protection domain of the present utility model.
Claims (7)
1. a switching mode digital display stabilized voltage supply, it comprises power module, it is characterized in that, described power module is connected with Keysheet module, FPGA governor circuit, D/A converter, operational amplifier, display circuit; Described Keysheet module is connected with FPGA governor circuit input end; Described FPGA governor circuit output terminal is connected with display circuit input end, D/A converter input end; Described D/A converter output terminal is connected with operational amplifier; Described D/A converter is set side by side with and is no less than two-way.
2. a kind of switching mode digital display stabilized voltage supply according to claim 1, is characterized in that, be provided with frequency divider in described FPGA governor circuit; Described frequency divider is connected with Keysheet module input end; Described Keysheet module output terminal is connected with counter module; Described counter module output terminal be connected with side by side alternative module and two, decimal system decoding module; Described two, decimal system decoding module is connected with D/A converter; Described alternative module is connected with 7 segment decoders; Described 7 segment decoders are connected with segment encode control end.
3. a kind of switching mode digital display stabilized voltage supply according to claim 2, it is characterized in that, described frequency divider is set side by side with two, and one is 1,000,000 frequency dividers, and another is 2,000,000 frequency dividers; Described 2,000,000 frequency dividers are connected with Keysheet module; Described 1,000,000 frequency dividers are connected with counter module.
4. switching mode digital display stabilized voltage supply according to claim 1, is characterized in that, described FPGA governor circuit adopts EP2C5T144 chip.
5. switching mode digital display stabilized voltage supply according to claim 1, it is characterized in that, described display circuit have employed common cathode digital display tube.
6. switching mode digital display stabilized voltage supply according to claim 1, is characterized in that, described D/A change-over circuit adopts D/AC0832 chip.
7. switching mode digital display stabilized voltage supply according to claim 1, is characterized in that, have employed ISL6443 power supply chip in described power module.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520594630.6U CN204832878U (en) | 2015-08-10 | 2015-08-10 | Switching mode digital display constant voltage power supply |
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|---|---|---|---|
| CN201520594630.6U CN204832878U (en) | 2015-08-10 | 2015-08-10 | Switching mode digital display constant voltage power supply |
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| CN201520594630.6U Expired - Fee Related CN204832878U (en) | 2015-08-10 | 2015-08-10 | Switching mode digital display constant voltage power supply |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106997743A (en) * | 2017-06-02 | 2017-08-01 | 江苏久正光电有限公司 | A kind of test device of Thin Film Transistor-LCD |
| CN110543207A (en) * | 2019-08-29 | 2019-12-06 | 电子科技大学 | four-way adjustable power module for electric control scanning antenna |
| CN110572025A (en) * | 2019-08-29 | 2019-12-13 | 电子科技大学 | multi-path adjustable power supply |
| CN111034051A (en) * | 2017-09-28 | 2020-04-17 | 微芯片技术股份有限公司 | Switched capacitor DAC using bootstrap switches |
-
2015
- 2015-08-10 CN CN201520594630.6U patent/CN204832878U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106997743A (en) * | 2017-06-02 | 2017-08-01 | 江苏久正光电有限公司 | A kind of test device of Thin Film Transistor-LCD |
| CN111034051A (en) * | 2017-09-28 | 2020-04-17 | 微芯片技术股份有限公司 | Switched capacitor DAC using bootstrap switches |
| CN111034051B (en) * | 2017-09-28 | 2023-09-22 | 微芯片技术股份有限公司 | Switched capacitor DAC using bootstrap switch |
| CN110543207A (en) * | 2019-08-29 | 2019-12-06 | 电子科技大学 | four-way adjustable power module for electric control scanning antenna |
| CN110572025A (en) * | 2019-08-29 | 2019-12-13 | 电子科技大学 | multi-path adjustable power supply |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151202 Termination date: 20160810 |