CN204809216U - 一种双面散热的无载体半导体封装结构 - Google Patents

一种双面散热的无载体半导体封装结构 Download PDF

Info

Publication number
CN204809216U
CN204809216U CN201520474417.1U CN201520474417U CN204809216U CN 204809216 U CN204809216 U CN 204809216U CN 201520474417 U CN201520474417 U CN 201520474417U CN 204809216 U CN204809216 U CN 204809216U
Authority
CN
China
Prior art keywords
chip
pin
bonding wire
sheet metal
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201520474417.1U
Other languages
English (en)
Inventor
石磊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tongfu Microelectronics Co Ltd
Original Assignee
Nantong Fujitsu Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nantong Fujitsu Microelectronics Co Ltd filed Critical Nantong Fujitsu Microelectronics Co Ltd
Priority to CN201520474417.1U priority Critical patent/CN204809216U/zh
Application granted granted Critical
Publication of CN204809216U publication Critical patent/CN204809216U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754—Coating
    • H01L2224/37599—Material
    • H01L2224/376—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本实用新型提供了一种双面散热的无载体半导体封装结构，包括金属框架引脚，芯片，焊线和金属片。焊线连接金属框架的引脚和芯片，金属片位于芯片之上。金属框架的引脚与芯片正面的门极通过焊线连接，金属片放置的位置与金属框架的位置相对应，金属片通过助焊剂金属框架和芯片连接。本实用新型的有益效果是：该结构实现了芯片尺寸不同的情况下使用同样尺寸的金属片，降低生产成本。芯片与引脚通过倒打线的方式焊接，同时金属片下面涂高介电材料，使用焊线焊接和金属片桥接结合的焊接方法，无载体的双面散热封装结构使产品的导热性能大幅提高，在提高产品封装良率、降低生产成本的同时满足了大功率、高能耗、高散热产品的性能要求。

Description

一种双面散热的无载体半导体封装结构
技术领域
本实用新型涉及一种基于半导体无载体的封装结构，确切的说是一种双面散热的无载体半导体封装结构。
背景技术
在半导体的封装过程中，焊接技术核心是将芯片的门极和圆区与框架引脚通过焊线或是植球的工艺焊接，构成电路的连通。特别是在应用于大功率产品的封装件中，焊接工艺的可靠性及电热性能尤为重要。传统的焊线焊接和植球焊接技术对工艺的实现有较高要求，其中，在大功率、高能耗的产品生产过程中，焊线焊接后产生的塌丝、断丝、短路现象较多，直接影响产品的可靠性。在植球焊接中，由于植球的形态较难控制，植球的大小、高度等因素都会直接影响产品的成品率，其中，植球形状过大会造成电路短路，形状过小会造成电路接触不良。
为了不断适应市场对于大功率产品的需求，封装件的可靠性、功率、散热等性能要求也需逐渐提高，封装件的金属片桥接封装技术更显得尤为重要。金属片材质通常为铜或铝，表层布有电路，连接芯片和框架引脚的引脚，构成电路的连通，采用金属片代替焊线或植球焊接的技术为桥接焊接技术。金属片桥接封装技术相较焊线焊接以及植球焊接更能满足产品的大功率、高能耗的要求。此外，使用金属片桥接技术更可以有效得降低产品的厚度，缩小产品体积，适用于电子产品更小、更薄的发展趋势。
而现有的金属片桥接技术，也存在一定缺陷。例如，芯片的每一个焊门极和圆区如果只使用一个金属片桥接，就会造成芯片电源短路，芯片功能失效。若使用两个金属片桥接，就需要分别制作不同尺寸及大小的两个或多个金属片，一个金属片焊接芯片正面的门极和框架的第一引脚，另一个金属片焊接芯片正面的圆区和框架的其他引脚。并且以每颗产品为单位桥接，焊接工艺难度较大，产品生产周期较长。若使用焊线焊接和金属片桥接结合的焊接方法，由于金属片位置在焊线的上方，且金属片与框架引脚的相对位置固定，而焊线是有一定弧度的细线，焊线的高度必须与金属片保持一定的距离，而焊线的线型及弧高较难控制，若与金属片触碰，就会造成电路短路，芯片功能失效。为了使线弧具有一定的弧度，传统焊线焊接工艺形成的弧线往往弧高很高，在金属片桥接的工序中，焊线会和金属片接触造成短路。而金属片在焊接时必须保持一定的形状及角度，由于金属片的形状为特制，也就需要制作特殊的模具制作金属片，也需要控制金属片的形状以及高度，增加了产品的成本，给产品的量产带来困难。
而在产品的实际运作过程中，产品内部会产生大量的热量，产品内部温度增高。传统半导体封装体的主要散热途径为向上散热或向下散热，但传统封装体上方有塑封料，下方有载体，会降低封装体本身的散热性能。产品向外散热性能不良会导致产品内部温度过高，产品会有功能不良、甚至失效的风险。
综上所述，传统的金属片桥接技术不能在提高产品封装良率、降低生产成本的同时满足大功率、高能耗、高散热产品的性能要求。
发明内容
为克服现有技术中存在的上述问题，本实用新型提供了一种双面散热的无载体半导体封装结构，包括金属框架引脚，芯片，焊线和金属片。金属框架的第一引脚与芯片正面的门极通过焊线连接，金属框架的其他引脚与芯片正面的圆区通过金属片连接，芯片正面的圆区和和金属框架的其他引脚设置有助焊剂，金属片放置的位置与金属框架的位置相对应，覆盖在芯片正面以及金属框架的其他引脚之上并与之桥接。
优选地，金属框架材质为铜、铝、银或合金。
进一步，芯片的门极与框架的第一引脚连接，焊线直接连接芯片的门极和框架的第一引脚。
进一步地，金属片的下方设置有强介电材料。在金属片的下方(即与芯片连接的一面)涂覆强介电材质，根据金属片需要涂强介电材质的位置，做带有图形的模具，模具上的开口即为需要涂强介电材质的区域。将模具盖在金属片上方，然后刷一层强介电材料，即在金属片表面形成介电层，金属片的材质为铜、铝等金属。
更进一步地，金属片与芯片的圆区和金属框架的其他引脚连接，金属片位置在芯片和金属框架的引脚之上。在芯片表面的圆区和金属框架的其他引脚上面刷助焊剂，然后把金属片盖在芯片和金属框架的其他引脚上面，位置与芯片和金属框架的其他引脚位置相对应，回流焊后，金属片、芯片和金属框架即构成桥接结构。
优选地，金属框架的材质为铜、银或合金等金属。焊线的材质为金、铜、合金等金属，金属片材质为铜、铝等金属，形状为平板状。
与现有技术相比，本实用新型法的有益效果是：金属框架引脚、芯片、焊线与平板状的金属片，构成了一种更为实用的半导体桥接封装结构。节省了生产成本，简化了生产流程，提高产品的良率，保证产品的可靠性，也进一步降低金属片桥接的工艺难度、降低了金属片的生产成本以及产品生产周期。无载体的双面散热封装结构使产品的导热性能大幅提高，本实用新型相比传统的金属片桥接封装结构，在提高产品封装良率、降低生产成本的同时满足了大功率、高能耗、高散热产品的性能要求。
附图说明
图1为金属框架示意图
图2为芯片背面与金属框架粘接后结构示意图
图3为门极与引脚连接后结构示意图
图4为图3中单独引脚焊线焊接部分放大图
图5为倒打线焊接工艺单独引脚焊接顺序图
图6为粘接金属片6后的结构剖面图
图7为产品塑封后结构示意图
图8为产品去除载体和底部助焊剂后结构示意图
图9为芯片与金属框架粘接后结构示意图
具体实施方式
以下结合附图和实施例，对本实用新型进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本实用新型，并不用于限定本实用新型。
在本实用新型的第一实施方式中，提供了一种双面散热的无载体半导体封装结构。该结构包括：金属框架引脚，芯片，焊线和金属片。金属框架的第一引脚与芯片正面的门极通过焊线连接，金属框架的其他引脚与芯片正面的圆区通过金属片连接，芯片正面的圆区和和金属框架的其他引脚设置有助焊剂，金属片放置的位置与金属框架的位置相对应，覆盖在芯片正面以及金属框架的其他引脚之上并与之桥接。
如图1所示，图1为金属框架示意图。该金属框架1的引脚高度明显高于传统引脚的高度，本实施例中的引脚高度大于芯片厚度，金属框架1材质为铜、铝、银或合金等金属。本实用新型的高引脚金属框架1设计并不限于本实施例。
芯片3的背面与金属框架1粘接。如附图2所示，图2为芯片背面与金属框架粘接后结构示意图，2是助焊剂，3是芯片。在金属框架1上粘接芯片3，金属框架1与芯片3的背面通过助焊剂2粘接。具体地，先在金属框架1表面刷一层助焊剂2，然后将芯片3置于金属框架1上，经过回流焊，芯片3背面即与金属框架1粘接。
芯片3正面的门极与金属框架1的第一引脚焊接。芯片表面的压区分为门极及圆区，门极为电源端，区为其他功能区。在本实用新型中，焊线焊接指门极通过焊线与金属框架的第一引脚焊接，圆区焊接指圆区通过金属片与其他引脚桥接。如图3所示，图3为门极与引脚连接后结构示意图，芯片3的门极(图中未示出)通过焊线4与金属框架1的引脚焊接。如图4所示，图4为图3中单独引脚焊线焊接部分放大图，a焊点为芯片的门极，b焊点为金属框架1引脚上的焊点。本实用新型使用倒打线的工艺将a焊点与b焊点焊接。本实用新型中，采用倒打线的方式焊接焊线，如图5所示，图5为倒打线焊接工艺单独引脚焊接顺序图，在倒打线工艺中，先焊接b焊点，然后拉出线段①后打弯，拉出线段②后打弯，再拉出线段③后打弯，再焊接a焊点。采用倒打线的工艺，与传统打线方式相比，可以有效降低焊线的弧高，解决了焊线焊接与金属片桥接相结合产品高度较大的工艺难题，避免了产品焊接后焊线与金属片触碰发生的短路，提高产品的良率，保证产品的可靠性，也进一步降低金属片桥接的工艺难度，保证了后续金属片桥接工序的顺利进行，产品的可靠性得到保证。本领域技术人员应当知晓，在实际生产中焊线的线弧线型并不限于本实施例，本实施例仅对焊线的焊接顺序做了说明。
芯片3圆区与金属框架1的其他引脚桥接。如图6所示，图6为粘接金属片6后的结构剖面图。5是强介电材料，6是金属片。在本步骤中，先在金属片的下面涂一层强介电材料5。然后在芯片3的上面和金属框架1的其他引脚上面涂一层助焊剂2，再把金属片6盖在芯片3的正面的圆区与金属框架1的其他引脚上，金属片6的放置位置与金属框架1的位置相对应，覆盖在所述芯片3正面以及所述金属框架1的其他引脚之上，不覆盖已与晶圆表面的门极焊接的引脚。再进行回流焊，金属片即与芯片3和金属框架1完成桥接。金属片6、芯片3、焊线4以及金属框架1共同构成电路的连通。
再进一步，对产品进行塑封，如图7，图7为产品塑封后结构示意图。在金属片6与芯片3的圆区和金属框架1的引脚桥接之后，对整个产品进行塑封，7为塑封体。
更进一步地，去除金属框架1的载体部分。如图8，图8为产品去除载体和底部助焊剂后结构示意图。
在本实用新型的第二实施例中，对第一实施例进行了改进。具体地，在该实施例中，对第一实施例中芯片3与金属框架1的粘接方式进行了改进，在该实施方式中，金属框架1上面刷有粘片胶8；芯片3与金属框架1粘接；芯片3与金属框架1粘接后烘烤。
图9为芯片与金属框架粘接后结构示意图，1为高引脚设计的金属框架，8是粘片胶，3是芯片。在金属框架1上粘接芯片3，金属框架1与芯片3通过粘片胶8粘接。
与现有技术相比，本实用新型法的有益效果是：金属框架引脚、芯片、焊线与平板状的金属片，构成了一种更为实用的半导体桥接封装结构。节省了生产成本，简化了生产流程，提高产品的良率，保证产品的可靠性，也进一步降低金属片桥接的工艺难度、降低了金属片的生产成本以及产品生产周期。无载体的双面散热封装结构使产品的导热性能大幅提高，本实用新型相比传统的金属片桥接封装结构，在提高产品封装良率、降低生产成本的同时满足了大功率、高能耗、高散热产品的性能要求。
上述说明示出并描述了本实用新型的优选实施例，如前所述，应当理解本实用新型并非局限于本文所披露的形式，不应看作是对其他实施例的排除，而可用于各种其他组合、修改和环境，并能够在本文所述发明构想范围内，通过上述教导或相关领域的技术或知识进行改动。而本领域人员所进行的改动和变化不脱离本实用新型的精神和范围，则都应在本实用新型所附权利要求的保护范围内。

Claims (10)

1.一种双面散热的无载体半导体封装结构，包括金属框架(1)，芯片(3)，焊线(4)和金属片(6)，其特征在于：所述焊线(4)连接金属框架(1)的引脚和芯片(3)，金属片(6)位于芯片(3)之上。
2.如权利要求1所述的双面散热的无载体半导体封装结构，其特征在于，金属框架(1)的引脚高度大于金属芯片的厚度。
3.如权利要求1所述的双面散热的无载体半导体封装结构，其特征在于，所述金属框架(1)的引脚与芯片(3)正面的门极通过焊线(4)连接。
4.如权利要求1所述的双面散热的无载体半导体封装结构，其特征在于，所述芯片(3)和金属框架(1)的正面设置有助焊剂。
5.如权利要求1所述的双面散热的无载体半导体封装结构，其特征在于，所述金属片(6)放置的位置与金属框架(1)的位置相对应，覆盖在所述芯片(3)正面以及所述金属框架(1)的引脚之上。
6.如权利要求1所述的双面散热的无载体半导体封装结构，其特征在于，所述金属片(6)的下方设置有强介电材料。
7.如权利要求1所述的双面散热的无载体半导体封装结构，其特征在于，所述金属片(6)通过助焊剂(2)所述金属框架(1)和芯片(3)连接。
8.如权利要求1所述的双面散热的无载体半导体封装结构，其特征在于，所述金属框架(1)的载体部分去除后只保留金属框架(1)的引脚部分。
9.如权利要求1所述的双面散热的无载体半导体封装结构，其特征在于，所述金属片(6)上表面露出。
10.如权利要求1所述的双面散热的无载体半导体封装结构，其特征在于，所述金属片(6)的形状为平板状。
CN201520474417.1U 2015-06-30 2015-06-30 一种双面散热的无载体半导体封装结构 Active CN204809216U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201520474417.1U CN204809216U (zh) 2015-06-30 2015-06-30 一种双面散热的无载体半导体封装结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201520474417.1U CN204809216U (zh) 2015-06-30 2015-06-30 一种双面散热的无载体半导体封装结构

Publications (1)

Publication Number Publication Date
CN204809216U true CN204809216U (zh) 2015-11-25

Family

ID=54593992

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201520474417.1U Active CN204809216U (zh) 2015-06-30 2015-06-30 一种双面散热的无载体半导体封装结构

Country Status (1)

Country Link
CN (1) CN204809216U (zh)

Similar Documents

Publication Publication Date Title
CN102683509B (zh) Led模块
WO2015043499A1 (zh) 一种半导体封装结构及其成型方法
CN105140205A (zh) 一种双面散热的半导体叠层封装结构
CN103824834A (zh) 一种具有改进型封装结构的半导体器件及其制造方法
CN206116387U (zh) 一种大电流功率半导体器件的封装结构
JP2007300088A5 (zh)
CN101404274B (zh) 三引脚电子器件封装用引线框架、封装结构及其封装方法
CN204809212U (zh) 一种半导体封装结构
CN204809216U (zh) 一种双面散热的无载体半导体封装结构
CN104952857A (zh) 一种无载体的半导体叠层封装结构
CN105047569A (zh) 一种半导体封装方法
CN201629329U (zh) 一种引线框架
TWI237409B (en) Method of fabricating light emitting diode (LED)
CN103887183B (zh) 金/硅共晶芯片焊接方法及晶体管
CN207577624U (zh) 一种金属焊接结构及焊接基片
CN110493954A (zh) 一种qfn器件内埋pcb结构及其制作方法
CN201319374Y (zh) 一种用超声波铜线制造集成电路芯片封装结构
CN105355567A (zh) 双面蚀刻水滴凸点式封装结构及其工艺方法
CN104538377A (zh) 一种基于载体的扇出封装结构及其制备方法
CN111785822A (zh) 一种led倒装芯片封装器件及其封装工艺
CN104600047A (zh) 功率模块及其封装方法
CN204632803U (zh) 一种csp led及基板
CN204741020U (zh) 发光二极管及电子器件
CN203942698U (zh) 基于轻质量微型smt元器件的pcb封装结构
CN205194697U (zh) 一种加强型引线框架

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
C56 Change in the name or address of the patentee
CP01 Change in the name or title of a patent holder

Address after: Jiangsu province Nantong City Chongchuan road 226004 No. 288

Patentee after: Tongfu Microelectronics Co., Ltd.

Address before: Jiangsu province Nantong City Chongchuan road 226004 No. 288

Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong