CN204731577U - A kind of multifunctional signal generator based on FPGA - Google Patents
A kind of multifunctional signal generator based on FPGA Download PDFInfo
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- CN204731577U CN204731577U CN201520385364.6U CN201520385364U CN204731577U CN 204731577 U CN204731577 U CN 204731577U CN 201520385364 U CN201520385364 U CN 201520385364U CN 204731577 U CN204731577 U CN 204731577U
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Abstract
The utility model discloses a kind of multifunctional signal generator based on FPGA, it comprises crystal oscillating circuit, PLL frequency multiplier circuit, frequency dividing circuit, multiple pulse signal combiner circuit, pulse choice and adjustment module, pulse signal modulate circuit, DDS signal generating module, D/A converter and low-pass filter, PLL frequency multiplier circuit exports two-way frequency-doubled signal I and II after receiving the output signal of crystal oscillating circuit simultaneously, signal I is as the reference input clock of DDS signal generating module and D/A converter, D/A converter is connected with between DDS signal generating module and low-pass filter, output frequency division signal III and pulse signal bundle IV while that signal II being after frequency dividing circuit frequency division, multiple pulse signal combiner circuit Received signal strength bundle IV, pulse choice and adjustment module is connected with between multiple pulse signal combiner circuit and pulse signal modulate circuit, signal III is as the change over clock of D/A converter.The utility model has can produce any medium and low frequency signal and function and the advantage that can export a kind of DDS signal and a kind of pulse signal simultaneously.
Description
Technical field
The utility model relates to a kind of multifunctional signal generator based on FPGA.
Background technology
In Fibre Optical Communication Technology and Distributed Optical Fiber Sensing Techniques, continue again rearward to transmit after often needing to do corresponding modulation treatment to the optical carrier being loaded with useful signal transmitted in optical fiber, can receive at signal receiving end the light signal changed according to certain rules, and then be conducive to the electric signal received light signal with certain Changing Pattern being converted to convenient process and observation.But, corresponding signal modulation process to be done to the light signal transmitted in a fiber, first having problems of modulation signal must be solved, especially the medium and low frequency modulation signals such as the various pulse signals of good stability and frequency-adjustable, sinusoidal signal and square-wave signal are produced, most important with process to the conversion doing signal at signal receiving end.Therefore, how to accomplish that can reduce costs and can produce easily the various modulation signal meeting different use occasion and different request for utilization becomes a ring important in optical fiber communication and sensory field of optic fibre.
Few for the usual function singleness of existing commercial signal generator, producible signal type, instrument volume large and heavy and expensive, the problem such as environment for use is restricted, simultaneously in view of FPGA device flourish in recent years, there is the advantages such as low cost, Highgrade integration and miniaturization, flexibly interface mode and control mode, the arithmetic capability of high speed and high-performance, take FPGA as hardware platform, by developing software accordingly with hardware description language to design the more aobvious convenience of various control circuit with flexible, and can be used for multiple workplace.Therefore, adopt FPGA device to design various control circuit and can not only substitute many traditional instrument and equipments and realize more function, also can reduce the R&D costs of Related product and reduce the volume of corresponding instrument equipment simultaneously.
Utility model content
The purpose of this utility model is to overcome the deficiency of the technology such as few, the bulky and environment for use of the producible signal type of existing signal generator is limited, there is provided a kind of multifunctional signal generator based on FPGA, it has the function and advantage that can produce any medium and low frequency modulation signal and can export a kind of DDS signal and a kind of pulse signal simultaneously.
The purpose of this utility model is achieved through the following technical solutions: a kind of multifunctional signal generator based on FPGA comprises crystal oscillating circuit, PLL frequency multiplier circuit, frequency dividing circuit, multiple pulse signal combiner circuit, pulse choice and adjustment module, pulse signal modulate circuit, DDS signal generating module, D/A converter and low-pass filter, PLL frequency multiplier circuit receives the clock signal of crystal oscillating circuit and exports two-way frequency-doubled signal I and II after doing frequency multiplication to it simultaneously, frequency-doubled signal I is as the input reference clock signal of DDS signal generating module and D/A converter, the D/A converter of 12 is connected with between DDS signal generating module and low-pass filter, it is the fractional frequency signal III of 1:1 and the single pulse signal bundle IV of multiple low duty ratio that frequency-doubled signal II exports a dutycycle after frequency dividing circuit frequency division simultaneously, multiple pulse signal combiner circuit receives the single pulse signal bundle IV of multiple low duty ratios that frequency dividing circuit exports, multiple pulse signal combiner circuit output terminal is connected with adjustment module input end with pulse choice, pulse choice is connected the input end of pulse signal modulate circuit with the output terminal of adjustment module, and be the digital-to-analog conversion operating clock signals of fractional frequency signal III as D/A converter of 1:1 using the dutycycle that frequency dividing circuit exports.
Described FPGA comprises PLL frequency multiplier circuit, frequency dividing circuit, multiple pulse signal combiner circuit, pulse choice and adjustment module, DDS signal generating module, described crystal oscillating circuit and FPGA coexist on one piece of FPGA development board, and described pulse signal modulate circuit, D/A converter and low-pass filter are external signal handling equipment.The frequency of the frequency-doubled signal I that PLL frequency multiplier circuit exports and frequency-doubled signal II can be determined by following formula:
,
(formula 1)
for the clock signal frequency that crystal oscillating circuit exports,
with
for the Clock Multiplier Factor arranged in PLL macroefficiency module, wherein
respective frequencies
,
respective frequencies
.
Described multiple pulse signal combiner circuit can generate single pulse signal, dipulse signal and three pulse signals simultaneously.
Described pulse choice and adjustment module comprise pulse pattern selection circuit, FM circuit and pulse width regulating circuit, pulse pattern selection circuit is selected to export single pulse signal as required, dipulse signal, or three pulse signals, FM circuit can the repetition frequency of regulating impulse signal, the pulsewidth of pulse width regulating circuit both adjustable single pulse signal, also two simple venations of adjustable dipulse signal wide and between spacing, spacing also between wide and adjacent two monopulses of three simple venations of adjustable three pulse signals, the pulsewidth of single pulse signal, spacing between wide and two monopulse of the simple venation of dipulse signal, and the adjustment stepping-in amount of spacing between wide and adjacent two monopulses of 3 three simple venations of pulse signal is all determined by following formula:
(formula 2)
In above formula,
wide and that between adjacent two monopulses, spacing regulates the separately stepping-in amount of simple venation for the pulse width of single pulse signal, dipulse signal and three pulse signals, unit is nanosecond (ns),
for the clock signal predominant frequency that crystal oscillating circuit exports, unit is megahertz (MHz),
for Clock Multiplier Factor.
Described DDS signal generating module mainly comprises phase accumulator and several ROM Waveform storage tables two large divisions of 32, the output rreturn value of phase accumulator receive frequency control word and phase accumulator itself, high 14 sampling address as ROM waveform look-up table intercepting operation result after accumulating operation are carried out through phase accumulator, the Wave data in ROM Waveform storage table is read by address lookup mode, and by the D/A converter of 12, the Wave data of reading is carried out D/A conversion formation staircase waveform, staircase waveform exports by forming analog waveform after the filtering of low-pass filter, the waveform of DDS signal is selected by keying mode.
Described pulse signal modulate circuit is RC filtering circuit, realizes the function of the negative overshoot of the pulse signal received and the noise that transfinites being carried out filtering.
Disappear and tremble by the waveform selection operating key that outputs signal described DDS with Verilog HDL hardware description language, output frequency operating key, amplitude operating key and encode, realize button multiplexing function, the waveform that when corresponding button is clicked, control DDS outputs signal, frequency and amplitude, corresponding to the bond distance's type of control wave, repetition frequency and pulsewidth parameter on time, respectively control disappearing of button and to tremble and cataloged procedure realizes in pulse choice and adjustment module.
The beneficial effects of the utility model are: (1) can produce arbitrary medium and low frequency modulation signal, and a kind of DDS signal and a kind of pulse signal can be exported simultaneously, the modulation signal meeting request for utilization can be selected easily and flexibly to modulate carrier signal according to the actual needs of rig-site utilization; (2) repetition frequency of each pulse signal can be regulated by FM circuit, and the simple venation of the pulsewidth of the type of output pulse signal, single pulse signal, dipulse signal is wide and three simple venations of spacing between two monopulse and three pulse signals are wide and spacing between adjacent two monopulses can regulate in keying mode; (3) waveform of DDS signal, output frequency and amplitude all carry out the adjustment of keying formula by button; (4) shake filtering is carried out to the button on FPGA development board and coding realizes button multiplexing function, thus the multiple adjustment realized signal and controlling functions.
Accompanying drawing explanation
Fig. 1 is the utility model block diagram;
Fig. 2 is pulse choice and adjustment module block diagram;
Fig. 3 is DDS signal generating module block diagram;
Fig. 4 be multifunctional signal generator simultaneously output pulse width be 100ns, the simulation result figure that repetition frequency is the single pulse signal of 4kHz and output frequency when being the DDS sinusoidal signal of 1.653MHz;
It is wide for 25ns that Fig. 5 is that multifunctional signal generator exports simple venation simultaneously, the simulation result figure that repetition frequency is the dipulse signal of 10kHz and output frequency when being the DDS square-wave signal of 5MHz;
It is wide for 10ns that Fig. 6 is that multifunctional signal generator exports simple venation simultaneously, the simulation result figure that repetition frequency is three pulse signals of 25kHz and output frequency when being the DDS sawtooth signal of 1.613MHz;
In Fig. 1 to Fig. 3,1, FPGA development board 2, crystal oscillating circuit 3, PLL frequency multiplier circuit 4, DDS signal generating module 5, D/A converter 6, low-pass filter 7, frequency dividing circuit 8, multiple pulse signal combiner circuit 9, pulse choice and adjustment module 10, pulse signal modulate circuit 11, pulse pattern selection circuit 12, FM circuit 13, pulse width regulating circuit 14,32 phase accumulators 15, ROM Waveform storage table, F
ifor the frequency control word being supplied to the frequency multiplied clock signal of DDS signal generating module, M is input phase totalizer.
In Fig. 4 to Fig. 6, the clk 200MHz frequency multiplied clock signal that to be 50MHz clock signal, c1_200 that crystal oscillating circuit exports be obtains after doing quadruple to crystal oscillator clock signal clk, Single_pulse are single pulse signal, and Double_pulse is dipulse signal, Three_pulse is three pulse signals, dds_data_out is the DDS signal that DDS signal generating module exports.
Embodiment
As shown in Figure 1, the reference clock signal exported the crystal oscillating circuit 2 on FPGA development board 1 is as the input clock signal of PLL frequency multiplier circuit 3, under QUARTUS II software development environment, adopt Verilog HDL hardware description language coding to design the frequency multiplier circuit module of crystal oscillator clock signal, and by calling the macroefficiency module installation Clock Multiplier Factor equimultiple frequency module parameter of PLL by name, export frequency-doubled signal I and frequency-doubled signal II after PLL frequency multiplier circuit does process of frequency multiplication and does temporal constraint simultaneously, wherein frequency-doubled signal I is as the input reference clock signal of DDS signal generating module 4 and D/A converter 5, the DDS signal data read from the ROM Waveform storage table 15 of DDS signal generating module 4 exports staircase waveform after D/A converter 5 is changed, again by exporting analog waveform after the smoothing filtering of low-pass filter 6, the other road frequency-doubled signal II that PLL frequency multiplier circuit exports is as the input clock signal of frequency dividing circuit 7, be the fractional frequency signal III of 1:1 and the single pulse signal bundle IV of multiple low duty ratio by obtaining dutycycle after arranging the different divide ratio of many groups and carrying out frequency division to frequency multiplied clock signal II in frequency dividing circuit 7, wherein dutycycle is the digital-to-analog conversion operating clock signals of fractional frequency signal III as D/A converter of 1:1, multiple pulse signal combiner circuit 8 receives the pulse signal bundle IV of self frequency-dividing circuit 7, synthesize simultaneously and export single pulse signal, dipulse signal and three pulse signals, through pulse choice and adjustment module 9 selection with regulate after export the pulse signal of expectation, again by negative overshoot and the noise that transfinites of pulse signal modulate circuit 10 filtering pulse signal,
As shown in Figure 2, described pulse choice and adjustment module 9 comprise pulse pattern selection circuit 11, FM circuit 12 and pulse width regulating circuit 13, single pulse signal, dipulse signal and three pulse signals that pulse pattern selection circuit 11 can export multiple pulse signal combiner circuit 8 as required carry out keying formula and select to export, the repetition frequency of the pulse signal that pulse pattern selection circuit 11 exports carries out the adjustment of keying formula by FM circuit 12, then by pulse width regulating circuit 13 with the pulse width of keying mode regulating impulse signal.
The selection of pulse signal type, the adjustment of pulse repetition frequency, the adjustment of pulse signal pulsewidth, the selection of DDS signal waveform, the adjustment of DDS signal output frequency and the adjustment of DDS signal output amplitude realize possessing button multiplexing function keying formula after all passing through to adopt Verilog HDL hardware description language coding to carry out shaking filtering and coding to the button on FPGA development board under QUARTUS II software development environment regulates, the corresponding parameter of DDS signal is regulated when each button is clicked, respectively by the corresponding parameter of bond distance's regulating impulse signal on time, the shake filtering of button and cataloged procedure complete in pulse choice and adjustment module.
As shown in Figure 3, described DDS signal generating module is partly formed with several ROM Wave data storage lists etc. primarily of the phase accumulator of 32, F
ifor doing through PLL frequency multiplier circuit the reference clock signal inputting DDS signal generating module after frequency multiplication and temporal constraint, phase accumulator receive frequency control word M and the output rreturn value of itself, phase accumulator exports high 14 bit data of data as the sampling address value of ROM Wave data storage list, reads the Wave data in ROM Waveform storage table and the D/A converter sending 12 to carries out digital-to-analog conversion by address lookup mode.
The output frequency of DDS signal is determined by following formula:
(formula 3)
In above formula,
for the output frequency of DDS signal,
for the frequency control word of input phase totalizer,
for the reference clock signal frequency that crystal oscillating circuit exports,
for Clock Multiplier Factor,
for the word length of phase accumulator, in the utility model
value gets 32.
Pin assignment is carried out to each signal, compilation and synthesis working procedure again after settling signal pin assignment, and by download program to fpga chip, connect pulse signal modulate circuit, D/A converter and low-pass filter and just can export a kind of DDS signal and a kind of pulse signal simultaneously, just can change the type of pulse signal, repetition frequency and pulse width by long by the corresponding button that controls, click the corresponding button that controls and then can change the waveform of DDS signal, output frequency and amplitude.
A kind of multifunctional signal generator based on FPGA exports the functional simulation figure of a kind of DDS signal and a kind of pulse signal as shown in Figure 4, Figure 5 and Figure 6 simultaneously, under Quartus II software development environment, write test file, add test and excitation signal and after compilation and synthesis runs project file again, call Modelsim emulation tool and do the simulation result that rtl simulation can obtain as shown in Figures 4 to 6.
Claims (6)
1. the multifunctional signal generator based on FPGA, it is characterized in that: it comprises crystal oscillating circuit, PLL frequency multiplier circuit, frequency dividing circuit, multiple pulse signal combiner circuit, pulse choice and adjustment module, pulse signal modulate circuit, DDS signal generating module, D/A converter and low-pass filter, PLL frequency multiplier circuit receives the clock signal from crystal oscillating circuit and exports two-way frequency-doubled signal after being done frequency multiplication simultaneously, wherein a road frequency-doubled signal is as the input reference clock of DDS signal generating module and D/A converter, D/A converter is connected with between DDS signal generating module and low-pass filter, an other road frequency-doubled signal then after frequency dividing circuit frequency division, exports multiple low duty ratio simultaneously and the adjustable single pulse signal Shu He mono-tunnel dutycycle of repetition frequency is the fractional frequency signal of 1:1, multiple pulse signal combiner circuit receives the single pulse signal bundle of multiple low duty ratios that frequency dividing circuit exports, pulse choice and adjustment module is connected with between multiple pulse signal combiner circuit and pulse signal modulate circuit, the other road dutycycle that frequency dividing circuit exports be 1:1 fractional frequency signal input D/A converter and as the digital-to-analog conversion operating clock signals of D/A converter,
Described FPGA comprises PLL frequency multiplier circuit, frequency dividing circuit, multiple pulse signal combiner circuit, pulse choice and adjustment module, DDS signal generating module, described crystal oscillating circuit and FPGA coexist on one piece of FPGA development board, and described pulse signal modulate circuit, D/A converter and low-pass filter are external signal handling equipment.
2. a kind of multifunctional signal generator based on FPGA according to claim 1, is characterized in that: described multiple pulse signal combiner circuit can synthesize single pulse signal, dipulse signal and three pulse signals simultaneously.
3. a kind of multifunctional signal generator based on FPGA according to claim 1, it is characterized in that: described pulse choice and adjustment module comprise pulse pattern selection circuit, FM circuit and pulse width regulating circuit, pulse pattern selection circuit is selected to export single pulse signal as required, dipulse signal, or three pulse signals, FM circuit can the repetition frequency of regulating impulse signal, the pulsewidth of pulse width regulating circuit both adjustable single pulse signal, also two simple venations of adjustable dipulse signal wide and between spacing, spacing also between wide and adjacent two monopulses of three simple venations of adjustable three pulse signals.
4. a kind of multifunctional signal generator based on FPGA according to claim 3, is characterized in that: the adjustment of the selection of described pulse signal type, the adjustment of repetition frequency and pulse width carries out the adjustment of keying formula by the different button of three on FPGA development board.
5. a kind of multifunctional signal generator based on FPGA according to claim 1, is characterized in that: the described multifunctional signal generator based on FPGA can produce arbitrary medium and low frequency modulation signal and can export a kind of DDS signal and a kind of pulse signal simultaneously.
6. a kind of multifunctional signal generator based on FPGA according to claim 1, it is characterized in that: the described multifunctional signal generator based on FPGA is encoded to the button on FPGA development board by adopting hardware description language coding, the waveform selection key that control DDS is outputed signal, frequency control key and amplitude operating key have button multiplexing function all simultaneously, the waveform of controls DDS output signal, output frequency and amplitude when corresponding button is clicked, corresponding press the bond distance's type of control wave, repetition frequency and pulse width on time.
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Cited By (7)
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| CN105842562A (en) * | 2016-03-30 | 2016-08-10 | 东莞市广安电气检测中心有限公司 | Device for testing immunity to common-mode conducted disturbance |
| CN106354196A (en) * | 2016-09-29 | 2017-01-25 | 华东电子工程研究所（中国电子科技集团公司第三十八研究所） | Low-noise broadband signal generator and signal generating method |
| CN108107426A (en) * | 2018-01-31 | 2018-06-01 | 菏泽学院 | A kind of radio altimeter |
| CN109590280A (en) * | 2018-11-28 | 2019-04-09 | 天津科技大学 | A kind of scaler system of the supersonic guide-wave liquid-filling pipe based on FPGA |
| CN109828632A (en) * | 2018-12-29 | 2019-05-31 | 武汉光谷互连科技有限公司 | A kind of adjustable ultra-narrow Multi-path synchronous pulse generating unit and method based on FPGA |
| CN113985761A (en) * | 2021-09-30 | 2022-01-28 | 歌尔股份有限公司 | Pulse generation control method based on FPGA, terminal equipment and readable storage medium |
| CN114499470A (en) * | 2022-04-06 | 2022-05-13 | 之江实验室 | Nanosecond programmable pulse signal generator |
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2015
- 2015-06-08 CN CN201520385364.6U patent/CN204731577U/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105842562A (en) * | 2016-03-30 | 2016-08-10 | 东莞市广安电气检测中心有限公司 | Device for testing immunity to common-mode conducted disturbance |
| CN105842562B (en) * | 2016-03-30 | 2018-12-21 | 东莞市广安电气检测中心有限公司 | A kind of device for the test of common mode conduction interference immunity to interference |
| CN106354196A (en) * | 2016-09-29 | 2017-01-25 | 华东电子工程研究所（中国电子科技集团公司第三十八研究所） | Low-noise broadband signal generator and signal generating method |
| CN106354196B (en) * | 2016-09-29 | 2019-11-12 | 华东电子工程研究所（中国电子科技集团公司第三十八研究所） | Low noise wideband signal generator and signal generating method |
| CN108107426A (en) * | 2018-01-31 | 2018-06-01 | 菏泽学院 | A kind of radio altimeter |
| CN109590280A (en) * | 2018-11-28 | 2019-04-09 | 天津科技大学 | A kind of scaler system of the supersonic guide-wave liquid-filling pipe based on FPGA |
| CN109828632A (en) * | 2018-12-29 | 2019-05-31 | 武汉光谷互连科技有限公司 | A kind of adjustable ultra-narrow Multi-path synchronous pulse generating unit and method based on FPGA |
| CN113985761A (en) * | 2021-09-30 | 2022-01-28 | 歌尔股份有限公司 | Pulse generation control method based on FPGA, terminal equipment and readable storage medium |
| CN113985761B (en) * | 2021-09-30 | 2024-02-09 | 歌尔股份有限公司 | Pulse generation control method based on FPGA, terminal equipment and readable storage medium |
| CN114499470A (en) * | 2022-04-06 | 2022-05-13 | 之江实验室 | Nanosecond programmable pulse signal generator |
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