CN204681074U - DC power supply current foldback circuit - Google Patents
DC power supply current foldback circuit Download PDFInfo
- Publication number
- CN204681074U CN204681074U CN201520426355.7U CN201520426355U CN204681074U CN 204681074 U CN204681074 U CN 204681074U CN 201520426355 U CN201520426355 U CN 201520426355U CN 204681074 U CN204681074 U CN 204681074U
- Authority
- CN
- China
- Prior art keywords
- delayer
- output
- semiconductor
- oxide
- channel enhancement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000001514 detection method Methods 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims description 40
- 238000000034 method Methods 0.000 abstract description 6
- 238000001914 filtration Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Landscapes
- Inverter Devices (AREA)
Abstract
The utility model discloses DC power supply current foldback circuit; comprise reference voltage input line, detection signal input line, output line, the first comparator, with door, the first delayer, the second delayer, the 3rd delayer, filter and inverter; reference voltage input line, detection signal input line are connected with two inputs of the first comparator respectively, and filter is connected in reference voltage input line.The output of the first comparator and the second delayer is connected respectively with two inputs of door, the input/output terminal of the first delayer connects the first comparator and the second delayer respectively, 3rd electric capacity one end is connected on the circuit between the first delayer and the second delayer, its other end ground connection.The input/output terminal of the 3rd delayer connects and door and inverter respectively, and output line is connected with the output of inverter.The utility model overall structure is simple, uses components and parts few, is convenient to implement, and can avoid the phenomenon occurring in testing process by mistake turning off during the utility model application.
Description
Technical field
The utility model relates to the protective device of power supply, specifically DC power supply current foldback circuit.
Background technology
The power-supply device application such as current Switching Power Supply, UPS are more and more extensive, and these equipment will detect voltage, the current signal of main circuit bar none.Existing current detection circuit is generally made up of current-sensing circuit, comparison circuit and output stage, what it adopted is " interruption " pattern, in testing process, for any overcurrent condition, as long as load current is greater than Limited Current, all will make the power failure of Switching Power Supply, easily be subject to the interference of the instantaneous large-signal of electrical network, and cause and turn off by mistake.
Utility model content
The purpose of this utility model is to overcome the deficiencies in the prior art, provides a kind of DC power supply current foldback circuit, can avoid the phenomenon occurring in testing process by mistake turning off during its application.
The utility model solves the problem and is achieved through the following technical solutions: DC power supply current foldback circuit, comprise reference voltage input line, detection signal input line, output line, the first comparator, with door, the first delayer, the second delayer, the 3rd delayer, filter and inverter, described reference voltage input line, detection signal input line are connected with the in-phase input end of the first comparator and inverting input respectively, and described filter is connected in reference voltage input line; Describedly be connected the first comparator output terminal and the second delayer output respectively with two inputs of door, the input of the first delayer, output connect the output of the first comparator and the input of the second delayer respectively, described 3rd electric capacity one end is connected on the circuit between the first delayer and the second delayer, its other end ground connection; The input of described 3rd delayer is connected with the output of door, and its output is connected with inverter, and described output line is connected with the output of inverter.The external power tube of output line of the present utility model, the utility model realizes corresponding current detecting by the switch detecting power tube in power-supply device.
Further, described filter comprises the first electric capacity and the second electric capacity, described first electric capacity and the second Capacitance parallel connection, and one end of this parallel branch is connected in reference voltage input line, its other end ground connection.Filter of the present utility model adopts two electric capacity realizations in parallel, is convenient to implement.
Further, described first delayer, the second delayer and the 3rd delayer all adopt even number of inverters series connection to be formed.So, the first delayer of the present utility model, the second delayer and the 3rd delayer can not change the logic state of incoming level when applying.
Further, described 3rd inverter between delayer and output line comprises the first P-channel enhancement type metal-oxide-semiconductor and a N channel enhancement metal-oxide-semiconductor, the grid of described first P-channel enhancement type metal-oxide-semiconductor is connected with the grid of a N channel enhancement metal-oxide-semiconductor, and the 3rd delayer is connected on the circuit between the grid of the first P-channel enhancement type metal-oxide-semiconductor and the grid of a N channel enhancement metal-oxide-semiconductor; The source electrode of described first P-channel enhancement type metal-oxide-semiconductor is connected with the drain electrode of a N channel enhancement metal-oxide-semiconductor, and output line is connected on the circuit between the source electrode of the first P-channel enhancement type metal-oxide-semiconductor and the drain electrode of a N channel enhancement metal-oxide-semiconductor; The drain electrode of described first P-channel enhancement type metal-oxide-semiconductor connects power supply, the source ground of a N channel enhancement metal-oxide-semiconductor.The utility model adopts a P-channel enhancement type metal-oxide-semiconductor and a N channel enhancement metal-oxide-semiconductor to be connected to inverter version, adopts components and parts few, is convenient to implement.
In sum, the utility model has following beneficial effect: (1) the utility model overall structure is simple, use components and parts are few, be convenient to implement, cost is low, 3rd electric capacity repeated charge during the utility model application, after change in voltage on the 3rd electric capacity arrives the logic level threshold value of the second delayer, the second delayer just reverses, so, the utility model has certain function of shielding, just power tube is closed when only having the continuous action time of over-current signal to exceed setting range, thus the phenomenon occurring shutoff by mistake in testing process can be avoided, ensure carrying out smoothly of testing process.
(2) the utility model is connected with filter in reference voltage input line, and when the utility model is applied, the part ripple of supply voltage that DC power supply exports can be carried out filtering by filter, can promote precision when the utility model carries out input.
Accompanying drawing explanation
Fig. 1 is the structural representation of the utility model specific embodiment.
Name in accompanying drawing corresponding to Reference numeral is called: 1, reference voltage input line, 2, detection signal input line, 3, output line, A1, the first comparator, B1, the first delayer, B2, the second delayer, B3, the 3rd delayer, C1, the first electric capacity, C2, the second electric capacity, C3, the 3rd electric capacity, AND and door, VCC, power supply, P1, the first P-channel enhancement type metal-oxide-semiconductor, N1, a N channel enhancement metal-oxide-semiconductor.
Embodiment
Below in conjunction with embodiment and accompanying drawing, detailed description is further done to the utility model, but execution mode of the present utility model is not limited thereto.
Embodiment:
As shown in Figure 1; DC power supply current foldback circuit; comprise reference voltage input line 1, detection signal input line 2, output line 3, first comparator A1, with door AND, the first delayer B1, the second delayer B2, the 3rd delayer B3, filter and inverter; wherein; reference voltage input line 1, detection signal input line 2 are connected with the in-phase input end of the first comparator A1 and inverting input respectively, and filter is connected in reference voltage input line 1.The present embodiment be connected the first comparator A1 output and the second delayer B2 output respectively with two inputs of door AND, the input of the first delayer B1, output connect the output of the first comparator A1 and the input of the second delayer B2 respectively, 3rd electric capacity C3 one end is connected on the circuit between the first delayer B1 and the second delayer B2, its other end ground connection.The input of the 3rd delayer B3 of the present embodiment is connected with the output of door AND, and its output is connected with inverter, and output line 3 is connected with the output of inverter.
The filter of the present embodiment comprises the first electric capacity C1 and the second electric capacity C2, wherein, the first electric capacity C1 and the second electric capacity C2 is 100uF, and the first electric capacity C1 is in parallel with the second electric capacity C2, one end of this parallel branch is connected in reference voltage input line 1, its other end ground connection.First delayer B1, the second delayer B2 of the present embodiment and the 3rd delayer B3 all adopt even number of inverters to connect and are formed, so, all do not changed the logic state of incoming level at output by each delayer in the present embodiment, and be only maintenance or the amplification of input signal being carried out to driving force, therefore after the time delay of the 3rd electric capacity C3, finally make to reach unanimity with the logical signal of two of door AND inputs, thus make to reverse with door AND output level.
Inverter between the 3rd delayer B3 of the present embodiment and output line 3 comprises a first P-channel enhancement type metal-oxide-semiconductor P1 and N channel enhancement metal-oxide-semiconductor N1, wherein, the grid of the first P-channel enhancement type metal-oxide-semiconductor P1 is connected with the grid of a N channel enhancement metal-oxide-semiconductor N1, and the 3rd delayer B3 is connected on the circuit between the grid of the first P-channel enhancement type metal-oxide-semiconductor P1 and the grid of a N channel enhancement metal-oxide-semiconductor N1.The source electrode of the first P-channel enhancement type metal-oxide-semiconductor P1 of the present embodiment is connected with the drain electrode of a N channel enhancement metal-oxide-semiconductor N1, and output line 3 is connected on the circuit between the source electrode of the first P-channel enhancement type metal-oxide-semiconductor P1 and the drain electrode of a N channel enhancement metal-oxide-semiconductor N1.The drain electrode of the first P-channel enhancement type metal-oxide-semiconductor P1 of the present embodiment meets power supply VCC, the source ground of a N channel enhancement metal-oxide-semiconductor N1.
When the present embodiment is applied, the external power tube of output line 3, current signal to be detected inputs from detection signal input line 2, reference voltage inputs from reference voltage input line 1, current signal to be detected with after filtering after reference voltage compare, when higher than reference voltage value, first comparator A1 outputs signal reversal connection, reverse with the input end signal that the first comparator A1 output is directly connected with door AND, but immediately do not reverse with another input of door AND, but by the first delayer B1 to the 3rd electric capacity C3 charge or discharge, until the change in voltage on the 3rd electric capacity C3 is reversed after arriving the logic level threshold value of the second delayer B2, after reversing with door AND signal, again through inverter process, then for power tube that drive singal output line 3 is external.
Above content is the further description done the utility model in conjunction with concrete preferred implementation, can not assert that embodiment of the present utility model is confined to these explanations.For the utility model person of an ordinary skill in the technical field, not departing from other execution modes drawn under the technical solution of the utility model, all should be included in protection range of the present utility model.
Claims (4)
1. DC power supply current foldback circuit, it is characterized in that, comprise reference voltage input line (1), detection signal input line (2), output line (3), the first comparator (A1), with door (AND), the first delayer (B1), the second delayer (B2), the 3rd delayer (B3), filter and inverter, described reference voltage input line (1), detection signal input line (2) are connected with the in-phase input end of the first comparator (A1) and inverting input respectively, and described filter is connected in reference voltage input line (1); Describedly be connected the first comparator (A1) output and the second delayer (B2) output respectively with two inputs of door (AND), the input of the first delayer (B1), output connect the output of the first comparator (A1) and the input of the second delayer (B2) respectively, described 3rd electric capacity (C3) one end is connected on the circuit between the first delayer (B1) and the second delayer (B2), its other end ground connection; The input of described 3rd delayer (B3) is connected with the output of door (AND), and its output is connected with inverter, and described output line (3) is connected with the output of inverter.
2. DC power supply current foldback circuit according to claim 1; it is characterized in that; described filter comprises the first electric capacity (C1) and the second electric capacity (C2); described first electric capacity (C1) is in parallel with the second electric capacity (C2); one end of this parallel branch is connected in reference voltage input line (1), its other end ground connection.
3. DC power supply current foldback circuit according to claim 1, is characterized in that, described first delayer (B1), the second delayer (B2) and the 3rd delayer (B3) all adopt even number of inverters to connect and formed.
4. according to the DC power supply current foldback circuit in claims 1 to 3 described in any one, it is characterized in that, inverter between described 3rd delayer (B3) and output line (3) comprises the first P-channel enhancement type metal-oxide-semiconductor (P1) and a N channel enhancement metal-oxide-semiconductor (N1), the grid of described first P-channel enhancement type metal-oxide-semiconductor (P1) is connected with the grid of a N channel enhancement metal-oxide-semiconductor (N1), 3rd delayer (B3) is connected on the circuit between the grid of the first P-channel enhancement type metal-oxide-semiconductor (P1) and the grid of a N channel enhancement metal-oxide-semiconductor (N1), the source electrode of described first P-channel enhancement type metal-oxide-semiconductor (P1) is connected with the drain electrode of a N channel enhancement metal-oxide-semiconductor (N1), and output line (3) is connected on the circuit between the source electrode of the first P-channel enhancement type metal-oxide-semiconductor (P1) and the drain electrode of a N channel enhancement metal-oxide-semiconductor (N1), the drain electrode of described first P-channel enhancement type metal-oxide-semiconductor (P1) connects power supply (VCC), the source ground of a N channel enhancement metal-oxide-semiconductor (N1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520426355.7U CN204681074U (en) | 2015-06-19 | 2015-06-19 | DC power supply current foldback circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520426355.7U CN204681074U (en) | 2015-06-19 | 2015-06-19 | DC power supply current foldback circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204681074U true CN204681074U (en) | 2015-09-30 |
Family
ID=54180742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520426355.7U Expired - Fee Related CN204681074U (en) | 2015-06-19 | 2015-06-19 | DC power supply current foldback circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204681074U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113037063A (en) * | 2021-05-25 | 2021-06-25 | 珠海市杰理科技股份有限公司 | Zero-crossing self-calibration circuit, DC/DC converter and power management chip |
| CN117833888A (en) * | 2024-03-05 | 2024-04-05 | 成都市易冲半导体有限公司 | Time delay circuit, rectifying circuit and rectifying chip thereof |
-
2015
- 2015-06-19 CN CN201520426355.7U patent/CN204681074U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113037063A (en) * | 2021-05-25 | 2021-06-25 | 珠海市杰理科技股份有限公司 | Zero-crossing self-calibration circuit, DC/DC converter and power management chip |
| CN117833888A (en) * | 2024-03-05 | 2024-04-05 | 成都市易冲半导体有限公司 | Time delay circuit, rectifying circuit and rectifying chip thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN203674696U (en) | Short circuit protection circuit | |
| CN202083915U (en) | Button switch control circuit with zero standby power consumption | |
| CN204243730U (en) | The current foldback circuit of Intelligent Power Module and air conditioner | |
| CN204761334U (en) | Motor control circuit | |
| CN205232174U (en) | Oscillating circuit | |
| CN204422720U (en) | Electric automobile high-voltage system and relay status pick-up unit thereof | |
| CN103199506A (en) | Over-current protection circuit and backlight module of light source drive module | |
| CN206727643U (en) | A kind of under-voltage and overvoltage crowbar | |
| CN204681074U (en) | DC power supply current foldback circuit | |
| CN204190483U (en) | Power supply switch circuit | |
| CN103353569A (en) | Relay connection state detecting apparatus | |
| CN104362842A (en) | Switching power supply and surge protection circuit and method adaptive to same | |
| CN205263206U (en) | Three phase voltage phase sequence detection circuit | |
| CN103926516B (en) | Online diode detection circuit | |
| CN203871840U (en) | Programmable, safe, energy-saving leakage protector | |
| WO2021088259A1 (en) | Control system and method for power backup system | |
| CN201726333U (en) | High-speed inverse power supply | |
| CN104057181A (en) | Open-phase protection circuit for inverter welding machine | |
| CN208386141U (en) | output protecting device and terminal controller | |
| CN204333921U (en) | The multiple level Spark plug optical fiber sensor system of locking function | |
| CN203368322U (en) | Low-loss series capacitor voltage-sharing device | |
| CN101738526B (en) | Direct current output voltage test circuit for power factor correction control circuit | |
| CN202094612U (en) | Battery management system | |
| CN201976078U (en) | Relay pulse signal driving circuit with turnoff protection | |
| CN209088529U (en) | Frequency converter output earth short circuit protective device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150930 Termination date: 20180619 |