CN204596791U - Display unit - Google Patents
Display unit Download PDFInfo
- Publication number
- CN204596791U CN204596791U CN201520041234.0U CN201520041234U CN204596791U CN 204596791 U CN204596791 U CN 204596791U CN 201520041234 U CN201520041234 U CN 201520041234U CN 204596791 U CN204596791 U CN 204596791U
- Authority
- CN
- China
- Prior art keywords
- opening
- insulating barrier
- display unit
- metal level
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The utility model discloses a kind of display unit, comprises array basal plate, defines the dot structure of multiple arrayed.Those dot structures have respectively: semi-conductor layer, are positioned on this substrate; One the first metal layer, is positioned on this substrate; One first insulating barrier, is positioned on this semiconductor layer, and this first insulating barrier has one first opening, and this first opening exposes an end face of this semiconductor layer and a side of this first insulating barrier; One second metal level, is positioned on this first insulating barrier, and is formed at this end face of this semiconductor layer and this side of this first insulating barrier via this first opening; And one second insulating barrier, be positioned on this second metal level and this first insulating barrier, and this second insulating barrier has one second opening, wherein this second opening exposes this second metal level be positioned on this side of this first insulating barrier.
Description
Technical field
The utility model relates to display unit, and particularly relates to the display unit utilizing thin-film transistor.
Background technology
In order to realize high-speed image process and high-quality show image, the flat-panel screens in recent years as color liquid crystal display arrangement uses widely.In liquid crystal indicator, generally include two upper and lower substrates, to bind or involution material is bonded together.And liquid crystal material is received between two substrates, in order to keep distance fixing between two plates, the particle with certain particle diameter is distributed between above-mentioned two plates.
Usually, lower substrate surface is formed with the thin-film transistor for being used as switch element, this thin-film transistor have the gate electrode (gate electrode) being connected to scan line (scanning line), the source electrode (source electrode) being connected to data wire (data line), be connected to the drain electrode (drain electrode) of pixel electrode (pixel electrode).And upper substrate is placed in above infrabasal plate, this upper substrate surface is formed with a filter and multiple light screening material (as being made up of resin black matrix (Resin BM)).The periphery of this two substrates has the bonding of involution material to be fixed, and has liquid crystal material between two substrates.Infrabasal plate is also referred to as array base palte (array substrate), and elements as several in thin-film transistor, contactant etc. formed thereon are then usually made by several lithographic fabrication process.
But, along with the lifting trend of the image resolution of display unit, during the several element just needing formation on infrabasal plate more to reduce as thin-film transistor, contactant equidimension, provide the array base palte of the aperture opening ratio performance that can maintain or more promote display unit.
Utility model content
The new object of this practicality is to provide a kind of display unit, to solve the problem.
For reaching above-mentioned purpose, the utility model provides a kind of display unit, comprises: array basal plate, defines the dot structure of multiple arrayed.Those dot structures have respectively: semi-conductor layer, are positioned on a substrate; One the first metal layer, is positioned on this substrate; One first insulating barrier, is positioned on this semiconductor layer, and this first insulating barrier has one first opening, and this first opening exposes an end face of this semiconductor layer and a side of this first insulating barrier; One second metal level, is positioned on this first insulating barrier, and is formed at this end face of this semiconductor layer and this side of this first insulating barrier via this first opening; And one second insulating barrier, be positioned on this second metal level and this first insulating barrier, and this second insulating barrier has one second opening, wherein, this second opening exposes this second metal level be positioned on this side of this first insulating barrier, wherein, this first opening, this second opening and this first metal layer putting in order as this first metal layer, this second opening along a direction, and this first opening.
The area of this second metal level that this second opening exposes is greater than the area of this end face of this semiconductor layer that this first opening exposes.
This second metal level and this first metal layer partly overlap.
This first metal layer comprises along the spaced first grid polar curve of first direction and a second gate line, and this second metal level comprises along spaced one first data wire of a second direction and one second data wire, this first direction is different from this second direction, this first grid polar curve, this second gate line, this first data wire and this second data line definition one pixel region, this first opening and this second opening are positioned at this pixel region, and this semiconductor layer is electrically connected with this first data wire.
This second opening is between this first opening and this first data wire.
This second opening portion is overlapped in this first metal layer.
This first opening has one first geometric center, and this second opening has one second geometric center, and wherein a line of this first geometric center and this second geometric center and this first grid polar curve have an angle, and this angle is greater than 0 degree and is less than 90 degree.According to another embodiment, above-mentioned display unit, also comprises: a transparent substrates; And a display layer, be arranged between this transparent substrates and this array base palte.
This display unit also comprises one first transparency electrode, and this first transparency electrode is electrically connected with this second metal level by this second opening.
This display layer is a liquid crystal layer or an Organic Light Emitting Diode layer.
The utility model has the advantage of, when reducing element, the overlay area of the transparency electrode in the P of pixel region can be increased, and then increase the effective vent rate of pixel region P.
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and the accompanying drawing appended by coordinating, be described in detail below.
Accompanying drawing explanation
Fig. 1 is the upper schematic diagram of the layout situation of a kind of array base palte of an embodiment of the present utility model;
Fig. 2 is the schematic diagram of the section situation of the array base palte along 2-2 line segment in Fig. 1 of an embodiment of the present utility model;
Fig. 3 is the upper schematic diagram of the layout situation of a kind of array base palte of another embodiment of the present utility model;
Fig. 4 is the upper schematic diagram of the layout situation of a kind of array base palte of another embodiment of the present utility model;
Fig. 5 is the upper schematic diagram of the layout situation of a kind of array base palte of another embodiment of the present utility model;
Fig. 6 is the schematic diagram of the section situation of the array base palte along 6-6 line segment in Fig. 5 of an embodiment of the present utility model;
Fig. 7 is the upper schematic diagram of the layout situation of a kind of array base palte of another embodiment of the present utility model;
Fig. 8 is the upper schematic diagram of the layout situation of a kind of array base palte of another embodiment of the present utility model; And
Fig. 9 is the generalized section of a kind of display unit of an embodiment of the present utility model.
Symbol description
10,10 ' ~ array base palte
100 ~ substrate
102 ~ semiconductor layer
102a ~ drain region
104 ~ insulating barrier
106 ~ metal level
108 ~ insulating barrier
110 ~ the first openings
112 ~ metal level
112 ' ~ metal level
116 ~ insulating barrier
118 ~ the second openings
120 ~ transparency electrode
300 ~ array base palte
350 ~ display layer
400 ~ transparent substrates
500 ~ display unit
A ~ geometric center
B ~ geometric center
P ~ pixel region
α ~ angle
Embodiment
Please refer to Fig. 1-Fig. 2, show a series of schematic diagrames of a kind of array base palte 10 according to an embodiment of the present utility model, it is applicable to the application of the display unit as color liquid crystal display arrangement.At this, Fig. 1 is a upper schematic diagram, and Fig. 2 is then a generalized section, to show the section situation of of the array base palte along 2-2 line segment in Fig. 1.
Please refer to Fig. 1, array base palte 10 mainly comprises: the semiconductor layer 102 of a substrate 100 (do not show at this, refer to Fig. 2), several U-shaped, is arranged on one of substrate 100 separatedly; Several metal level 106, along the first direction as X-direction, along stretching, compartment of terrain is arranged on one of substrate 100, and covers one of this little semiconductor layer 104 respectively; One insulating barrier 108 (do not show at this, refer to Fig. 2), is formed on substrate 100, semiconductor layer 102, this little the first metal layer 106; Several metal level 112, along the second direction as Y-direction along stretching, compartment of terrain is arranged on insulating barrier 108 and partly cover of one of this little semiconductor layer 102; Several metal level 112 ', one that is arranged at the insulating barrier 108 between two adjacent metal levels 112 respectively covers another portion of one of this little semiconductor layer 102 with part; Several first opening 110, be arranged within insulating barrier 108 separatedly, (do not show at this with the end face in several portions of exposing this little semiconductor layer 102 respectively, refer to Fig. 2), one of metal level 112 and metal level 112 ' then fills within one of this little first opening 110, to form the electrically connect relation between semiconductor layer 102 respectively; One insulating barrier 116 (do not show at this, refer to Fig. 2), smooth substrate 100, this little metal level 112 ', this little metal level 112 of being formed at covering is with on insulating barrier 108; Several second opening 118, is arranged in one of insulating barrier 116 separatedly, to expose the end face of of one of this little metal level 112 ' respectively and to partially overlap one of this little first opening 110 of below; Several transparency electrode 120, be arranged at intervals at be positioned at this bit by two adjacent and staggered metal levels 106 and two metal levels 112 intersect the several pixel region P defined insulating barrier 116 on, one of transparency conducting layer 120 then fills in one of this little second opening 118, with contact metal layer 112 '.Within this little pixel region P, be then formed with a dot structure respectively.
As shown in Figure 1, along the first direction as X-direction along stretching, this little metal level 106 spaced is respectively as the use of a gate line (gate line), along the second direction as Y-direction along stretching this little metal wire 112 spaced then respectively as the use of a data wire (data line), and this little first opening 110 is as the use of the first contact hole (contact hole), and this little second opening 118 is as the use of the second contact hole.At this, be formed at the use of the pixel electrode for the drain region and follow-up formation that are electrically connected a thin film transistor device of the metal level 112 ' in the first opening 110, and the second opening 118 is overlapping with a part for the first opening 110, thus one of metal level 112 ' is exposed, and the transparency electrode 120 be formed in the second opening 118 partially overlaps metal level 112 and contacts it, and then define electrical connection situation.
Please refer to the schematic diagram of Fig. 2, to show the section situation of the array base palte 10 along 2-2 line segment in Fig. 1 according to an embodiment of the present utility model.
As shown in Figure 2, between semiconductor layer 102 and insulating barrier 108, be also provided with another insulating barrier 104, using the use as the gate insulation layer (gate insulator) in a thin-film transistor.A drain region 102a is then formed within semiconductor layer 102, first opening 110 has then penetrated this insulating barrier 104 and has partly exposed an end face of this drain region 102a, the surface that metal level 112 ' is then conformably formed at insulating barrier 108 fills in the first opening 110, and it covers via the first opening 110 and contacts the end face of the drain region 102a in the side wall surface of the insulating barrier 102 and 104 exposed for the first opening 110 and semiconductor layer 102.
Moreover, the second opening 118 be formed in insulating barrier 116 partially overlaps the first opening 110 in the P of pixel region, and then expose one of the metal level 112 ' be formed on insulating barrier 108 and in this first opening 110, transparency electrode 120 is then except on the end face being formed at insulating barrier 116, and it is also formed at the part contacting the metal level 112 ' exposed for the second opening 118 within the second opening 118.It should be noted that the area of the metal level 112 ' exposed for the second opening 118 is greater than the area of the end face of the semiconductor layer 102 exposed for the first opening 110.In other words, the size of the second opening 118 is greater than the size of the first opening 110.
Situation as Figure 1-Figure 2, by the second opening 118 being formed at the position between the first opening 110 and metal wire 106, so just can increasing the overlay area of the transparency electrode 120 in the P of pixel region, and then increasing the effective vent rate of pixel region P.
Continue referring to Fig. 1-Fig. 2, the first opening 110 in the P of pixel region and the second opening 118 one pull out taper (tapered shape) opening for what have decreasing dimensions from top to bottom.And based on simplicity of illustration object, only show a full-size of this little first opening 110 and the second opening 118 in Fig. 1, and this little first opening 110 and the second opening 118 have a geometric center A and B respectively.
As shown in Figure 1, sight is looked from above, a line A-B between the geometric center B of geometric center A second opening 118 adjacent thereto of this first opening 110 in the P of pixel region and the angle α of 90 degree substantially can be had between metal wire 106, and this line A-B system is perpendicular to metal wire 106.But, in order to more increase the overlay area of the transparency electrode 120 in the P of pixel region and increase the effective vent rate of pixel region P, the then position of adjustable second opening 118, make it comparatively close to the metal wire 112 (as shown in Figure 3) of left or the metal wire 112 (as shown in Figure 4) of right, and then the line A-B between the geometric center B making the geometric center A of the first opening 110 second opening 118 adjacent thereto is no longer perpendicular to metal wire 106, and the angle [alpha] of an on-right angle will be accompanied between this line A-B and metal wire 106.The visual actual demand of this angle [alpha] and be greater than 0 degree and be less than 90 degree.
Please refer to Fig. 5-Fig. 6, show a series of schematic diagrames of a kind of array base palte 10 ' according to another embodiment of the present utility model.Fig. 5 is a upper schematic diagram, and Fig. 6 is then a generalized section, to show the section situation of of the array base palte along 6-6 line segment in Fig. 5.At this, the embodiment of Fig. 5-Fig. 6 obtained by revising the embodiment shown in Fig. 1-Fig. 2, and therefore in Fig. 5-Fig. 6, similar elements adopts shown by identical label, and only explains orally the difference place between itself and Fig. 1-embodiment illustrated in fig. 2 below.
Please refer to Fig. 5, can more adjust be positioned at pixel region P metal level 112 ', semiconductor layer 102 part with and the relevant position of contiguous associated components, make metal level 112 ' and the second opening 118 partially overlap metal wire 106.Therefore, transparency electrode 120 only partly to fill in the second opening 118 and only part covers the end face of insulating barrier 116 and the partial sidewall face of insulating barrier 118 of exposing for the second opening 118 and the end face of metal level 112 ' and side wall surface.
Please refer to Fig. 6, then show the section situation of of the array base palte along 6-6 line segment in Fig. 5, only partly to fill in the second opening 118 and only part covers the end face of insulating barrier 116 and the partial sidewall face of insulating barrier 118 of exposing for the second opening 118 and the end face of metal level 112 ' and side wall surface, the metal level 106 below the metal level 112 ' being positioned at top then partially overlaps and is positioned in this transparency electrode 120.
Continue referring to Fig. 5-Fig. 6, the first opening 110 in the P of pixel region and the second opening 118 across pixel region P and metal wire 106 one pull out taper (taperedshape) opening for what have decreasing dimensions from top to bottom.And based on simplicity of illustration object, only show a full-size of this little first opening 110 and the second opening 118 in Fig. 5, and this little first opening 110 and the second opening 118 have a geometric center A and B respectively.
As shown in Figure 5, sight is looked from above, a line A-B between the geometric center B of geometric center A second opening 118 adjacent thereto of this first opening 110 and angle α of 90 degree substantially can be had between metal wire 106, and this line A-B is perpendicular to metal wire 106.But, in order to more increase the overlay area of the transparency electrode 120 in the P of pixel region and increase the effective vent rate of pixel region P, the then position of adjustable second opening 118, make it comparatively close to the metal wire 112 (as shown in Figure 7) of left or the metal wire 112 (as shown in Figure 8) of right, and then the line A-B between the geometric center B making the geometric center A of the first opening 110 second opening 118 adjacent thereto is no longer perpendicular to metal wire 106, and the angle [alpha] of an on-right angle will be accompanied between this line A-B and metal wire 106.The visual actual demand of this angle [alpha] and be greater than 0 degree and be less than 90 degree.
Similar in appearance to the enforcement situation shown in Fig. 1-Fig. 4, also by the second opening 118 being formed at the position between the first opening 110 and metal wire 106 in array base palte 10 ' in enforcement situation shown in Fig. 5-Fig. 8, to increase the overlay area of the transparency electrode 120 in the P of pixel region, and increase the effective vent rate of pixel region P.
In the embodiment shown in Fig. 1-Fig. 4 Yu Fig. 5-Fig. 8, the material of substrate 100 is such as glass or plastic cement, the material of semiconductor layer 102 is such as polysilicon, the material of insulating barrier 104 and 108 is such as silica, silicon nitride or its combination, and different insulative layer 104 can comprise identical or not identical material with between 108, the material of metal level 106 is such as tungsten or aluminium, insulating barrier 116 comprise as spin-coating glass or isolation material, the material of metal level 112 and metal level 112 ' such as can be formed for tungsten or aluminium simultaneously, and transparency electrode 120 can comprise the transparent conductive material of tin indium oxide (ITO).And the external form of semiconductor layer 102 is also non-is limited with U-shaped, it also can be L shape or other shapes.The making of above-mentioned component can adopt traditional array substrate manufacture technique to complete, therefore at this in detail its relative production is not described in detail.
Please refer to Fig. 9, show a generalized section of a kind of display unit 500 according to an embodiment of the present utility model.
As shown in Figure 9, display unit 500 comprises: array basal plate 300; One transparent substrates 350; And a display layer 400, be arranged between transparent substrates 350 and this array base palte 300.In an embodiment, the array base palte 300 in display unit 500 can comprise array base palte as Figure 1-Figure 8 10 and 10 ', and can also comprise as other components such as common electrode (not shown)s.Such as, and according to the enforcement situation of display unit 500, be liquid crystal indicator or organic LED display device, display layer 400 comprises a liquid crystal layer or an Organic Light Emitting Diode layer.And in display unit 500, according to the enforcement situation of display unit 500, be such as liquid crystal indicator or organic LED display device, transparent substrates 350 also can include other components as colorized optical filtering thing (not shown), and transparent substrates 350 can comprise the light-transmitting materials as glass or plastic cement.
Claims (10)
1. a display unit, is characterized in that, this display unit comprises:
Array base palte, defines the dot structure of multiple arrayed, and those dot structures have respectively:
Semiconductor layer, is positioned on a substrate;
The first metal layer, is positioned on this substrate;
First insulating barrier, is positioned on this semiconductor layer, and this first insulating barrier has the first opening, and this first opening exposes an end face of this semiconductor layer and a side of this first insulating barrier;
Second metal level, is positioned on this first insulating barrier, and is formed at this end face of this semiconductor layer and this side of this first insulating barrier via this first opening; And
Second insulating barrier, be positioned on this second metal level and this first insulating barrier, and this second insulating barrier has the second opening, and wherein, this second opening exposes this second metal level be positioned on this side of this first insulating barrier,
Wherein, this first opening, this second opening and this first metal layer putting in order as this first metal layer, this second opening along a direction, and this first opening.
2. display unit as claimed in claim 1, it is characterized in that, the area of this second metal level that this second opening exposes is greater than the area of this end face of this semiconductor layer that this first opening exposes.
3. display unit as claimed in claim 1, it is characterized in that, this second metal level and this first metal layer partly overlap.
4. display unit as claimed in claim 1, it is characterized in that, this the first metal layer comprises along the spaced first grid polar curve of first direction and a second gate line, and this second metal level comprises along spaced one first data wire of a second direction and one second data wire, this first direction is different from this second direction, this first grid polar curve, this second gate line, this first data wire and this second data line definition one pixel region, this first opening and this second opening are positioned at this pixel region, and this semiconductor layer is electrically connected with this first data wire.
5. display unit as claimed in claim 4, it is characterized in that, this second opening is between this first opening and this first data wire.
6. display unit as claimed in claim 4, it is characterized in that, this second opening portion is overlapped in this first metal layer.
7. display unit as claimed in claim 4, it is characterized in that, this first opening has one first geometric center, and this second opening has one second geometric center, wherein a line of this first geometric center and this second geometric center and this first grid polar curve have an angle, and this angle is greater than 0 degree and is less than 90 degree.
8. display unit as claimed in claim 1, it is characterized in that, this display unit also comprises:
Transparent substrates; And
Display layer, is arranged between this transparent substrates and this array base palte.
9. display unit as claimed in claim 1, it is characterized in that, this display unit also comprises the first transparency electrode, and this first transparency electrode is electrically connected with this second metal level by this second opening.
10. display unit as claimed in claim 8, it is characterized in that, this display layer is a liquid crystal layer or an Organic Light Emitting Diode layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520041234.0U CN204596791U (en) | 2015-01-21 | 2015-01-21 | Display unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520041234.0U CN204596791U (en) | 2015-01-21 | 2015-01-21 | Display unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204596791U true CN204596791U (en) | 2015-08-26 |
Family
ID=53932914
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520041234.0U Active CN204596791U (en) | 2015-01-21 | 2015-01-21 | Display unit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204596791U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105870124A (en) * | 2015-01-21 | 2016-08-17 | 群创光电股份有限公司 | Display device |
| JP2020129113A (en) * | 2015-08-28 | 2020-08-27 | 群創光電股▲ふん▼有限公司Ｉｎｎｏｌｕｘ Ｃｏｒｐｏｒａｔｉｏｎ | Display device |
-
2015
- 2015-01-21 CN CN201520041234.0U patent/CN204596791U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105870124A (en) * | 2015-01-21 | 2016-08-17 | 群创光电股份有限公司 | Display device |
| CN105870124B (en) * | 2015-01-21 | 2019-06-07 | 群创光电股份有限公司 | Display device |
| JP2020129113A (en) * | 2015-08-28 | 2020-08-27 | 群創光電股▲ふん▼有限公司Ｉｎｎｏｌｕｘ Ｃｏｒｐｏｒａｔｉｏｎ | Display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102466933B (en) | Pixel structure of liquid crystal display and method for manufacturing pixel structure | |
| CN103676367B (en) | Display floater and display device | |
| CN109860224B (en) | Display substrate, manufacturing method thereof, display panel and display device | |
| CN102315165B (en) | Edge electric field type liquid crystal display array substrate and manufacture method thereof | |
| CN103488015B (en) | Pixel structure and display panel with same | |
| TWI532154B (en) | Display panel and display device | |
| CN108766976B (en) | Display panel, manufacturing method thereof and display device | |
| US20210303093A1 (en) | Array substrate and method for manufacturing same, and display device | |
| CN111708237B (en) | Array substrate, display panel and display device | |
| US10877307B2 (en) | Display device | |
| WO2021196362A1 (en) | Low temperature poly-silicon display panel and manufacturing method therefor, and liquid crystal display apparatus | |
| WO2022193692A1 (en) | Display panel and display device | |
| CN107870490B (en) | Display device | |
| CN204596791U (en) | Display unit | |
| KR101778364B1 (en) | Display device | |
| CN202126557U (en) | Array substrate | |
| WO2016161700A1 (en) | Thin-film transistor array substrate and manufacturing method therefor | |
| CN103280197B (en) | A kind of array base palte and display floater | |
| CN100444405C (en) | Double grid film electric crystal and pixel structure and its producing method | |
| CN108663862B (en) | Display panel | |
| CN107393873B (en) | Manufacturing method of thin film transistor array substrate | |
| CN100524779C (en) | Thin film transistor module base board and its making method | |
| CN105575978A (en) | Thin film transistor array substrate, and manufacturing method and liquid crystal display apparatus thereof, | |
| CN101493613B (en) | Liquid crystal display panel and image display system using the liquid crystal display panel | |
| CN110518042B (en) | Display substrate, preparation method thereof and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |