CN204576925U - A kind of DSP Digital Signal Processing Experiment case for imparting knowledge to students - Google Patents
A kind of DSP Digital Signal Processing Experiment case for imparting knowledge to students Download PDFInfo
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- CN204576925U CN204576925U CN201520265108.3U CN201520265108U CN204576925U CN 204576925 U CN204576925 U CN 204576925U CN 201520265108 U CN201520265108 U CN 201520265108U CN 204576925 U CN204576925 U CN 204576925U
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Abstract
The utility model provides a kind of DSP Digital Signal Processing Experiment case for imparting knowledge to students, experimental box adopts modular design, except comprising power unit, main control part also comprises USB2.0 OTG module (1) outward, Ethernet card module (5), serial interface module (4), audio A/D/D/A module (2), voice AD/DA module (3), wherein, described power unit can provide 3.3V, 2.5V, 5V, the direct supply of 12V exports, described main control part comprises main control chip, reset circuit and DSP downloader, described reset circuit and DSP downloader are connected with described main control chip, described main control module (6) is connected with experimental box main circuit board with extrapolation form, a kind of DSP Digital Signal Processing Experiment of the utility model case, for student provides a kind of DSP application platform, makes it understand and grasp the basic development technique of dsp chip, and described experimental box has abundant peripheral module, can give full play to the creativeness of student.
Description
Technical field
The utility model relates to technical field of teaching instruments, mainly relates to a kind of DSP Digital Signal Processing Experiment case for imparting knowledge to students.
Background technology
Along with the fast development of electronics technology, dsp chip and digital signal processor, fast with its speed, precision is high, and stability is high, the advantage such as interface and integrated convenience and be widely applied to the every field of life.Dsp chip is not also adopted to combine a large amount of Teaching Experiment Box commonly used module and carry out testing at present, in addition along with DSP widely using in every field, exigence, by improving experimental teaching equipment and teaching method, progressively deepens the understanding of student to DSP, improves student DSP application power.For overcoming the above problems, devise a kind of DSP Digital Signal Processing Experiment of the utility model case.
Utility model content
The purpose of this utility model is to provide a kind of DSP application experiment case, student can be allowed to understand and grasp the basic development technique of dsp chip, the peripheral module that case is abundant by experiment, improving the innovation ability of student;
For overcoming the above problems, a kind of DSP Digital Signal Processing Experiment of the utility model case, comprise power unit, main control part and expansion, main control part and expansion are powered by power unit, wherein, described power unit can provide the direct supply of 3.3V, 2.5V, 5V, 12V to export;
Described main control part comprises main control module and DSP downloader module, and main control module is containing DSP main control chip and reset circuit, and described reset circuit and DSP downloader are connected with described DSP main control chip respectively; Described main control part comprises DSP main control chip, reset circuit and DSP downloader, and described reset circuit is connected with described main control chip respectively with DSP downloader;
Described expansion comprises USB2.0OTG module, audio A/D/D/A module, voice AD/DA module, serial interface module, Ethernet card module, HPI-PC module, two CPLD module, signal generating module (2), loudspeaker module, Signal averaging module, GPIO module, LED module, LCD module, 4*4 Keysheet module;
Described USB2.0OTG module, audio A/D/D/A module, voice AD/DA module, serial interface module, GPIO module, LED module, LCD module, Keysheet module are connected with main control module respectively by the expansion of CPLD module's address, IO expansion;
Described signal generating module (2), loudspeaker module, Signal averaging module is the module that can work independently, as supplementary module, be not connected with DSP main control chip, described signal generating module and Signal averaging model calling, phonetic entry A/D module, audio frequency export D/A module also respectively with Signal averaging model calling, audio frequency exports D/A module multiple output channel, one of them output channel connects loudspeaker module, signal generating module produces at least one signal and exports, the input signal of the signal that signal generating module produces by Signal averaging module and phonetic entry A/D module superposes, output to audio frequency and export D/A module, complete the function of supplementary module.
Described HPI-PC module is connected with PC by HPI parallel port line;
Described USB2.0OTG is connected with PC by USB line;
Described Ethernet card module is connected with PC by netting twine;
Described serial interface module is connected with PC by serial port connecting line;
Described audio A/D/D/A module, voice AD/DA module are connected with loudspeaker module by tone frequency channel wire;
Described power unit is connected with described main control part and expansion respectively;
Described DSP downloader connects PC by USB port;
After adopting above design, the utility model is compared with prior art: the utility model can not only allow student understand dsp chip knowledge, and the basic development technique of dsp chip can also be grasped, experiment is mainly divided into algorithm experimental and interface and Control release two parts, algorithm experimental contains multiple conventional digital signal processing algorithm (convolution, relevant, FFT, DCT, FIR, IIR, LMS), interface and Control release relate to multiple conventional module, and wherein representative is that Ethernet card and ICP/IP protocol are tested and MP3 audio decoder is tested.
Below by drawings and Examples, the technical solution of the utility model is described in further detail.
Accompanying drawing explanation
Above-mentioned is only the general introduction of technical solutions of the utility model, and in order to better understand the utility model, below in conjunction with accompanying drawing and embodiment, the utility model is described in further detail.
Fig. 1 is the structural drawing of the novel a kind of DSP Digital Signal Processing Experiment case of this experiment.
Fig. 2, Fig. 3 are USB2.0OTG module principle figure of the present utility model.
Fig. 4 is the utility model experimental system interface definition schematic diagram.
Fig. 5, Fig. 6 are CPLD module principle figure of the present utility model.
Fig. 7 is LED module schematic diagram of the present utility model.
Fig. 8 is LCD module schematic diagram of the present utility model.
Fig. 9, Figure 10 are Ethernet card module principle figure of the present utility model.
Figure 11, Figure 12, Figure 13 are voice AD/DA module principle figure of the present utility model.
Figure 14 is audio A/D of the present utility model/D/A module schematic diagram.
Embodiment
A kind of DSP Digital Signal Processing Experiment of the utility model case, comprises power unit, main control part, expansion, also has USB connecting line, serial port connecting line, netting twine, parallel port line, tone frequency channel wire.
Power unit provides the direct supply of 3.3V, 2.5V, 5V, 12V to export, and delivers to the modules of experimental box respectively, is used alone for convenience, two master control borads is all provided with independently Power Entry Module, can accesses the direct supply of 5V.
The resource of main control part mainly contains sram chip CY7C1021,8M Flash chip TE39LV800 and reset circuit, the DSP downloader of dsp chip TMS320C5416,64K × 16.TMS320C54x is for realizing low-power consumption, high-performance and custom-designed fixed-point DSP chip, and its circuit is simple and have abundant internal resource, easily operates.The utility model adopts DSP downloader, and the debugging of general DSP is all that hardware is online, and run in DSP internal memory by download program, DSP passes operation information back PC, and PC also sends control, debug command by this serial ports.
Expansion module comprises USB2.0OTG module, audio A/D/D/A module, voice AD/DA module, serial interface module, Ethernet card module, HPI-PC module, two CPLD module, signal generating module (2), loudspeaker module, Signal averaging module, GPIO module, LED module, LCD module, 4*4 Keysheet module, in the process of experiment, because modules of the present utility model is independently, by corresponding line, different functions can be realized.
CPLD module adopts the XC9572 programmable chip of Xilinx company, the bus marco work of this module primary responsibility experimental system, CPLD is made up of completely programmable and/or gate array and macroelement, and/or array Reprogrammable, can realize multiple logic function.
USB2.0OTG module mainly comprises a USB main control chip (IPS1362), USB universal port (H-A), two for realize OTG (point-to-point communication) agreement and OTG (point-to-point communication) port, be OTG-B when making Host (main frame) and the OTG-A being Device respectively, configured the working method of USB system by corresponding wire jumper seat.
The main chip of audio A/D/D/A module is AIC23, AIC23 is high performance audio A/D, D/A amplifying circuit that TI company produces, and peripheral interface operating voltage is 3.3V, and core operational voltage is 1.5V, and under 48kHz sampling rate, A/D converts signal to noise ratio (S/N ratio) can reach 100dB.This module is provided with four jacks, and one group is Line-In (line enters) and Line-Out (line goes out), and another group is Mic-In (microphone enters) and Phone-Out (voice go out).
Voice AD/DA module adopts AD50 chip design, AD50 is TI company produce 16, audiorange (sample frequency is 2K ~ 22.05KHZ), include the analog interface chip of frequency overlapped-resistable filter and reconfigurable filter, the synchronous serial communication interface that it has an energy to be connected with many dsp chips.A timer (adjustment sampling rate and frame synchronization time delay) and controller (adjustment programming gain amplifier, phase-locked loop pll, master slave mode) is also comprised in AD50C sheet.AD50 has two kinds of communication modes, and one is 15+1 mode software application second serial communication, and one switches communication modes with FC.Owing to bothering voice data process, the utility model adopts draws high FC to reach the mode switching communication.
UART interface module adopts asynchronism transceiver chip SC16C550 design according to asynchronous serial communication protocol, the Main Function of this chip is that parallel data is converted to serial data, then by asynchronous serial communication mode, data are sent out, the serial data accepted is converted to parallel data simultaneously.Specify in RS-232-C standard that-5V ~-15V is logical one ,+5V ~+15V is logical zero, therefore adopts MAX3232 to complete the conversion of Transistor-Transistor Logic level and RS-232 level.Can be received by COM Debug Assistant monitoring computer serial ports and send the situation of data in the process of experiment.
Ethernet card module mainly includes Ethernet (Ethernet) control chip RTL8019AS, and module is provided with the network cable jack of a RJ-45 (crossroad 45).RTL8019AS and main frame have 3 kinds of interface modes, and the first is wire jumper pattern, and I/O and the interruption of network interface card are determined by wire jumper.The second is plug and play mode, has software automatically to configure.The third mode is wire jumper free mode, and I/O and the interruption of network interface card are determined by the content in external 93c46.Which kind of mode network interface card uses follow the 65 pin JP of RTL8019AS to determine, this module adopts and draws high 65 pin, makes it be operated in wire jumper pattern.
Signal generating module mainly produces the sound signal of two-way three kinds of different wave by signal generating circuit, comprise square wave, triangular wave and sine wave.Wire jumper in the signal type available modules produced is selected, and amplitude and frequency can be regulated by knob, and two-way audio signal also containing adding circuit, can be added by this module.
GPIO module has 5 light emitting diodes, corresponds to five pins of DSPMcBSP, and this module is used one and latched chip, and draws its sheet and select pin CS as sensing point." 0 " " 1 " signal is inputted by 5416 module McBSP mouths, and the control signal of latch is selected by 5416 module sheets and exported via after the decoding of CPLD module.
Refer to the module of USB2.0OTG shown in Fig. 11, audio A/D/D/A module 2, voice AD/DA module 3, serial interface module 4, Ethernet card module 5, main control module 6, signal generating module (1) 7, signal generating module (2) 8,4*4 Keysheet module 9, LCD module 10, LED module 11, power management module 12, GPIO module 13, experimental box power switch 14, three-core supply socket 15, well 16, HPI-PC module 17.220V civil power is by the general supply by power switch 14 Control release case after three-core supply socket 15.USB2.0OTG module 1, audio A/D/D/A module 2, voice AD/DA module 3, serial interface module 4, Ethernet card module 5, main control module 6, signal generating module (1) 7, signal generating module (2) 8,4*4 Keysheet module 9, LCD module 10, GPIO module 13, HPI-PC module 17 module are independently module, as required, corresponding connecting line is connected.Well 16 can place the instruments such as power lead, downloading wire, Serial Port Line, screwdriver, electric soldering iron.
Referring to CON301 shown in Fig. 2, Fig. 3 is USB (HOST) interface, and CON303 is USB (OTG-HOST) interface, and CON305 is USB (OTG-DEVICE) interface.HOST interface receives 36,41,46,47 pins of ISP1362 respectively, and OTG-HOST interface receives 35,42,49,50 pins of ISP1362 respectively, and OTG-DEVICE interface receives 55,49,50 pins of ISP1362 respectively.D0 ~ D15, the A0 of ISP1362, A1, CS, RW, RD and DSP main control chip are connected, and control bus is connected with CPLD.
Referring to shown in Fig. 4, is the definition of each experimental system interface in figure, if need to expand greater functionality, can connect these I/O ports to required module data port by Du Pont's line.
Refer to Fig. 5, shown in Fig. 6, Fig. 7, CPLD module is mainly responsible for the bus marco work of experimental system.25,26,27,28,29,30,31,32 pins of the input termination CON32 of latch HTC573, export 8 input ends of termination charactron.
Refer to shown in Fig. 8, the sheet choosing end of LCD is connected on 13,14 pins of 164245 chips respectively.Enable Pin L_E connects 19 pins, DI and RW connects 16 respectively, 17 pins, input termination CPLD.
Refer to shown in Fig. 9, Figure 10, this module is Ethernet card module, first configures the IP address of PC in the process of experiment, is configured to 192.168.1.X (except 0,2,255).58,59,45,46 pins of chip RTL8019AS connect 8,6,1,3 pins of network transformer respectively, and CONe01 is mesh.
Refer to shown in Figure 11, Figure 12, Figure 13, AD50 is connected in SPI mode with dsp chip, and AD50 is operated in host mode (M/S=1), provides SCLK (data shifts clock) and FS (frame-synchronizing impulse).Dsp chip works in the slave mode of SPI mode, BCLKX1 and BFSX1 is input pin, is all utilize extraneous clock and shift pulse when connecing data and send out data.
Refer to shown in Figure 14, the realization of this module is mainly divided into two parts, a part is the Bypass function of AIC23, namely from circuit input port (LINEIN) input audio signal, control chip internal register, that input audio signal is directly exported through power amplification by Bypass passage in AIC23, realize simulation to modulating output, another part is the D/A conversion experiment of AIC23, namely the voice data word sent here by DSP, deliver to D/A in AIC23 through musical audio digital interface and be transformed into simulating signal, exported by headphone outlet (HPOUT) through power amplifier.
The utility model combines a large amount of conventional modules from shallow to deeply, detailed describes DSP performance history, this not only allows student understand DSP relevant knowledge, and the skill that DSP develops substantially can also be grasped, experiment is mainly divided into algorithms most in use and interface and Control release two parts, in the process of experiment, not only can improve their manipulative ability and their innovation ability of performance, grasp basic DSP development technique, and the growing CYBERSPACE in they and the external world can be made to integrate with.
The above; it is only preferred embodiment of the present utility model; not do any pro forma restriction to the utility model, those skilled in the art utilize the content of above-mentioned announcement to make a little simple modification, equivalent variations or modification, all drop in protection domain of the present utility model.
Claims (9)
1. the DSP Digital Signal Processing Experiment case for imparting knowledge to students, comprise power unit, main control part and expansion, main control part and expansion are powered by power unit, described main control part comprises DSP main control chip, reset circuit and DSP downloader, and described reset circuit, DSP downloader are connected with described DSP main control chip; Described expansion comprises USB2.0OTG module, audio frequency exports D/A module, phonetic entry A/D module, serial interface module, Ethernet card module, HPI-PC module, two CPLD module, signal generating module, loudspeaker module, Signal averaging module, GPIO module, LED module, LCD module, 4*4 Keysheet module;
Described USB2.0OTG module, audio frequency output D/A module, phonetic entry A/D module, serial interface module, GPIO module, LED module, LCD module, 4*4 Keysheet module are connected with DSP main control chip by two CPLD module, it is characterized in that: signal generating module and Signal averaging module are as supplementary module, be not connected with DSP main control chip, described signal generating module and Signal averaging model calling, phonetic entry A/D module, audio frequency export D/A module also respectively with Signal averaging model calling, audio frequency exports D/A module multiple output channel, one of them output channel connects loudspeaker module, signal generating module produces at least one signal and exports, the input signal of the signal that signal generating module produces by Signal averaging module and phonetic entry A/D module superposes, output to audio frequency and export D/A module, complete the function of supplementary module.
2. DSP Digital Signal Processing Experiment case according to claim 1, is characterized in that: described pair of CPLD module adopts two pieces of XC9572 chips, and XC9572 described in two panels adopts the mode of cascade to connect.
3. DSP Digital Signal Processing Experiment case according to claim 1, is characterized in that: described Ethernet card module is RTL8019AS module, and this module is connected with main control chip by two CPLD module, is connected with PC by netting twine.
4. DSP Digital Signal Processing Experiment case according to claim 1, is characterized in that: described USB2.0OTG module comprises a USB main control chip IPS1362.
5. DSP Digital Signal Processing Experiment case according to claim 1, is characterized in that: described audio frequency exports D/A module and adopts AIC23 chip.
6. DSP Digital Signal Processing Experiment case according to claim 1, is characterized in that: described phonetic entry A/D module adopts AD50 chip.
7. DSP Digital Signal Processing Experiment case according to claim 1, is characterized in that: described DSP downloader connects PC by USB interface.
8. DSP Digital Signal Processing Experiment case according to claim 1, is characterized in that: power unit comprises the DC output power of 3.3V, 2.5V, 5V, 12V.
9. DSP Digital Signal Processing Experiment case according to claim 1, is characterized in that: described signal generating module has 2.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105047051A (en) * | 2015-04-28 | 2015-11-11 | 北京百科融创教学仪器设备有限公司 | Digital signal processing (DSP) experimental box for teaching purpose |
| CN114677868A (en) * | 2022-03-11 | 2022-06-28 | 中国人民解放军陆军装甲兵学院 | Equipment maintenance training system |
| CN114694443A (en) * | 2022-03-11 | 2022-07-01 | 中国人民解放军陆军装甲兵学院 | Equipment maintenance training platform |
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2015
- 2015-04-28 CN CN201520265108.3U patent/CN204576925U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105047051A (en) * | 2015-04-28 | 2015-11-11 | 北京百科融创教学仪器设备有限公司 | Digital signal processing (DSP) experimental box for teaching purpose |
| CN114677868A (en) * | 2022-03-11 | 2022-06-28 | 中国人民解放军陆军装甲兵学院 | Equipment maintenance training system |
| CN114694443A (en) * | 2022-03-11 | 2022-07-01 | 中国人民解放军陆军装甲兵学院 | Equipment maintenance training platform |
| CN114694443B (en) * | 2022-03-11 | 2023-08-15 | 中国人民解放军陆军装甲兵学院 | Equipment maintenance training platform |
| CN114677868B (en) * | 2022-03-11 | 2023-08-15 | 中国人民解放军陆军装甲兵学院 | Equipment maintenance training system |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150819 Termination date: 20200428 |