CN204539307U - The device of VIDEO and the COMMAND function of MIPI signal is realized based on FPGA - Google Patents
The device of VIDEO and the COMMAND function of MIPI signal is realized based on FPGA Download PDFInfo
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Abstract
The utility model discloses a kind of device realizing VIDEO and the COMMAND function of MIPI signal based on FPGA, comprise MIPI control module, RGB modular converter, VIDEO synchronization module, VIDEO blanking control module, VIDEO data module, VIDEO cache module, COMMAND data module, COMMAND cache module, MIPI group are responsible for assigning module, HS transport module, HS signal generator module, LPDT cache module, LPDT transport module and MIPI signal output module.The utility model can realize VIDEO and the COMMAND display mode of MIPI signal simultaneously, conforms to MIPI DSI, DCS, DPHY agreement; VIDEO and the COMMAND mode that the utility model realizes all can send to MIPI module with data-stream form under HS state, and COMMAND mode also can send to MIPI module with LPDT transmission mode under LP state.
Description
Technical field
The utility model relates to display and the field tests of MIPI liquid crystal module, refers to a kind of device realizing VIDEO and the COMMAND function of MIPI signal based on FPGA particularly.
Background technology
Two kinds of display modes are had for MIPI signal and module thereof, one is that vision signal sends to module displays so that continuous data is streamed, i.e. VIDEO mode, another kind is that vision signal issues module displays, i.e. COMMAND pattern with the form of the subsidiary video data of register command.
VIDEO mode is generally used for the video display under most of occasion, be especially embodied in dynamic menu display, the MIPI signal of which is generally transferred to module with differential signal data flow characteristic under HS state.COMMAND mode is generally used on display tableaux, or for module debugging, detection occasion, which both can pass to module with data flow characteristic under HS state, also under LP state, can be transferred to module in LPDT mode.But this display mode needs to carry video data memory module in module, can increase module cost.
Along with the aggravation of market competition, make no matter in the exploitation of module performance or the application of MIPI display device, the module manufacturer more come the more starts to produce and can support that the module of VIDEO and COMMAND display mode is to be in the catbird seat in market simultaneously.But in the debugging, detection of module production, only there is minority picture signal source device could provide the signal of these two kinds of display modes by external bridging chip simultaneously, cause detection scheme technical sophistication, the shortcoming that with high costs, troublesome poeration, reliability are low like this.
Summary of the invention
For the deficiencies in the prior art, the purpose of this utility model is VIDEO and the COMMAND display mode simultaneously realizing MIPI signal in a slice fpga chip according to MIPI DSI and DCS agreement, and makes VIDEO and COMMAND mode all can MIPI module point be sent to shield with data-stream form under HS state according to MIPI DSI agreement.
For achieving the above object, a kind of device realizing VIDEO and the COMMAND function of MIPI signal based on FPGA designed by the utility model, its special character is, comprises MIPI control module, RGB modular converter, VIDEO synchronization module, VIDEO blanking control module, VIDEO data module, VIDEO cache module, COMMAND data module, COMMAND cache module, MIPI group are responsible for assigning module, HS transport module, HS signal generator module, LPDT cache module, LPDT transport module and MIPI signal output module;
Described MIPI control module respectively with RGB modular converter, VIDEO synchronization module, VIDEO blanking control module, MIPI group is responsible for assigning module, HS transport module, HS signal generator module is connected with MIPI signal output module, described RGB modular converter respectively with VIDEO synchronization module, VIDEO data module, COMMAND data module connects, described VIDEO synchronization module to be responsible for assigning model calling by VIDEO blanking control module and MIPI group, described VIDEO data module to be responsible for assigning model calling by VIDEO cache module and MIPI group, described COMMAND data module to be responsible for assigning model calling by COMMAND cache module and MIPI group, the described MIPI group module that is responsible for assigning is connected with HS transport module and LPDT cache module respectively, described HS transport module is connected with MIPI signal output module by HS signal generator module, described LPDT cache module is connected with MIPI signal output module by LPDT transport module, described MIPI signal output module is connected with MIPI module.
Further, described MIPI control module is connected by Ethernet, USB or serial mode with upper strata.
Further, described MIPI control module receives the electric signal of MIPI transmission configuration parameter by the I/O cell input of FPGA.
The beneficial effects of the utility model are:
(1) the utility model can realize VIDEO and the COMMAND display mode of MIPI signal simultaneously, conforms to MIPI DSI, DCS, DPHY agreement.
(2) VIDEO and the COMMAND mode that the utility model realizes all can send to MIPI module with data-stream form under HS state, and COMMAND mode also can send to MIPI module with LPDT transmission mode under LP state.
(3) the utility model is applicable to the MIPI module of different resolution, size, different RGB color characteristics, different MIPI transfer rate, can be applicable to the MIPI module of 1 ~ 4LANE.Be applicable to the MIPI module of different VIDEO display mode (Burst and Non-burst), different COMMAND display mode (point line mode, segmented mode, full frame mode), and the reliable inerrancy of Signal transmissions.
(4) associative operation configuration (as MIPI module configuration-direct, RGB configuration parameter, VIDEO mode, COMMAND mode configuration parameter etc., video transmission manner) needed for the utility model all can be configured by upper layer software (applications), thus make easy and simple to handle, quick, again without the need to Artificial Control after configuration completes.
(5) the utility model is by realizing described function with fpga chip; FPGA is the common chip in market, and not only working stability is reliable for the utility model, realization is easy, and it is lower to realize cost, avoids the problem such as design, use complexity, poor stability, design cost height caused because using the technical scheme of external bridging chip.
Accompanying drawing explanation
Fig. 1 is the utility model realizes the device of VIDEO and the COMMAND function of MIPI signal circuit block diagram based on FPGA;
Fig. 2 is the transmission means of the two kind blanking pattern of VIDEO video data under HSDT transmission means.
In figure: MIPI control module 1, RGB modular converter 2, VIDEO synchronization module 3, VIDEO blanking control module 4, VIDEO data module 5, VIDEO cache module 6, COMMAND data module 7, COMMAND cache module 8, MIPI group is responsible for assigning module 9, HS transport module 10, HS signal generator module 11, LPDT cache module 12, LPDT transport module 13, MIPI signal output module 14, MIPI module 15.
Embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.
As shown in Figure 1, the device realizing VIDEO and the COMMAND function of MIPI signal based on FPGA provided by the utility model, comprises MIPI control module 1, RGB modular converter 2, VIDEO synchronization module 3, VIDEO blanking control module 4, VIDEO data module 5, VIDEO cache module 6, COMMAND data module 7, COMMAND cache module 8, MIPI group is responsible for assigning module 9, HS transport module 10, HS signal generator module 11, LPDT cache module 12, LPDT transport module 13 and MIPI signal output module 14.
MIPI control module 1 respectively with RGB modular converter 2, VIDEO synchronization module 3, VIDEO blanking control module 4, MIPI group is responsible for assigning module 9, HS transport module 10, HS signal generator module 11 is connected with MIPI signal output module 14, RGB modular converter 2 respectively with VIDEO synchronization module 3, VIDEO data module 5, COMMAND data module 7 connects, VIDEO synchronization module 3 is connected by VIDEO blanking control module 4 and the MIPI group module 9 that is responsible for assigning, VIDEO data module 5 is connected by VIDEO cache module 6 and the MIPI group module 9 that is responsible for assigning, COMMAND data module 7 is connected by COMMAND cache module 8 and the MIPI group module 9 that is responsible for assigning, the MIPI group module 9 that is responsible for assigning is connected with HS transport module 10 and LPDT cache module 12 respectively, HS transport module 10 is connected with MIPI signal output module 14 by HS signal generator module 11, LPDT cache module 12 is connected with MIPI signal output module 14 by LPDT transport module 13, MIPI signal output module 14 is connected with MIPI module 11.
MIPI control module 1 for produce configuration parameter according to upper-layer configured control signal and be sent to RGB modular converter 2, VIDEO synchronization module 3, VIDEO blanking control module 4, MIPI group are responsible for assigning module 9, HS transport module 10, HS signal generator module 11 and MIPI signal output module 14.
RGB modular converter 2 is for being converted to rgb video signal by the video transfer signal of input.
VIDEO synchronization module 3 starts and terminates the synchronous short bag of mark for producing frame/row according to the synchronizing signal in rgb video signal.
VIDEO blanking control module 4 for producing Burst pattern synchronization information or Non-Burst pattern synchronization information according to the blanking pattern signal in synchronizing signal, and is processed into LP mark or empty bag.
Video data in rgb video signal is converted to VIDEO data by VIDEO data module 5.
VIDEO cache module 6 is for buffer memory VIDEO data.
COMMAND data module 7 is for being COMMAND data by the rgb video signal of input and instruction transformation of spreading its tail.
COMMAND cache module 8 is for by buffer memory COMMAND data.
MIPI group is responsible for assigning module 9 for synchronizing signal being produced frame/row and start and terminate the synchronous short bag of mark, LP mark or empty bag and the long bag of VIDEO data composition MIPI data being sent to HS transport module 10, and then the COMMAND data of buffer memory are sent to HS transport module 10 and LPDT cache module 12 according to configuration parameter respectively according to the long bag of MIPI DCS agreement composition MIPI data.
HS transport module 10 for the long bag of reception MIPI data is converted to MIPI serial data, and generates MIPI HS clock signal and MIPI HS data-signal according to the transmission time sequence of configuration parameter.
HS signal generator module 11 is for receiving MIPI HS clock signal and MIPI HS data-signal and exporting the LP level signal under MIPI HS clock signal under HS state and MIPI HS data-signal and LP state respectively according to the transmission time sequence in configuration parameter.
The MIPI packet that LPDT cache module 12 receives for buffer memory.
LPDT transport module 13 is for converting standard MIPILPDT data-signal to by the MIPI packet of buffer memory and export.
MIPI signal output module 14 is for exporting MIPI HS clock signal under the HS state that receives and MIPI HS data-signal or MIPI LPDT data-signal to MIPI module 15 according to the transmission time sequence in configuration parameter.
The concrete steps realizing realizing based on FPGA the method for VIDEO and the COMMAND function of MIPI signal according to this device comprise:
1) upper strata (can be MCU, PC or other control appliances) first sets configuration information, and by common interfaces such as Ethernet, serial ports, USB, upper-layer configured control signal is sent to MIPI control module 1.MIPI control module 1 receives the electric signal of MIPI transmission configuration parameter by the I/O cell input of FPGA.MIPI control module 1 again its configuration information is reduced into each configuration parameter and other correlation modules are given in instruction.These configuration parameters comprise VIDEO or COMMAND display mode, MIPI module spreads its tail instruction, RGB color bit wide, RGB component order, module data LANE number, COMMAND transmission means, Signal transmissions sequential, transmission rate, output electric parameter etc.
2) module is spread its tail by MIPI control module 1, and to send into that COMMAND data module 7 converts thereof into COMMAND data and send into the MIPI group module 9 groups of bags that are responsible for assigning be MIPI packet in instruction, then MIPI packet sent into LPDT cache module 12 buffer memory, be then converted to LPDT data-signal through LPDT transport module 13 and export MIPI module 15 to by MIPI signal output module 14 again and complete step of spreading its tail.
3) MIPI control module 1 starts RGB modular converter 2 receiver, video signal transmission, and video transfer signal includes but not limited to LVDS vision signal, and the video transfer signal of reception is converted to rgb video signal by RGB modular converter 2.
4) MIPI control module 1 starts VIDEO synchronization module 3, VIDEO blanking control module 4, VIDEO data module 5, VIDEO cache module 6, COMMAND data module 7, COMMAND cache module 8 according to VIDEO or the COMMAND display mode in configuration parameter.
5) when being VIDEO display mode in configuration parameter, the synchronizing signal in rgb video signal is taken out by VIDEO synchronization module 3 and VIDEO blanking control module 4, completes VIDEO transmission configuration according to synchronizing signal.Concrete steps comprise:
5.1) VIDEO synchronization module 3 takes out frame synchronizing signal in the synchronizing signal of rgb video signal and line synchronizing signal, VIDEO synchronization module 3 is according to the VIDEO mode configuration information in the configuration parameter of MIPI DSI agreement and MIPI control module 1, to frame synchronizing signal (VSYNC) line synchronizing signal (HSYNC, DE) in synchronizing signal, catch their synchronizing signal original position or end position, and calculate the length of the pulsewidth valid interval of respective synchronizing signal, and by these two information VIDEO blanking control modules 4.
5.2) the blanking pattern signal that VIDEO blanking control module 4 configures according to the VIDEO mode in the configuration parameter of MIPI control module 1 produces Burst pattern synchronization information or Non-Burst pattern synchronization information, blanking interval between frame or the pulsewidth phase of going or data (DE) is processed into corresponding LP to identify or empty bag, as shown in Figure 2.
5.3) then specify to produce MIPI frame/row according to MIPI DSI agreement when VIDEO blanking control module 4 receives original position or the end position of the synchronous or frame synchronization of row that VIDEO synchronization module 3 sends here to start or the synchronizing information that terminates to identify is given MIPI group and to be responsible for assigning module 9.Frame/row synchronizing information is processed into the short bag of MIPI and arranges according to LANE number by the MIPI group module 9 that is responsible for assigning again, is assigned to and each data LANE passes out to subsequent module for processing becomes MIPI signal to issue MIPI module 15.
5.4) LP mark or empty bag are issued MIPI group and to be responsible for assigning module 9 by VIDEO blanking control module 4, the MIPI group module 9 that is responsible for assigning becomes MIPI sky bag and is dealt into simultaneously all data LANE send into subsequent module again to change into corresponding MIPI signal according to empty bag identification process, if LP mark then informs that subsequent module proceeds to LP state again.
6) VIDEO data module 5 is according to VIDEO transmission configuration, the video data in described rgb video signal is converted to VIDEO data then buffer memory.
When VIDEO synchronization module 3 and VIDEO blanking control module 4 process RGB synchronizing signal, VIDEO data module 5 is changed into the byte data needed for MIPI group bag when RGB data arrives, and according in the configuration parameter of MIPI control module 1 RGB color bit wide (6,8,10,12,16bit), RGB component order to split RGB data and resets, and sends into VIDEO cache module 6 buffer memory afterwards.
7) by the long bag of the VIDEO data of VIDEO cache module 6 buffer memory composition MIPI data.
Be responsible for assigning in MIPI group from VIDEO cache module 6, after module 9 pairs of sync packet and empty bag process, then read that MIPI byte data composition MIPI data are long wraps and be assigned on each data LANE, then send into subsequent module and be output into MIPI signal.For ensureing the data stream transmitting continuity of VIDEO mode, VIDEO data module 5, VIDEO cache module 6, the MIPI group module 9 that is responsible for assigning adopts ping-pong operation mode to carry out the read/write RGB data that often row is processed simultaneously.
10 are gone to step) after completing.
8) when being COMMAND display mode in configuration controling parameters, the rgb video signal that RGB modular converter 2 exports is converted to buffer memory after COMMAND data.Concrete steps comprise:
8.1) COMMAND data module 7 exports COMMAND cache module 8 buffer memory to after the first row view data of a two field picture is converted to COMMAND data in rgb video signal, and inserts DCS order 2C in MIPI DCS agreement is on first Data Position of the first row COMMAND data of buffer memory.
8.2) the next line view data in described rgb video signal is converted to buffer memory after COMMAND data by COMMAND data module 7 successively, and in every a line COMMAND data of buffer memory, inserts DCS order 3C according to MIPI DCS agreement.
9) the MIPI group a line COMMAND data that module 9 reads buffer memory in COMMAND cache module 8 successively that are responsible for assigning are formed the long bag of MIPI data.
The MIPI group module 9 that is responsible for assigning forms in the process of the long bag of MIPI data, according to the front and back position of R, G, B component of each video data of RGB component arranged in order parameter adjustment.The MIPI group module 9 that is responsible for assigning is that the RGB component of the video data of 12bit, 16bit splits into two high low bytes and inserts successively to color range according to described RGB color bit wide configuration parameter.
10) when MIPI control module 1 is HSDT transmission mode from the Signal transmissions sequential the configuration parameter that upper strata receives, MIPI control module 1 starts MIPI group module 9, HS transport module 10, HS signal generator module 11 and the MIPI signal output module 14 that be responsible for assigning and carries out associative operation.
Due to FPGA work time, front and continued module has time delay, if module 9 is when next line data not yet arrive after current line group bag completes therefore MIPI group is responsible for assigning, automatically insert MIPI sky bag with the transmission rate maintaining HSDT, therefore MIPI group is responsible for assigning module 9 all in work when frame data export, these data and empty bag are then sent to MIPI module 15 so that HSDT data flow is continual, until all frame data are all transmitted by follow-up HS transport module 10, HS signal generator module 11.
Concrete steps comprise:
10.1) the long bag of reception MIPI data is converted to MIPI serial data by HS transport module 10, and generate MIPI HS clock signal and MIPI HS data-signal according to the transmission time sequence of configuration parameter, then HS mode signal generator module 7 exports MIPI HS clock signal and MIPI HS data-signal to MIPI signal output module 14.
10.2) HS signal generator module 11 exports the LP level signal under MIPI HS clock signal under HS state and MIPI HS data-signal and LP state respectively according to the transmission time sequence in configuration parameter.According to MIPI DPHY agreement, the transmission that HS signal generator module 11 produces HS state according to transmission time sequence controls, and when transmission MIPI HS data-signal then enters HSDT transmission, then outputs signal enter LP level signal state when not receiving data.Namely LP level signal state exports the LP level signal state (LP11-02-00) into LVCOMS level.
11) when MIPI control module 1 is LPDT transmission mode from the Signal transmissions sequential the configuration parameter that upper strata receives, MIPI control module 1 starts MIPI group module 9, LPDT cache module 12, LPDT transport module 13 and the MIPI signal output module 14 that be responsible for assigning and carries out associative operation.Concrete steps comprise:
11.1) the MIPI group a line COMMAND data that module 9 reads buffer memory in COMMAND cache module 8 successively that are responsible for assigning are formed the long bag of MIPI data, and give LPDT cache module 12 buffer memory by long for MIPI data bag.
11.2) after LPDT cache module 12 buffer memory completes, then wait for the some time, start LPDT transport module 13 after interval time operate when reaching to send.
11.3) LPDT transport module 13 specifies according to MIPI DPHY agreement upon actuation, each byte data of long for the MIPI data of institute's buffer memory in LPDT cache module 12 bag is taken out in turn and carries out one by one and turn string operation, export in a serial fashion, the LPDT coded system that these serial data all specify according to MIPI DPHY agreement is converted to MIPI LPDT data-signal and exports MIPI signal output module 14 to, and arranges the corresponding serial transmission speed of formation by the transmission rate of configuration parameter in MIPI control module 1.
11.4) MIPI signal output module 14 upon actuation, according to the control of Signal transmissions sequential in the configuration parameter that MIPI control module 1 sends, by MIPI HS clock signal and the MIPI HS data-signal of two kinds of transmission meanss (HSDT mode and LPDT mode) that receive and MIPI LPDT data-signal according to together with MIPI DHPY protocol integration, the MIPI signal transmission forming standard is sent to MIPI module 15 and shows.
12) check whether new image input, do not input then pausing operation, have input then to repeat step 4) ~ 11).Modules of the present utility model is all break-ofves after the current frame data of piece image is transferred to module, until again these frame data of this image are sent to MIPI module 15 again again during the initial arrival of a new frame of lower piece image.
Below be only preferred implementation of the present utility model; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the utility model principle; can also design some improvement, these improvement also should be considered as protection range of the present utility model.
The content that this specification is not described in detail belongs to the known prior art of professional and technical personnel in the field.
Claims (3)
1. one kind realizes the device of VIDEO and the COMMAND function of MIPI signal based on FPGA, it is characterized in that: comprise MIPI control module (1), RGB modular converter (2), VIDEO synchronization module (3), VIDEO blanking control module (4), VIDEO data module (5), VIDEO cache module (6), COMMAND data module (7), COMMAND cache module (8), MIPI group is responsible for assigning module (9), HS transport module (10), HS signal generator module (11), LPDT cache module (12), LPDT transport module (13) and MIPI signal output module (14),
Described MIPI control module (1) respectively with RGB modular converter (2), VIDEO synchronization module (3), VIDEO blanking control module (4), MIPI group is responsible for assigning module (9), HS transport module (10), HS signal generator module (11) is connected with MIPI signal output module (14), described RGB modular converter (2) respectively with VIDEO synchronization module (3), VIDEO data module (5), COMMAND data module (7) connects, described VIDEO synchronization module (3) is connected by VIDEO blanking control module (4) and the MIPI group module (9) that is responsible for assigning, described VIDEO data module (5) is connected by VIDEO cache module (6) and the MIPI group module (9) that is responsible for assigning, described COMMAND data module (7) is connected by COMMAND cache module (8) and the MIPI group module (9) that is responsible for assigning, the described MIPI group module (9) that is responsible for assigning is connected with HS transport module (10) and LPDT cache module (12) respectively, described HS transport module (10) is connected with MIPI signal output module (14) by HS signal generator module (11), described LPDT cache module (12) is connected with MIPI signal output module (14) by LPDT transport module (13), described MIPI signal output module (14) is connected with MIPI module (15).
2. the device realizing VIDEO and the COMMAND function of MIPI signal based on FPGA according to claim 1, is characterized in that: described MIPI control module (1) is connected by Ethernet, USB or serial mode with upper strata.
3. the device realizing VIDEO and the COMMAND function of MIPI signal based on FPGA according to claims 1 or 2, is characterized in that: described MIPI control module (1) receives the electric signal of MIPI transmission configuration parameter by the I/O cell input of FPGA.
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| US11063737B2 (en) | 2016-04-20 | 2021-07-13 | Sony Corporation | Reception device, transmission device, communication system, signal reception method, signal transmission method, and communication method |
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| US11063737B2 (en) | 2016-04-20 | 2021-07-13 | Sony Corporation | Reception device, transmission device, communication system, signal reception method, signal transmission method, and communication method |
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Address after: 430070 Hubei City, Hongshan Province, South Lake Road, No. 53, Hongshan Venture Center, building on the 4 floor, No. Patentee after: Wuhan fine test electronics group Limited by Share Ltd Address before: 430070 Hubei City, Hongshan Province, South Lake Road, No. 53, Hongshan Venture Center, building on the 4 floor, No. Patentee before: Wuhan Jingce Electronic Technology Co., Ltd. |